Lines Matching +full:iref +full:- +full:enable
1 // SPDX-License-Identifier: MIT
196 * the range value for them is (actual_value - 2).
308 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
309 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
313 * divided-down version of it.
318 clock->m = clock->m2 + 2; in pnv_calc_dpll_params()
319 clock->p = clock->p1 * clock->p2; in pnv_calc_dpll_params()
321 clock->vco = clock->n == 0 ? 0 : in pnv_calc_dpll_params()
322 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in pnv_calc_dpll_params()
323 clock->dot = clock->p == 0 ? 0 : in pnv_calc_dpll_params()
324 DIV_ROUND_CLOSEST(clock->vco, clock->p); in pnv_calc_dpll_params()
326 return clock->dot; in pnv_calc_dpll_params()
331 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
336 clock->m = i9xx_dpll_compute_m(clock); in i9xx_calc_dpll_params()
337 clock->p = clock->p1 * clock->p2; in i9xx_calc_dpll_params()
339 clock->vco = clock->n + 2 == 0 ? 0 : in i9xx_calc_dpll_params()
340 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); in i9xx_calc_dpll_params()
341 clock->dot = clock->p == 0 ? 0 : in i9xx_calc_dpll_params()
342 DIV_ROUND_CLOSEST(clock->vco, clock->p); in i9xx_calc_dpll_params()
344 return clock->dot; in i9xx_calc_dpll_params()
349 clock->m = clock->m1 * clock->m2; in vlv_calc_dpll_params()
350 clock->p = clock->p1 * clock->p2 * 5; in vlv_calc_dpll_params()
352 clock->vco = clock->n == 0 ? 0 : in vlv_calc_dpll_params()
353 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in vlv_calc_dpll_params()
354 clock->dot = clock->p == 0 ? 0 : in vlv_calc_dpll_params()
355 DIV_ROUND_CLOSEST(clock->vco, clock->p); in vlv_calc_dpll_params()
357 return clock->dot; in vlv_calc_dpll_params()
362 clock->m = clock->m1 * clock->m2; in chv_calc_dpll_params()
363 clock->p = clock->p1 * clock->p2 * 5; in chv_calc_dpll_params()
365 clock->vco = clock->n == 0 ? 0 : in chv_calc_dpll_params()
366 DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), clock->n << 22); in chv_calc_dpll_params()
367 clock->dot = clock->p == 0 ? 0 : in chv_calc_dpll_params()
368 DIV_ROUND_CLOSEST(clock->vco, clock->p); in chv_calc_dpll_params()
370 return clock->dot; in chv_calc_dpll_params()
375 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in i9xx_pll_refclk()
376 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i9xx_pll_refclk()
378 if ((hw_state->dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) in i9xx_pll_refclk()
379 return i915->display.vbt.lvds_ssc_freq; in i9xx_pll_refclk()
391 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_dpll_get_hw_state()
392 struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; in i9xx_dpll_get_hw_state()
398 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) in i9xx_dpll_get_hw_state()
399 tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe]; in i9xx_dpll_get_hw_state()
402 DPLL_MD(dev_priv, crtc->pipe)); in i9xx_dpll_get_hw_state()
404 hw_state->dpll_md = tmp; in i9xx_dpll_get_hw_state()
407 hw_state->dpll = intel_de_read(dev_priv, DPLL(dev_priv, crtc->pipe)); in i9xx_dpll_get_hw_state()
410 hw_state->fp0 = intel_de_read(dev_priv, FP0(crtc->pipe)); in i9xx_dpll_get_hw_state()
411 hw_state->fp1 = intel_de_read(dev_priv, FP1(crtc->pipe)); in i9xx_dpll_get_hw_state()
413 /* Mask out read-only status bits. */ in i9xx_dpll_get_hw_state()
414 hw_state->dpll &= ~(DPLL_LOCK_VLV | in i9xx_dpll_get_hw_state()
423 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_crtc_clock_get()
424 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_crtc_clock_get()
425 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i9xx_crtc_clock_get()
426 u32 dpll = hw_state->dpll; in i9xx_crtc_clock_get()
433 fp = hw_state->fp0; in i9xx_crtc_clock_get()
435 fp = hw_state->fp1; in i9xx_crtc_clock_get()
439 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; in i9xx_crtc_clock_get()
464 drm_dbg_kms(&dev_priv->drm, in i9xx_crtc_clock_get()
479 lvds_pipe == crtc->pipe) { in i9xx_crtc_clock_get()
510 crtc_state->port_clock = port_clock; in i9xx_crtc_clock_get()
515 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_crtc_clock_get()
516 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_crtc_clock_get()
517 enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); in vlv_crtc_clock_get()
518 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); in vlv_crtc_clock_get()
519 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in vlv_crtc_clock_get()
525 if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0) in vlv_crtc_clock_get()
538 crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock); in vlv_crtc_clock_get()
543 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_crtc_clock_get()
544 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in chv_crtc_clock_get()
545 enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); in chv_crtc_clock_get()
546 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); in chv_crtc_clock_get()
547 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in chv_crtc_clock_get()
553 if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0) in chv_crtc_clock_get()
572 crtc_state->port_clock = chv_calc_dpll_params(refclk, &clock); in chv_crtc_clock_get()
583 if (clock->n < limit->n.min || limit->n.max < clock->n) in intel_pll_is_valid()
585 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) in intel_pll_is_valid()
587 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) in intel_pll_is_valid()
589 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) in intel_pll_is_valid()
595 if (clock->m1 <= clock->m2) in intel_pll_is_valid()
600 if (clock->p < limit->p.min || limit->p.max < clock->p) in intel_pll_is_valid()
602 if (clock->m < limit->m.min || limit->m.max < clock->m) in intel_pll_is_valid()
606 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) in intel_pll_is_valid()
611 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) in intel_pll_is_valid()
622 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in i9xx_select_p2_div()
626 * For LVDS just rely on its current settings for dual-channel. in i9xx_select_p2_div()
631 return limit->p2.p2_fast; in i9xx_select_p2_div()
633 return limit->p2.p2_slow; in i9xx_select_p2_div()
635 if (target < limit->p2.dot_limit) in i9xx_select_p2_div()
636 return limit->p2.p2_slow; in i9xx_select_p2_div()
638 return limit->p2.p2_fast; in i9xx_select_p2_div()
658 struct drm_device *dev = crtc_state->uapi.crtc->dev; in i9xx_find_best_dpll()
666 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; in i9xx_find_best_dpll()
668 for (clock.m2 = limit->m2.min; in i9xx_find_best_dpll()
669 clock.m2 <= limit->m2.max; clock.m2++) { in i9xx_find_best_dpll()
672 for (clock.n = limit->n.min; in i9xx_find_best_dpll()
673 clock.n <= limit->n.max; clock.n++) { in i9xx_find_best_dpll()
674 for (clock.p1 = limit->p1.min; in i9xx_find_best_dpll()
675 clock.p1 <= limit->p1.max; clock.p1++) { in i9xx_find_best_dpll()
684 clock.p != match_clock->p) in i9xx_find_best_dpll()
687 this_err = abs(clock.dot - target); in i9xx_find_best_dpll()
716 struct drm_device *dev = crtc_state->uapi.crtc->dev; in pnv_find_best_dpll()
724 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; in pnv_find_best_dpll()
726 for (clock.m2 = limit->m2.min; in pnv_find_best_dpll()
727 clock.m2 <= limit->m2.max; clock.m2++) { in pnv_find_best_dpll()
728 for (clock.n = limit->n.min; in pnv_find_best_dpll()
729 clock.n <= limit->n.max; clock.n++) { in pnv_find_best_dpll()
730 for (clock.p1 = limit->p1.min; in pnv_find_best_dpll()
731 clock.p1 <= limit->p1.max; clock.p1++) { in pnv_find_best_dpll()
740 clock.p != match_clock->p) in pnv_find_best_dpll()
743 this_err = abs(clock.dot - target); in pnv_find_best_dpll()
772 struct drm_device *dev = crtc_state->uapi.crtc->dev; in g4x_find_best_dpll()
783 max_n = limit->n.max; in g4x_find_best_dpll()
785 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { in g4x_find_best_dpll()
787 for (clock.m1 = limit->m1.max; in g4x_find_best_dpll()
788 clock.m1 >= limit->m1.min; clock.m1--) { in g4x_find_best_dpll()
789 for (clock.m2 = limit->m2.max; in g4x_find_best_dpll()
790 clock.m2 >= limit->m2.min; clock.m2--) { in g4x_find_best_dpll()
791 for (clock.p1 = limit->p1.max; in g4x_find_best_dpll()
792 clock.p1 >= limit->p1.min; clock.p1--) { in g4x_find_best_dpll()
801 this_err = abs(clock.dot - target); in g4x_find_best_dpll()
832 return calculated_clock->p > best_clock->p; in vlv_PLL_is_optimal()
839 abs(target_freq - calculated_clock->dot), in vlv_PLL_is_optimal()
846 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { in vlv_PLL_is_optimal()
866 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_find_best_dpll()
867 struct drm_device *dev = crtc->base.dev; in vlv_find_best_dpll()
871 int max_n = min(limit->n.max, refclk / 19200); in vlv_find_best_dpll()
877 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { in vlv_find_best_dpll()
878 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { in vlv_find_best_dpll()
879 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; in vlv_find_best_dpll()
880 clock.p2 -= clock.p2 > 10 ? 2 : 1) { in vlv_find_best_dpll()
883 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { in vlv_find_best_dpll()
924 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_find_best_dpll()
925 struct drm_device *dev = crtc->base.dev; in chv_find_best_dpll()
942 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { in chv_find_best_dpll()
943 for (clock.p2 = limit->p2.p2_fast; in chv_find_best_dpll()
944 clock.p2 >= limit->p2.p2_slow; in chv_find_best_dpll()
945 clock.p2 -= clock.p2 > 10 ? 2 : 1) { in chv_find_best_dpll()
983 crtc_state->port_clock, refclk, in bxt_find_best_dpll()
989 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp()
994 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
999 return (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; in i965_dpll_md()
1007 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_dpll()
1008 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_dpll()
1020 dpll |= (crtc_state->pixel_multiplier - 1) in i9xx_dpll()
1033 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_dpll()
1034 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in i9xx_dpll()
1036 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; in i9xx_dpll()
1037 WARN_ON(reduced_clock->p1 != clock->p1); in i9xx_dpll()
1039 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_dpll()
1040 WARN_ON(reduced_clock->p1 != clock->p1); in i9xx_dpll()
1043 switch (clock->p2) { in i9xx_dpll()
1057 WARN_ON(reduced_clock->p2 != clock->p2); in i9xx_dpll()
1062 if (crtc_state->sdvo_tv_clock) in i9xx_dpll()
1077 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_compute_dpll()
1078 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_compute_dpll()
1079 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i9xx_compute_dpll()
1082 hw_state->fp0 = pnv_dpll_compute_fp(clock); in i9xx_compute_dpll()
1083 hw_state->fp1 = pnv_dpll_compute_fp(reduced_clock); in i9xx_compute_dpll()
1085 hw_state->fp0 = i9xx_dpll_compute_fp(clock); in i9xx_compute_dpll()
1086 hw_state->fp1 = i9xx_dpll_compute_fp(reduced_clock); in i9xx_compute_dpll()
1089 hw_state->dpll = i9xx_dpll(crtc_state, clock, reduced_clock); in i9xx_compute_dpll()
1092 hw_state->dpll_md = i965_dpll_md(crtc_state); in i9xx_compute_dpll()
1100 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i8xx_dpll()
1101 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i8xx_dpll()
1107 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_dpll()
1109 if (clock->p1 == 2) in i8xx_dpll()
1112 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_dpll()
1113 if (clock->p2 == 4) in i8xx_dpll()
1116 WARN_ON(reduced_clock->p1 != clock->p1); in i8xx_dpll()
1117 WARN_ON(reduced_clock->p2 != clock->p2); in i8xx_dpll()
1123 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock in i8xx_dpll()
1124 * Enable) must be set to “1” in both the DPLL A Control Register in i8xx_dpll()
1125 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)." in i8xx_dpll()
1148 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i8xx_compute_dpll()
1150 hw_state->fp0 = i9xx_dpll_compute_fp(clock); in i8xx_compute_dpll()
1151 hw_state->fp1 = i9xx_dpll_compute_fp(reduced_clock); in i8xx_compute_dpll()
1153 hw_state->dpll = i8xx_dpll(crtc_state, clock, reduced_clock); in i8xx_compute_dpll()
1159 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in hsw_crtc_compute_clock()
1179 if (!crtc_state->has_pch_encoder) in hsw_crtc_compute_clock()
1180 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in hsw_crtc_compute_clock()
1188 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in hsw_crtc_get_shared_dpll()
1214 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in dg2_crtc_compute_clock()
1233 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); in mtl_crtc_compute_clock()
1235 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in mtl_crtc_compute_clock()
1243 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_fb_cb_factor()
1244 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in ilk_fb_cb_factor()
1247 ((intel_panel_use_ssc(display) && i915->display.vbt.lvds_ssc_freq == 100000) || in ilk_fb_cb_factor()
1251 if (crtc_state->sdvo_tv_clock) in ilk_fb_cb_factor()
1259 return dpll->m < factor * dpll->n; in ilk_needs_fb_cb_tune()
1278 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_dpll()
1279 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_dpll()
1289 dpll |= (crtc_state->pixel_multiplier - 1) in ilk_dpll()
1301 * SDVO/HDMI/DP, but we also enable it for CRT to make it in ilk_dpll()
1311 * this on ILK at all since it has a fixed DPLL<->pipe mapping. in ilk_dpll()
1318 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ilk_dpll()
1320 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in ilk_dpll()
1322 switch (clock->p2) { in ilk_dpll()
1336 WARN_ON(reduced_clock->p2 != clock->p2); in ilk_dpll()
1351 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in ilk_compute_dpll()
1354 hw_state->fp0 = ilk_dpll_compute_fp(clock, factor); in ilk_compute_dpll()
1355 hw_state->fp1 = ilk_dpll_compute_fp(reduced_clock, factor); in ilk_compute_dpll()
1357 hw_state->dpll = ilk_dpll(crtc_state, clock, reduced_clock); in ilk_compute_dpll()
1364 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in ilk_crtc_compute_clock()
1372 if (!crtc_state->has_pch_encoder) in ilk_crtc_compute_clock()
1377 drm_dbg_kms(&dev_priv->drm, in ilk_crtc_compute_clock()
1379 dev_priv->display.vbt.lvds_ssc_freq); in ilk_crtc_compute_clock()
1380 refclk = dev_priv->display.vbt.lvds_ssc_freq; in ilk_crtc_compute_clock()
1398 if (!crtc_state->clock_set && in ilk_crtc_compute_clock()
1399 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in ilk_crtc_compute_clock()
1400 refclk, NULL, &crtc_state->dpll)) in ilk_crtc_compute_clock()
1401 return -EINVAL; in ilk_crtc_compute_clock()
1403 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); in ilk_crtc_compute_clock()
1405 ilk_compute_dpll(crtc_state, &crtc_state->dpll, in ilk_crtc_compute_clock()
1406 &crtc_state->dpll); in ilk_crtc_compute_clock()
1412 crtc_state->port_clock = crtc_state->dpll.dot; in ilk_crtc_compute_clock()
1413 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in ilk_crtc_compute_clock()
1425 if (!crtc_state->has_pch_encoder) in ilk_crtc_get_shared_dpll()
1433 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_dpll()
1439 if (crtc->pipe != PIPE_A) in vlv_dpll()
1451 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in vlv_compute_dpll()
1453 hw_state->dpll = vlv_dpll(crtc_state); in vlv_compute_dpll()
1454 hw_state->dpll_md = i965_dpll_md(crtc_state); in vlv_compute_dpll()
1459 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_dpll()
1465 if (crtc->pipe != PIPE_A) in chv_dpll()
1477 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in chv_compute_dpll()
1479 hw_state->dpll = chv_dpll(crtc_state); in chv_compute_dpll()
1480 hw_state->dpll_md = i965_dpll_md(crtc_state); in chv_compute_dpll()
1491 if (!crtc_state->clock_set && in chv_crtc_compute_clock()
1492 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in chv_crtc_compute_clock()
1493 refclk, NULL, &crtc_state->dpll)) in chv_crtc_compute_clock()
1494 return -EINVAL; in chv_crtc_compute_clock()
1496 chv_calc_dpll_params(refclk, &crtc_state->dpll); in chv_crtc_compute_clock()
1504 crtc_state->port_clock = crtc_state->dpll.dot; in chv_crtc_compute_clock()
1505 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in chv_crtc_compute_clock()
1518 if (!crtc_state->clock_set && in vlv_crtc_compute_clock()
1519 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in vlv_crtc_compute_clock()
1520 refclk, NULL, &crtc_state->dpll)) in vlv_crtc_compute_clock()
1521 return -EINVAL; in vlv_crtc_compute_clock()
1523 vlv_calc_dpll_params(refclk, &crtc_state->dpll); in vlv_crtc_compute_clock()
1531 crtc_state->port_clock = crtc_state->dpll.dot; in vlv_crtc_compute_clock()
1532 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in vlv_crtc_compute_clock()
1541 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in g4x_crtc_compute_clock()
1549 refclk = dev_priv->display.vbt.lvds_ssc_freq; in g4x_crtc_compute_clock()
1550 drm_dbg_kms(&dev_priv->drm, in g4x_crtc_compute_clock()
1569 if (!crtc_state->clock_set && in g4x_crtc_compute_clock()
1570 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in g4x_crtc_compute_clock()
1571 refclk, NULL, &crtc_state->dpll)) in g4x_crtc_compute_clock()
1572 return -EINVAL; in g4x_crtc_compute_clock()
1574 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); in g4x_crtc_compute_clock()
1576 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in g4x_crtc_compute_clock()
1577 &crtc_state->dpll); in g4x_crtc_compute_clock()
1579 crtc_state->port_clock = crtc_state->dpll.dot; in g4x_crtc_compute_clock()
1582 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in g4x_crtc_compute_clock()
1591 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in pnv_crtc_compute_clock()
1599 refclk = dev_priv->display.vbt.lvds_ssc_freq; in pnv_crtc_compute_clock()
1600 drm_dbg_kms(&dev_priv->drm, in pnv_crtc_compute_clock()
1610 if (!crtc_state->clock_set && in pnv_crtc_compute_clock()
1611 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in pnv_crtc_compute_clock()
1612 refclk, NULL, &crtc_state->dpll)) in pnv_crtc_compute_clock()
1613 return -EINVAL; in pnv_crtc_compute_clock()
1615 pnv_calc_dpll_params(refclk, &crtc_state->dpll); in pnv_crtc_compute_clock()
1617 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in pnv_crtc_compute_clock()
1618 &crtc_state->dpll); in pnv_crtc_compute_clock()
1620 crtc_state->port_clock = crtc_state->dpll.dot; in pnv_crtc_compute_clock()
1621 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in pnv_crtc_compute_clock()
1630 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in i9xx_crtc_compute_clock()
1638 refclk = dev_priv->display.vbt.lvds_ssc_freq; in i9xx_crtc_compute_clock()
1639 drm_dbg_kms(&dev_priv->drm, in i9xx_crtc_compute_clock()
1649 if (!crtc_state->clock_set && in i9xx_crtc_compute_clock()
1650 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in i9xx_crtc_compute_clock()
1651 refclk, NULL, &crtc_state->dpll)) in i9xx_crtc_compute_clock()
1652 return -EINVAL; in i9xx_crtc_compute_clock()
1654 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); in i9xx_crtc_compute_clock()
1656 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in i9xx_crtc_compute_clock()
1657 &crtc_state->dpll); in i9xx_crtc_compute_clock()
1659 crtc_state->port_clock = crtc_state->dpll.dot; in i9xx_crtc_compute_clock()
1662 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in i9xx_crtc_compute_clock()
1671 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in i8xx_crtc_compute_clock()
1679 refclk = dev_priv->display.vbt.lvds_ssc_freq; in i8xx_crtc_compute_clock()
1680 drm_dbg_kms(&dev_priv->drm, in i8xx_crtc_compute_clock()
1692 if (!crtc_state->clock_set && in i8xx_crtc_compute_clock()
1693 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in i8xx_crtc_compute_clock()
1694 refclk, NULL, &crtc_state->dpll)) in i8xx_crtc_compute_clock()
1695 return -EINVAL; in i8xx_crtc_compute_clock()
1697 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); in i8xx_crtc_compute_clock()
1699 i8xx_compute_dpll(crtc_state, &crtc_state->dpll, in i8xx_crtc_compute_clock()
1700 &crtc_state->dpll); in i8xx_crtc_compute_clock()
1702 crtc_state->port_clock = crtc_state->dpll.dot; in i8xx_crtc_compute_clock()
1703 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in i8xx_crtc_compute_clock()
1753 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_dpll_crtc_compute_clock()
1758 drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state)); in intel_dpll_crtc_compute_clock()
1760 memset(&crtc_state->dpll_hw_state, 0, in intel_dpll_crtc_compute_clock()
1761 sizeof(crtc_state->dpll_hw_state)); in intel_dpll_crtc_compute_clock()
1763 if (!crtc_state->hw.enable) in intel_dpll_crtc_compute_clock()
1766 ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc); in intel_dpll_crtc_compute_clock()
1768 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n", in intel_dpll_crtc_compute_clock()
1769 crtc->base.base.id, crtc->base.name); in intel_dpll_crtc_compute_clock()
1779 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_dpll_crtc_get_shared_dpll()
1784 drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state)); in intel_dpll_crtc_get_shared_dpll()
1785 drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && crtc_state->shared_dpll); in intel_dpll_crtc_get_shared_dpll()
1787 if (!crtc_state->hw.enable || crtc_state->shared_dpll) in intel_dpll_crtc_get_shared_dpll()
1790 if (!i915->display.funcs.dpll->crtc_get_shared_dpll) in intel_dpll_crtc_get_shared_dpll()
1793 ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc); in intel_dpll_crtc_get_shared_dpll()
1795 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n", in intel_dpll_crtc_get_shared_dpll()
1796 crtc->base.base.id, crtc->base.name); in intel_dpll_crtc_get_shared_dpll()
1807 dev_priv->display.funcs.dpll = &mtl_dpll_funcs; in intel_dpll_init_clock_hook()
1809 dev_priv->display.funcs.dpll = &dg2_dpll_funcs; in intel_dpll_init_clock_hook()
1811 dev_priv->display.funcs.dpll = &hsw_dpll_funcs; in intel_dpll_init_clock_hook()
1813 dev_priv->display.funcs.dpll = &ilk_dpll_funcs; in intel_dpll_init_clock_hook()
1815 dev_priv->display.funcs.dpll = &chv_dpll_funcs; in intel_dpll_init_clock_hook()
1817 dev_priv->display.funcs.dpll = &vlv_dpll_funcs; in intel_dpll_init_clock_hook()
1819 dev_priv->display.funcs.dpll = &g4x_dpll_funcs; in intel_dpll_init_clock_hook()
1821 dev_priv->display.funcs.dpll = &pnv_dpll_funcs; in intel_dpll_init_clock_hook()
1823 dev_priv->display.funcs.dpll = &i9xx_dpll_funcs; in intel_dpll_init_clock_hook()
1825 dev_priv->display.funcs.dpll = &i8xx_dpll_funcs; in intel_dpll_init_clock_hook()
1839 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_enable_pll()
1840 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_enable_pll()
1841 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i9xx_enable_pll()
1842 enum pipe pipe = crtc->pipe; in i9xx_enable_pll()
1845 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); in i9xx_enable_pll()
1851 intel_de_write(dev_priv, FP0(pipe), hw_state->fp0); in i9xx_enable_pll()
1852 intel_de_write(dev_priv, FP1(pipe), hw_state->fp1); in i9xx_enable_pll()
1860 hw_state->dpll & ~DPLL_VGA_MODE_DIS); in i9xx_enable_pll()
1861 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); in i9xx_enable_pll()
1869 hw_state->dpll_md); in i9xx_enable_pll()
1876 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); in i9xx_enable_pll()
1881 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); in i9xx_enable_pll()
1893 * PLLB opamp always calibrates to max value of 0x3f, force enable it in vlv_pllb_recal_opamp()
1918 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_prepare_pll()
1919 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_prepare_pll()
1920 const struct dpll *clock = &crtc_state->dpll; in vlv_prepare_pll()
1921 enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); in vlv_prepare_pll()
1922 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); in vlv_prepare_pll()
1923 enum pipe pipe = crtc->pipe; in vlv_prepare_pll()
1937 /* Disable target IRef on PLL */ in vlv_prepare_pll()
1946 tmp = DPIO_M1_DIV(clock->m1) | in vlv_prepare_pll()
1947 DPIO_M2_DIV(clock->m2) | in vlv_prepare_pll()
1948 DPIO_P1_DIV(clock->p1) | in vlv_prepare_pll()
1949 DPIO_P2_DIV(clock->p2) | in vlv_prepare_pll()
1950 DPIO_N_DIV(clock->n) | in vlv_prepare_pll()
1965 if (crtc_state->port_clock == 162000 || in vlv_prepare_pll()
2005 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in _vlv_enable_pll()
2006 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in _vlv_enable_pll()
2007 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in _vlv_enable_pll()
2008 enum pipe pipe = crtc->pipe; in _vlv_enable_pll()
2010 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); in _vlv_enable_pll()
2015 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); in _vlv_enable_pll()
2021 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_enable_pll()
2022 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_enable_pll()
2023 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in vlv_enable_pll()
2024 enum pipe pipe = crtc->pipe; in vlv_enable_pll()
2026 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); in vlv_enable_pll()
2031 /* Enable Refclk */ in vlv_enable_pll()
2033 hw_state->dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); in vlv_enable_pll()
2035 if (hw_state->dpll & DPLL_VCO_ENABLE) { in vlv_enable_pll()
2040 intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe), hw_state->dpll_md); in vlv_enable_pll()
2046 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_prepare_pll()
2047 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in chv_prepare_pll()
2048 const struct dpll *clock = &crtc_state->dpll; in chv_prepare_pll()
2049 enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); in chv_prepare_pll()
2050 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); in chv_prepare_pll()
2054 m2_frac = clock->m2 & 0x3fffff; in chv_prepare_pll()
2061 DPIO_CHV_P1_DIV(clock->p1) | in chv_prepare_pll()
2062 DPIO_CHV_P2_DIV(clock->p2) | in chv_prepare_pll()
2065 /* Feedback post-divider - m2 */ in chv_prepare_pll()
2067 DPIO_CHV_M2_DIV(clock->m2 >> 22)); in chv_prepare_pll()
2069 /* Feedback refclk divider - n and m1 */ in chv_prepare_pll()
2078 /* M2 fraction division enable */ in chv_prepare_pll()
2096 if (clock->vco == 5400000) { in chv_prepare_pll()
2101 } else if (clock->vco <= 6200000) { in chv_prepare_pll()
2106 } else if (clock->vco <= 6480000) { in chv_prepare_pll()
2135 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in _chv_enable_pll()
2136 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in _chv_enable_pll()
2137 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in _chv_enable_pll()
2138 enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); in _chv_enable_pll()
2139 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); in _chv_enable_pll()
2140 enum pipe pipe = crtc->pipe; in _chv_enable_pll()
2145 /* Enable back the 10bit clock to display controller */ in _chv_enable_pll()
2153 * Need to wait > 100ns between dclkp clock enable bit and PLL enable. in _chv_enable_pll()
2157 /* Enable PLL */ in _chv_enable_pll()
2158 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); in _chv_enable_pll()
2162 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe); in _chv_enable_pll()
2168 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_enable_pll()
2169 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in chv_enable_pll()
2170 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in chv_enable_pll()
2171 enum pipe pipe = crtc->pipe; in chv_enable_pll()
2173 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); in chv_enable_pll()
2178 /* Enable Refclk and SSC */ in chv_enable_pll()
2180 hw_state->dpll & ~DPLL_VCO_ENABLE); in chv_enable_pll()
2182 if (hw_state->dpll & DPLL_VCO_ENABLE) { in chv_enable_pll()
2196 hw_state->dpll_md); in chv_enable_pll()
2198 dev_priv->display.state.chv_dpll_md[pipe] = hw_state->dpll_md; in chv_enable_pll()
2204 drm_WARN_ON(&dev_priv->drm, in chv_enable_pll()
2209 hw_state->dpll_md); in chv_enable_pll()
2215 * vlv_force_pll_on - forcibly enable just the PLL
2217 * @pipe: pipe PLL to enable
2220 * Enable the PLL for @pipe using the supplied @dpll config. To be used
2227 struct intel_display *display = &dev_priv->display; in vlv_force_pll_on()
2233 return -ENOMEM; in vlv_force_pll_on()
2235 crtc_state->cpu_transcoder = (enum transcoder)pipe; in vlv_force_pll_on()
2236 crtc_state->pixel_multiplier = 1; in vlv_force_pll_on()
2237 crtc_state->dpll = *dpll; in vlv_force_pll_on()
2238 crtc_state->output_types = BIT(INTEL_OUTPUT_EDP); in vlv_force_pll_on()
2248 intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi); in vlv_force_pll_on()
2298 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_disable_pll()
2299 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_disable_pll()
2300 enum pipe pipe = crtc->pipe; in i9xx_disable_pll()
2307 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); in i9xx_disable_pll()
2315 * vlv_force_pll_off - forcibly disable just the PLL
2330 /* Only for pre-ILK configs */
2334 struct intel_display *display = &dev_priv->display; in assert_pll()