Lines Matching +full:force +full:- +full:m1
1 // SPDX-License-Identifier: MIT
37 } dot, vco, n, m, m1, m2, p, p1;
49 .m1 = { .min = 18, .max = 26 },
62 .m1 = { .min = 18, .max = 26 },
75 .m1 = { .min = 18, .max = 26 },
88 .m1 = { .min = 8, .max = 18 },
101 .m1 = { .min = 8, .max = 18 },
115 .m1 = { .min = 17, .max = 23 },
130 .m1 = { .min = 16, .max = 23 },
143 .m1 = { .min = 17, .max = 23 },
157 .m1 = { .min = 17, .max = 23 },
173 .m1 = { .min = 0, .max = 0 },
186 .m1 = { .min = 0, .max = 0 },
196 * We calculate clock using (register_value + 2) for N/M1/M2, so here
197 * the range value for them is (actual_value - 2).
204 .m1 = { .min = 12, .max = 22 },
217 .m1 = { .min = 12, .max = 22 },
230 .m1 = { .min = 12, .max = 22 },
244 .m1 = { .min = 12, .max = 22 },
257 .m1 = { .min = 12, .max = 22 },
275 .m1 = { .min = 2, .max = 3 },
291 .m1 = { .min = 2, .max = 2 },
301 .m1 = { .min = 2, .max = 2 },
309 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
310 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
314 * divided-down version of it.
316 /* m1 is reserved as 0 in Pineview, n is a ring counter */
319 clock->m = clock->m2 + 2;
320 clock->p = clock->p1 * clock->p2;
322 clock->vco = clock->n == 0 ? 0 :
323 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
324 clock->dot = clock->p == 0 ? 0 :
325 DIV_ROUND_CLOSEST(clock->vco, clock->p);
327 return clock->dot;
332 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
337 clock->m = i9xx_dpll_compute_m(clock);
338 clock->p = clock->p1 * clock->p2;
340 clock->vco = clock->n + 2 == 0 ? 0 :
341 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
342 clock->dot = clock->p == 0 ? 0 :
343 DIV_ROUND_CLOSEST(clock->vco, clock->p);
345 return clock->dot;
350 clock->m = clock->m1 * clock->m2;
351 clock->p = clock->p1 * clock->p2 * 5;
353 clock->vco = clock->n == 0 ? 0 :
354 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
355 clock->dot = clock->p == 0 ? 0 :
356 DIV_ROUND_CLOSEST(clock->vco, clock->p);
358 return clock->dot;
363 clock->m = clock->m1 * clock->m2;
364 clock->p = clock->p1 * clock->p2 * 5;
366 clock->vco = clock->n == 0 ? 0 :
367 DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), clock->n << 22);
368 clock->dot = clock->p == 0 ? 0 :
369 DIV_ROUND_CLOSEST(clock->vco, clock->p);
371 return clock->dot;
376 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
377 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
379 if ((hw_state->dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
380 return i915->display.vbt.lvds_ssc_freq;
392 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
393 struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
399 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
400 tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe];
403 DPLL_MD(dev_priv, crtc->pipe));
405 hw_state->dpll_md = tmp;
408 hw_state->dpll = intel_de_read(dev_priv, DPLL(dev_priv, crtc->pipe));
411 hw_state->fp0 = intel_de_read(dev_priv, FP0(crtc->pipe));
412 hw_state->fp1 = intel_de_read(dev_priv, FP1(crtc->pipe));
414 /* Mask out read-only status bits. */
415 hw_state->dpll &= ~(DPLL_LOCK_VLV |
424 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
425 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
426 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
427 u32 dpll = hw_state->dpll;
434 fp = hw_state->fp0;
436 fp = hw_state->fp1;
438 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
440 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
465 drm_dbg_kms(&dev_priv->drm,
480 lvds_pipe == crtc->pipe) {
511 crtc_state->port_clock = port_clock;
516 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
517 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
518 enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);
519 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
520 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
526 if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0)
533 clock.m1 = REG_FIELD_GET(DPIO_M1_DIV_MASK, tmp);
539 crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock);
544 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
545 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
546 enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);
547 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
548 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
554 if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0)
565 clock.m1 = REG_FIELD_GET(DPIO_CHV_M1_DIV_MASK, pll_dw1) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
573 crtc_state->port_clock = chv_calc_dpll_params(refclk, &clock);
584 if (clock->n < limit->n.min || limit->n.max < clock->n)
586 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
588 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
590 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
596 if (clock->m1 <= clock->m2)
601 if (clock->p < limit->p.min || limit->p.max < clock->p)
603 if (clock->m < limit->m.min || limit->m.max < clock->m)
607 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
612 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
623 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
627 * For LVDS just rely on its current settings for dual-channel.
632 return limit->p2.p2_fast;
634 return limit->p2.p2_slow;
636 if (target < limit->p2.dot_limit)
637 return limit->p2.p2_slow;
639 return limit->p2.p2_fast;
659 struct drm_device *dev = crtc_state->uapi.crtc->dev;
667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
671 if (clock.m2 >= clock.m1)
673 for (clock.n = limit->n.min;
674 clock.n <= limit->n.max; clock.n++) {
675 for (clock.p1 = limit->p1.min;
676 clock.p1 <= limit->p1.max; clock.p1++) {
685 clock.p != match_clock->p)
688 this_err = abs(clock.dot - target);
717 struct drm_device *dev = crtc_state->uapi.crtc->dev;
725 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
726 clock.m1++) {
727 for (clock.m2 = limit->m2.min;
728 clock.m2 <= limit->m2.max; clock.m2++) {
729 for (clock.n = limit->n.min;
730 clock.n <= limit->n.max; clock.n++) {
731 for (clock.p1 = limit->p1.min;
732 clock.p1 <= limit->p1.max; clock.p1++) {
741 clock.p != match_clock->p)
744 this_err = abs(clock.dot - target);
773 struct drm_device *dev = crtc_state->uapi.crtc->dev;
784 max_n = limit->n.max;
786 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
787 /* based on hardware requirement, prefer larger m1,m2 */
788 for (clock.m1 = limit->m1.max;
789 clock.m1 >= limit->m1.min; clock.m1--) {
790 for (clock.m2 = limit->m2.max;
791 clock.m2 >= limit->m2.min; clock.m2--) {
792 for (clock.p1 = limit->p1.max;
793 clock.p1 >= limit->p1.min; clock.p1--) {
802 this_err = abs(clock.dot - target);
833 return calculated_clock->p > best_clock->p;
840 abs(target_freq - calculated_clock->dot),
847 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
867 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
868 struct drm_device *dev = crtc->base.dev;
872 int max_n = min(limit->n.max, refclk / 19200);
878 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
879 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
880 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
881 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
883 /* based on hardware requirement, prefer bigger m1,m2 values */
884 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
888 refclk * clock.m1);
925 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
926 struct drm_device *dev = crtc->base.dev;
936 * Based on hardware doc, the n always set to 1, and m1 always
941 clock.m1 = 2;
943 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
944 for (clock.p2 = limit->p2.p2_fast;
945 clock.p2 >= limit->p2.p2_slow;
946 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
952 refclk * clock.m1);
954 if (m2 > INT_MAX/clock.m1)
984 crtc_state->port_clock, refclk,
990 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
995 return (1 << dpll->n) << 16 | dpll->m2;
1000 return (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1008 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1009 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1021 dpll |= (crtc_state->pixel_multiplier - 1)
1034 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1035 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
1037 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
1038 WARN_ON(reduced_clock->p1 != clock->p1);
1040 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1041 WARN_ON(reduced_clock->p1 != clock->p1);
1044 switch (clock->p2) {
1058 WARN_ON(reduced_clock->p2 != clock->p2);
1063 if (crtc_state->sdvo_tv_clock)
1078 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1079 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1080 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
1083 hw_state->fp0 = pnv_dpll_compute_fp(clock);
1084 hw_state->fp1 = pnv_dpll_compute_fp(reduced_clock);
1086 hw_state->fp0 = i9xx_dpll_compute_fp(clock);
1087 hw_state->fp1 = i9xx_dpll_compute_fp(reduced_clock);
1090 hw_state->dpll = i9xx_dpll(crtc_state, clock, reduced_clock);
1093 hw_state->dpll_md = i965_dpll_md(crtc_state);
1101 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1102 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1108 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1110 if (clock->p1 == 2)
1113 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1114 if (clock->p2 == 4)
1117 WARN_ON(reduced_clock->p1 != clock->p1);
1118 WARN_ON(reduced_clock->p2 != clock->p2);
1126 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
1149 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
1151 hw_state->fp0 = i9xx_dpll_compute_fp(clock);
1152 hw_state->fp1 = i9xx_dpll_compute_fp(reduced_clock);
1154 hw_state->dpll = i8xx_dpll(crtc_state, clock, reduced_clock);
1160 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1180 if (!crtc_state->has_pch_encoder)
1181 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1189 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1215 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1234 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
1236 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1244 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1245 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1248 ((intel_panel_use_ssc(display) && i915->display.vbt.lvds_ssc_freq == 100000) ||
1252 if (crtc_state->sdvo_tv_clock)
1260 return dpll->m < factor * dpll->n;
1279 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1280 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1290 dpll |= (crtc_state->pixel_multiplier - 1)
1312 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
1319 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1321 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
1323 switch (clock->p2) {
1337 WARN_ON(reduced_clock->p2 != clock->p2);
1352 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
1355 hw_state->fp0 = ilk_dpll_compute_fp(clock, factor);
1356 hw_state->fp1 = ilk_dpll_compute_fp(reduced_clock, factor);
1358 hw_state->dpll = ilk_dpll(crtc_state, clock, reduced_clock);
1365 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1373 if (!crtc_state->has_pch_encoder)
1378 drm_dbg_kms(&dev_priv->drm,
1380 dev_priv->display.vbt.lvds_ssc_freq);
1381 refclk = dev_priv->display.vbt.lvds_ssc_freq;
1399 if (!crtc_state->clock_set &&
1400 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1401 refclk, NULL, &crtc_state->dpll))
1402 return -EINVAL;
1404 i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1406 ilk_compute_dpll(crtc_state, &crtc_state->dpll,
1407 &crtc_state->dpll);
1413 crtc_state->port_clock = crtc_state->dpll.dot;
1414 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1426 if (!crtc_state->has_pch_encoder)
1434 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1440 if (crtc->pipe != PIPE_A)
1452 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
1454 hw_state->dpll = vlv_dpll(crtc_state);
1455 hw_state->dpll_md = i965_dpll_md(crtc_state);
1460 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1466 if (crtc->pipe != PIPE_A)
1478 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
1480 hw_state->dpll = chv_dpll(crtc_state);
1481 hw_state->dpll_md = i965_dpll_md(crtc_state);
1492 if (!crtc_state->clock_set &&
1493 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1494 refclk, NULL, &crtc_state->dpll))
1495 return -EINVAL;
1497 chv_calc_dpll_params(refclk, &crtc_state->dpll);
1505 crtc_state->port_clock = crtc_state->dpll.dot;
1506 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1519 if (!crtc_state->clock_set &&
1520 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1521 refclk, NULL, &crtc_state->dpll))
1522 return -EINVAL;
1524 vlv_calc_dpll_params(refclk, &crtc_state->dpll);
1532 crtc_state->port_clock = crtc_state->dpll.dot;
1533 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1542 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1550 refclk = dev_priv->display.vbt.lvds_ssc_freq;
1551 drm_dbg_kms(&dev_priv->drm,
1570 if (!crtc_state->clock_set &&
1571 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1572 refclk, NULL, &crtc_state->dpll))
1573 return -EINVAL;
1575 i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1577 i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
1578 &crtc_state->dpll);
1580 crtc_state->port_clock = crtc_state->dpll.dot;
1583 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1592 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1600 refclk = dev_priv->display.vbt.lvds_ssc_freq;
1601 drm_dbg_kms(&dev_priv->drm,
1611 if (!crtc_state->clock_set &&
1612 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1613 refclk, NULL, &crtc_state->dpll))
1614 return -EINVAL;
1616 pnv_calc_dpll_params(refclk, &crtc_state->dpll);
1618 i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
1619 &crtc_state->dpll);
1621 crtc_state->port_clock = crtc_state->dpll.dot;
1622 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1631 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1639 refclk = dev_priv->display.vbt.lvds_ssc_freq;
1640 drm_dbg_kms(&dev_priv->drm,
1650 if (!crtc_state->clock_set &&
1651 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1652 refclk, NULL, &crtc_state->dpll))
1653 return -EINVAL;
1655 i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1657 i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
1658 &crtc_state->dpll);
1660 crtc_state->port_clock = crtc_state->dpll.dot;
1663 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1672 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1680 refclk = dev_priv->display.vbt.lvds_ssc_freq;
1681 drm_dbg_kms(&dev_priv->drm,
1693 if (!crtc_state->clock_set &&
1694 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1695 refclk, NULL, &crtc_state->dpll))
1696 return -EINVAL;
1698 i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1700 i8xx_compute_dpll(crtc_state, &crtc_state->dpll,
1701 &crtc_state->dpll);
1703 crtc_state->port_clock = crtc_state->dpll.dot;
1704 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1754 struct drm_i915_private *i915 = to_i915(state->base.dev);
1759 drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
1761 memset(&crtc_state->dpll_hw_state, 0,
1762 sizeof(crtc_state->dpll_hw_state));
1764 if (!crtc_state->hw.enable)
1767 ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc);
1769 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n",
1770 crtc->base.base.id, crtc->base.name);
1780 struct drm_i915_private *i915 = to_i915(state->base.dev);
1785 drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
1786 drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && crtc_state->shared_dpll);
1788 if (!crtc_state->hw.enable || crtc_state->shared_dpll)
1791 if (!i915->display.funcs.dpll->crtc_get_shared_dpll)
1794 ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc);
1796 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n",
1797 crtc->base.base.id, crtc->base.name);
1808 dev_priv->display.funcs.dpll = &mtl_dpll_funcs;
1810 dev_priv->display.funcs.dpll = &dg2_dpll_funcs;
1812 dev_priv->display.funcs.dpll = &hsw_dpll_funcs;
1814 dev_priv->display.funcs.dpll = &ilk_dpll_funcs;
1816 dev_priv->display.funcs.dpll = &chv_dpll_funcs;
1818 dev_priv->display.funcs.dpll = &vlv_dpll_funcs;
1820 dev_priv->display.funcs.dpll = &g4x_dpll_funcs;
1822 dev_priv->display.funcs.dpll = &pnv_dpll_funcs;
1824 dev_priv->display.funcs.dpll = &i9xx_dpll_funcs;
1826 dev_priv->display.funcs.dpll = &i8xx_dpll_funcs;
1840 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1841 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1842 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
1843 enum pipe pipe = crtc->pipe;
1846 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
1852 intel_de_write(dev_priv, FP0(pipe), hw_state->fp0);
1853 intel_de_write(dev_priv, FP1(pipe), hw_state->fp1);
1861 hw_state->dpll & ~DPLL_VGA_MODE_DIS);
1862 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll);
1870 hw_state->dpll_md);
1877 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll);
1882 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll);
1894 * PLLB opamp always calibrates to max value of 0x3f, force enable it
1919 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1920 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1921 const struct dpll *clock = &crtc_state->dpll;
1922 enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);
1923 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
1924 enum pipe pipe = crtc->pipe;
1947 tmp = DPIO_M1_DIV(clock->m1) |
1948 DPIO_M2_DIV(clock->m2) |
1949 DPIO_P1_DIV(clock->p1) |
1950 DPIO_P2_DIV(clock->p2) |
1951 DPIO_N_DIV(clock->n) |
1966 if (crtc_state->port_clock == 162000 ||
2006 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2007 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2008 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
2009 enum pipe pipe = crtc->pipe;
2011 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll);
2016 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);
2022 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2023 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2024 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
2025 enum pipe pipe = crtc->pipe;
2027 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
2034 hw_state->dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
2036 if (hw_state->dpll & DPLL_VCO_ENABLE) {
2041 intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe), hw_state->dpll_md);
2047 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2048 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2049 const struct dpll *clock = &crtc_state->dpll;
2050 enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);
2051 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
2055 m2_frac = clock->m2 & 0x3fffff;
2062 DPIO_CHV_P1_DIV(clock->p1) |
2063 DPIO_CHV_P2_DIV(clock->p2) |
2066 /* Feedback post-divider - m2 */
2068 DPIO_CHV_M2_DIV(clock->m2 >> 22));
2070 /* Feedback refclk divider - n and m1 */
2097 if (clock->vco == 5400000) {
2102 } else if (clock->vco <= 6200000) {
2107 } else if (clock->vco <= 6480000) {
2136 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2137 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2138 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
2139 enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);
2140 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
2141 enum pipe pipe = crtc->pipe;
2159 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll);
2163 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);
2169 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2170 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2171 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
2172 enum pipe pipe = crtc->pipe;
2174 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
2181 hw_state->dpll & ~DPLL_VCO_ENABLE);
2183 if (hw_state->dpll & DPLL_VCO_ENABLE) {
2197 hw_state->dpll_md);
2199 dev_priv->display.state.chv_dpll_md[pipe] = hw_state->dpll_md;
2205 drm_WARN_ON(&dev_priv->drm,
2210 hw_state->dpll_md);
2216 * vlv_force_pll_on - forcibly enable just the PLL
2228 struct intel_display *display = &dev_priv->display;
2234 return -ENOMEM;
2236 crtc_state->cpu_transcoder = (enum transcoder)pipe;
2237 crtc_state->pixel_multiplier = 1;
2238 crtc_state->dpll = *dpll;
2239 crtc_state->output_types = BIT(INTEL_OUTPUT_EDP);
2249 intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
2299 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2300 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2301 enum pipe pipe = crtc->pipe;
2308 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
2316 * vlv_force_pll_off - forcibly disable just the PLL
2331 /* Only for pre-ILK configs */
2335 struct intel_display *display = &dev_priv->display;