Lines Matching full:dpll
317 static int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params()
330 static u32 i9xx_dpll_compute_m(const struct dpll *dpll) in i9xx_dpll_compute_m() argument
332 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
335 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params()
348 static int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params()
361 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params()
379 if ((hw_state->dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) in i9xx_pll_refclk()
408 hw_state->dpll = intel_de_read(dev_priv, DPLL(dev_priv, crtc->pipe)); in i9xx_dpll_get_hw_state()
415 hw_state->dpll &= ~(DPLL_LOCK_VLV | in i9xx_dpll_get_hw_state()
427 u32 dpll = hw_state->dpll; in i9xx_crtc_clock_get() local
429 struct dpll clock; in i9xx_crtc_clock_get()
433 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) in i9xx_crtc_clock_get()
449 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> in i9xx_crtc_clock_get()
452 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> in i9xx_crtc_clock_get()
455 switch (dpll & DPLL_MODE_MASK) { in i9xx_crtc_clock_get()
457 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? in i9xx_crtc_clock_get()
461 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? in i9xx_crtc_clock_get()
466 "Unknown DPLL mode %08x in programmed " in i9xx_crtc_clock_get()
467 "mode\n", (int)(dpll & DPLL_MODE_MASK)); in i9xx_crtc_clock_get()
483 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> in i9xx_crtc_clock_get()
491 if (dpll & PLL_P1_DIVIDE_BY_TWO) in i9xx_crtc_clock_get()
494 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> in i9xx_crtc_clock_get()
497 if (dpll & PLL_P2_DIVIDE_BY_4) in i9xx_crtc_clock_get()
522 struct dpll clock; in vlv_crtc_clock_get()
525 /* In case of DSI, DPLL will not be used */ in vlv_crtc_clock_get()
526 if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0) in vlv_crtc_clock_get()
549 struct dpll clock; in chv_crtc_clock_get()
553 /* In case of DSI, DPLL will not be used */ in chv_crtc_clock_get()
554 if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0) in chv_crtc_clock_get()
582 const struct dpll *clock) in intel_pll_is_valid()
656 const struct dpll *match_clock, in i9xx_find_best_dpll()
657 struct dpll *best_clock) in i9xx_find_best_dpll()
660 struct dpll clock; in i9xx_find_best_dpll()
714 const struct dpll *match_clock, in pnv_find_best_dpll()
715 struct dpll *best_clock) in pnv_find_best_dpll()
718 struct dpll clock; in pnv_find_best_dpll()
770 const struct dpll *match_clock, in g4x_find_best_dpll()
771 struct dpll *best_clock) in g4x_find_best_dpll()
774 struct dpll clock; in g4x_find_best_dpll()
821 const struct dpll *calculated_clock, in vlv_PLL_is_optimal()
822 const struct dpll *best_clock, in vlv_PLL_is_optimal()
864 const struct dpll *match_clock, in vlv_find_best_dpll()
865 struct dpll *best_clock) in vlv_find_best_dpll()
869 struct dpll clock; in vlv_find_best_dpll()
922 const struct dpll *match_clock, in chv_find_best_dpll()
923 struct dpll *best_clock) in chv_find_best_dpll()
928 struct dpll clock; in chv_find_best_dpll()
978 struct dpll *best_clock) in bxt_find_best_dpll()
988 u32 i9xx_dpll_compute_fp(const struct dpll *dpll) in i9xx_dpll_compute_fp() argument
990 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp()
993 static u32 pnv_dpll_compute_fp(const struct dpll *dpll) in pnv_dpll_compute_fp() argument
995 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
1004 const struct dpll *clock, in i9xx_dpll()
1005 const struct dpll *reduced_clock) in i9xx_dpll()
1010 u32 dpll; in i9xx_dpll() local
1012 dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS; in i9xx_dpll()
1015 dpll |= DPLLB_MODE_LVDS; in i9xx_dpll()
1017 dpll |= DPLLB_MODE_DAC_SERIAL; in i9xx_dpll()
1021 dpll |= (crtc_state->pixel_multiplier - 1) in i9xx_dpll()
1027 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_dpll()
1030 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_dpll()
1034 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_dpll()
1035 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in i9xx_dpll()
1037 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; in i9xx_dpll()
1040 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_dpll()
1046 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in i9xx_dpll()
1049 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in i9xx_dpll()
1052 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in i9xx_dpll()
1055 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in i9xx_dpll()
1061 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); in i9xx_dpll()
1064 dpll |= PLL_REF_INPUT_TVCLKINBC; in i9xx_dpll()
1067 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i9xx_dpll()
1069 dpll |= PLL_REF_INPUT_DREFCLK; in i9xx_dpll()
1071 return dpll; in i9xx_dpll()
1075 const struct dpll *clock, in i9xx_compute_dpll()
1076 const struct dpll *reduced_clock) in i9xx_compute_dpll()
1090 hw_state->dpll = i9xx_dpll(crtc_state, clock, reduced_clock); in i9xx_compute_dpll()
1097 const struct dpll *clock, in i8xx_dpll()
1098 const struct dpll *reduced_clock) in i8xx_dpll()
1103 u32 dpll; in i8xx_dpll() local
1105 dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS; in i8xx_dpll()
1108 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_dpll()
1111 dpll |= PLL_P1_DIVIDE_BY_TWO; in i8xx_dpll()
1113 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_dpll()
1115 dpll |= PLL_P2_DIVIDE_BY_4; in i8xx_dpll()
1124 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock in i8xx_dpll()
1125 * Enable) must be set to “1” in both the DPLL A Control Register in i8xx_dpll()
1126 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)." in i8xx_dpll()
1134 dpll |= DPLL_DVO_2X_MODE; in i8xx_dpll()
1138 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i8xx_dpll()
1140 dpll |= PLL_REF_INPUT_DREFCLK; in i8xx_dpll()
1142 return dpll; in i8xx_dpll()
1146 const struct dpll *clock, in i8xx_compute_dpll()
1147 const struct dpll *reduced_clock) in i8xx_compute_dpll()
1154 hw_state->dpll = i8xx_dpll(crtc_state, clock, reduced_clock); in i8xx_compute_dpll()
1258 static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor) in ilk_needs_fb_cb_tune() argument
1260 return dpll->m < factor * dpll->n; in ilk_needs_fb_cb_tune()
1263 static u32 ilk_dpll_compute_fp(const struct dpll *clock, int factor) in ilk_dpll_compute_fp()
1275 const struct dpll *clock, in ilk_dpll()
1276 const struct dpll *reduced_clock) in ilk_dpll()
1281 u32 dpll; in ilk_dpll() local
1283 dpll = DPLL_VCO_ENABLE; in ilk_dpll()
1286 dpll |= DPLLB_MODE_LVDS; in ilk_dpll()
1288 dpll |= DPLLB_MODE_DAC_SERIAL; in ilk_dpll()
1290 dpll |= (crtc_state->pixel_multiplier - 1) in ilk_dpll()
1295 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_dpll()
1298 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_dpll()
1303 * possible to share the DPLL between CRT and HDMI. Enabling in ilk_dpll()
1308 * DPLLs and so DPLL sharing is the only way to get three pipes in ilk_dpll()
1310 * and potentially avoid enabling the second DPLL, but it's not in ilk_dpll()
1312 * this on ILK at all since it has a fixed DPLL<->pipe mapping. in ilk_dpll()
1316 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_dpll()
1319 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ilk_dpll()
1321 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in ilk_dpll()
1325 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in ilk_dpll()
1328 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in ilk_dpll()
1331 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in ilk_dpll()
1334 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in ilk_dpll()
1341 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in ilk_dpll()
1343 dpll |= PLL_REF_INPUT_DREFCLK; in ilk_dpll()
1345 return dpll; in ilk_dpll()
1349 const struct dpll *clock, in ilk_compute_dpll()
1350 const struct dpll *reduced_clock) in ilk_compute_dpll()
1358 hw_state->dpll = ilk_dpll(crtc_state, clock, reduced_clock); in ilk_compute_dpll()
1401 refclk, NULL, &crtc_state->dpll)) in ilk_crtc_compute_clock()
1404 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); in ilk_crtc_compute_clock()
1406 ilk_compute_dpll(crtc_state, &crtc_state->dpll, in ilk_crtc_compute_clock()
1407 &crtc_state->dpll); in ilk_crtc_compute_clock()
1413 crtc_state->port_clock = crtc_state->dpll.dot; in ilk_crtc_compute_clock()
1435 u32 dpll; in vlv_dpll() local
1437 dpll = DPLL_INTEGRATED_REF_CLK_VLV | in vlv_dpll()
1441 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in vlv_dpll()
1443 /* DPLL not used with DSI, but still need the rest set up */ in vlv_dpll()
1445 dpll |= DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV; in vlv_dpll()
1447 return dpll; in vlv_dpll()
1454 hw_state->dpll = vlv_dpll(crtc_state); in vlv_compute_dpll()
1461 u32 dpll; in chv_dpll() local
1463 dpll = DPLL_SSC_REF_CLK_CHV | in chv_dpll()
1467 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in chv_dpll()
1469 /* DPLL not used with DSI, but still need the rest set up */ in chv_dpll()
1471 dpll |= DPLL_VCO_ENABLE; in chv_dpll()
1473 return dpll; in chv_dpll()
1480 hw_state->dpll = chv_dpll(crtc_state); in chv_compute_dpll()
1494 refclk, NULL, &crtc_state->dpll)) in chv_crtc_compute_clock()
1497 chv_calc_dpll_params(refclk, &crtc_state->dpll); in chv_crtc_compute_clock()
1505 crtc_state->port_clock = crtc_state->dpll.dot; in chv_crtc_compute_clock()
1521 refclk, NULL, &crtc_state->dpll)) in vlv_crtc_compute_clock()
1524 vlv_calc_dpll_params(refclk, &crtc_state->dpll); in vlv_crtc_compute_clock()
1532 crtc_state->port_clock = crtc_state->dpll.dot; in vlv_crtc_compute_clock()
1572 refclk, NULL, &crtc_state->dpll)) in g4x_crtc_compute_clock()
1575 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); in g4x_crtc_compute_clock()
1577 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in g4x_crtc_compute_clock()
1578 &crtc_state->dpll); in g4x_crtc_compute_clock()
1580 crtc_state->port_clock = crtc_state->dpll.dot; in g4x_crtc_compute_clock()
1613 refclk, NULL, &crtc_state->dpll)) in pnv_crtc_compute_clock()
1616 pnv_calc_dpll_params(refclk, &crtc_state->dpll); in pnv_crtc_compute_clock()
1618 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in pnv_crtc_compute_clock()
1619 &crtc_state->dpll); in pnv_crtc_compute_clock()
1621 crtc_state->port_clock = crtc_state->dpll.dot; in pnv_crtc_compute_clock()
1652 refclk, NULL, &crtc_state->dpll)) in i9xx_crtc_compute_clock()
1655 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); in i9xx_crtc_compute_clock()
1657 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in i9xx_crtc_compute_clock()
1658 &crtc_state->dpll); in i9xx_crtc_compute_clock()
1660 crtc_state->port_clock = crtc_state->dpll.dot; in i9xx_crtc_compute_clock()
1695 refclk, NULL, &crtc_state->dpll)) in i8xx_crtc_compute_clock()
1698 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); in i8xx_crtc_compute_clock()
1700 i8xx_compute_dpll(crtc_state, &crtc_state->dpll, in i8xx_crtc_compute_clock()
1701 &crtc_state->dpll); in i8xx_crtc_compute_clock()
1703 crtc_state->port_clock = crtc_state->dpll.dot; in i8xx_crtc_compute_clock()
1767 ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc); in intel_dpll_crtc_compute_clock()
1769 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n", in intel_dpll_crtc_compute_clock()
1791 if (!i915->display.funcs.dpll->crtc_get_shared_dpll) in intel_dpll_crtc_get_shared_dpll()
1794 ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc); in intel_dpll_crtc_get_shared_dpll()
1796 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n", in intel_dpll_crtc_get_shared_dpll()
1808 dev_priv->display.funcs.dpll = &mtl_dpll_funcs; in intel_dpll_init_clock_hook()
1810 dev_priv->display.funcs.dpll = &dg2_dpll_funcs; in intel_dpll_init_clock_hook()
1812 dev_priv->display.funcs.dpll = &hsw_dpll_funcs; in intel_dpll_init_clock_hook()
1814 dev_priv->display.funcs.dpll = &ilk_dpll_funcs; in intel_dpll_init_clock_hook()
1816 dev_priv->display.funcs.dpll = &chv_dpll_funcs; in intel_dpll_init_clock_hook()
1818 dev_priv->display.funcs.dpll = &vlv_dpll_funcs; in intel_dpll_init_clock_hook()
1820 dev_priv->display.funcs.dpll = &g4x_dpll_funcs; in intel_dpll_init_clock_hook()
1822 dev_priv->display.funcs.dpll = &pnv_dpll_funcs; in intel_dpll_init_clock_hook()
1824 dev_priv->display.funcs.dpll = &i9xx_dpll_funcs; in intel_dpll_init_clock_hook()
1826 dev_priv->display.funcs.dpll = &i8xx_dpll_funcs; in intel_dpll_init_clock_hook()
1857 * the P1/P2 dividers. Otherwise the DPLL will keep using the old in i9xx_enable_pll()
1860 intel_de_write(dev_priv, DPLL(dev_priv, pipe), in i9xx_enable_pll()
1861 hw_state->dpll & ~DPLL_VGA_MODE_DIS); in i9xx_enable_pll()
1862 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); in i9xx_enable_pll()
1865 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in i9xx_enable_pll()
1873 * DPLL is enabled and the clocks are stable. in i9xx_enable_pll()
1877 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); in i9xx_enable_pll()
1882 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); in i9xx_enable_pll()
1883 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in i9xx_enable_pll()
1921 const struct dpll *clock = &crtc_state->dpll; in vlv_prepare_pll()
2011 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); in _vlv_enable_pll()
2012 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in _vlv_enable_pll()
2015 if (intel_de_wait_for_set(dev_priv, DPLL(dev_priv, pipe), DPLL_LOCK_VLV, 1)) in _vlv_enable_pll()
2016 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); in _vlv_enable_pll()
2033 intel_de_write(dev_priv, DPLL(dev_priv, pipe), in vlv_enable_pll()
2034 hw_state->dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); in vlv_enable_pll()
2036 if (hw_state->dpll & DPLL_VCO_ENABLE) { in vlv_enable_pll()
2049 const struct dpll *clock = &crtc_state->dpll; in chv_prepare_pll()
2159 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); in _chv_enable_pll()
2162 if (intel_de_wait_for_set(dev_priv, DPLL(dev_priv, pipe), DPLL_LOCK_VLV, 1)) in _chv_enable_pll()
2180 intel_de_write(dev_priv, DPLL(dev_priv, pipe), in chv_enable_pll()
2181 hw_state->dpll & ~DPLL_VCO_ENABLE); in chv_enable_pll()
2183 if (hw_state->dpll & DPLL_VCO_ENABLE) { in chv_enable_pll()
2206 (intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) & in chv_enable_pll()
2219 * @dpll: PLL configuration
2221 * Enable the PLL for @pipe using the supplied @dpll config. To be used
2226 const struct dpll *dpll) in vlv_force_pll_on() argument
2238 crtc_state->dpll = *dpll; in vlv_force_pll_on()
2266 intel_de_write(dev_priv, DPLL(dev_priv, pipe), val); in vlv_disable_pll()
2267 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in vlv_disable_pll()
2284 intel_de_write(dev_priv, DPLL(dev_priv, pipe), val); in chv_disable_pll()
2285 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in chv_disable_pll()
2310 intel_de_write(dev_priv, DPLL(dev_priv, pipe), DPLL_VGA_MODE_DIS); in i9xx_disable_pll()
2311 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in i9xx_disable_pll()
2338 cur_state = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE; in assert_pll()