238 /* LVDS 100mhz refclk limits. */
317 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)  in pnv_calc_dpll_params()  argument
323 		DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);  in pnv_calc_dpll_params()
335 int i9xx_calc_dpll_params(int refclk, struct dpll *clock)  in i9xx_calc_dpll_params()  argument
341 		DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);  in i9xx_calc_dpll_params()
348 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)  in vlv_calc_dpll_params()  argument
354 		DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);  in vlv_calc_dpll_params()
361 int chv_calc_dpll_params(int refclk, struct dpll *clock)  in chv_calc_dpll_params()  argument
367 		DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), clock->n << 22);  in chv_calc_dpll_params()
431 	int refclk = i9xx_pll_refclk(crtc_state);  in i9xx_crtc_clock_get()  local
472 			port_clock = pnv_calc_dpll_params(refclk, &clock);  in i9xx_crtc_clock_get()
474 			port_clock = i9xx_calc_dpll_params(refclk, &clock);  in i9xx_crtc_clock_get()
503 		port_clock = i9xx_calc_dpll_params(refclk, &clock);  in i9xx_crtc_clock_get()
521 	int refclk = 100000;  in vlv_crtc_clock_get()  local
539 	crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock);  in vlv_crtc_clock_get()
551 	int refclk = 100000;  in chv_crtc_clock_get()  local
573 	crtc_state->port_clock = chv_calc_dpll_params(refclk, &clock);  in chv_crtc_clock_get()
577  * Returns whether the given set of divisors are valid for a given refclk with
645  * refclk, or FALSE.
655 		    int target, int refclk,  in i9xx_find_best_dpll()  argument
679 					i9xx_calc_dpll_params(refclk, &clock);  in i9xx_find_best_dpll()
703  * refclk, or FALSE.
713 		   int target, int refclk,  in pnv_find_best_dpll()  argument
735 					pnv_calc_dpll_params(refclk, &clock);  in pnv_find_best_dpll()
759  * refclk, or FALSE.
769 		   int target, int refclk,  in g4x_find_best_dpll()  argument
796 					i9xx_calc_dpll_params(refclk, &clock);  in g4x_find_best_dpll()
858  * refclk, or FALSE.
863 		   int target, int refclk,  in vlv_find_best_dpll()  argument
872 	int max_n = min(limit->n.max, refclk / 19200);  in vlv_find_best_dpll()
888 								     refclk * clock.m1);  in vlv_find_best_dpll()
890 					vlv_calc_dpll_params(refclk, &clock);  in vlv_find_best_dpll()
916  * refclk, or FALSE.
921 		   int target, int refclk,  in chv_find_best_dpll()  argument
937 	 * set to 2.  If requires to support 200Mhz refclk, we need to  in chv_find_best_dpll()
952 						   refclk * clock.m1);  in chv_find_best_dpll()
959 			chv_calc_dpll_params(refclk, &clock);  in chv_find_best_dpll()
981 	int refclk = 100000;  in bxt_find_best_dpll()  local
984 				  crtc_state->port_clock, refclk,  in bxt_find_best_dpll()
1369 	int refclk = 120000;  in ilk_crtc_compute_clock()  local
1381 			refclk = dev_priv->display.vbt.lvds_ssc_freq;  in ilk_crtc_compute_clock()
1385 			if (refclk == 100000)  in ilk_crtc_compute_clock()
1390 			if (refclk == 100000)  in ilk_crtc_compute_clock()
1401 				refclk, NULL, &crtc_state->dpll))  in ilk_crtc_compute_clock()
1404 	i9xx_calc_dpll_params(refclk, &crtc_state->dpll);  in ilk_crtc_compute_clock()
1490 	int refclk = 100000;  in chv_crtc_compute_clock()  local
1494 				refclk, NULL, &crtc_state->dpll))  in chv_crtc_compute_clock()
1497 	chv_calc_dpll_params(refclk, &crtc_state->dpll);  in chv_crtc_compute_clock()
1517 	int refclk = 100000;  in vlv_crtc_compute_clock()  local
1521 				refclk, NULL, &crtc_state->dpll))  in vlv_crtc_compute_clock()
1524 	vlv_calc_dpll_params(refclk, &crtc_state->dpll);  in vlv_crtc_compute_clock()
1546 	int refclk = 96000;  in g4x_crtc_compute_clock()  local
1550 			refclk = dev_priv->display.vbt.lvds_ssc_freq;  in g4x_crtc_compute_clock()
1553 				    refclk);  in g4x_crtc_compute_clock()
1572 				refclk, NULL, &crtc_state->dpll))  in g4x_crtc_compute_clock()
1575 	i9xx_calc_dpll_params(refclk, &crtc_state->dpll);  in g4x_crtc_compute_clock()
1596 	int refclk = 96000;  in pnv_crtc_compute_clock()  local
1600 			refclk = dev_priv->display.vbt.lvds_ssc_freq;  in pnv_crtc_compute_clock()
1603 				    refclk);  in pnv_crtc_compute_clock()
1613 				refclk, NULL, &crtc_state->dpll))  in pnv_crtc_compute_clock()
1616 	pnv_calc_dpll_params(refclk, &crtc_state->dpll);  in pnv_crtc_compute_clock()
1635 	int refclk = 96000;  in i9xx_crtc_compute_clock()  local
1639 			refclk = dev_priv->display.vbt.lvds_ssc_freq;  in i9xx_crtc_compute_clock()
1642 				    refclk);  in i9xx_crtc_compute_clock()
1652 				 refclk, NULL, &crtc_state->dpll))  in i9xx_crtc_compute_clock()
1655 	i9xx_calc_dpll_params(refclk, &crtc_state->dpll);  in i9xx_crtc_compute_clock()
1676 	int refclk = 48000;  in i8xx_crtc_compute_clock()  local
1680 			refclk = dev_priv->display.vbt.lvds_ssc_freq;  in i8xx_crtc_compute_clock()
1683 				    refclk);  in i8xx_crtc_compute_clock()
1695 				 refclk, NULL, &crtc_state->dpll))  in i8xx_crtc_compute_clock()
1698 	i9xx_calc_dpll_params(refclk, &crtc_state->dpll);  in i8xx_crtc_compute_clock()
2032 	/* Enable Refclk */  in vlv_enable_pll()
2070 	/* Feedback refclk divider - n and m1 */  in chv_prepare_pll()
2179 	/* Enable Refclk and SSC */  in chv_enable_pll()