Lines Matching defs:limit
582 const struct intel_limit *limit,
585 if (clock->n < limit->n.min || limit->n.max < clock->n)
587 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
589 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
591 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
602 if (clock->p < limit->p.min || limit->p.max < clock->p)
604 if (clock->m < limit->m.min || limit->m.max < clock->m)
608 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
613 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
620 i9xx_select_p2_div(const struct intel_limit *limit,
633 return limit->p2.p2_fast;
635 return limit->p2.p2_slow;
637 if (target < limit->p2.dot_limit)
638 return limit->p2.p2_slow;
640 return limit->p2.p2_fast;
654 i9xx_find_best_dpll(const struct intel_limit *limit,
666 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
668 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
670 for (clock.m2 = limit->m2.min;
671 clock.m2 <= limit->m2.max; clock.m2++) {
674 for (clock.n = limit->n.min;
675 clock.n <= limit->n.max; clock.n++) {
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
682 limit,
712 pnv_find_best_dpll(const struct intel_limit *limit,
724 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
726 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
728 for (clock.m2 = limit->m2.min;
729 clock.m2 <= limit->m2.max; clock.m2++) {
730 for (clock.n = limit->n.min;
731 clock.n <= limit->n.max; clock.n++) {
732 for (clock.p1 = limit->p1.min;
733 clock.p1 <= limit->p1.max; clock.p1++) {
738 limit,
768 g4x_find_best_dpll(const struct intel_limit *limit,
783 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
785 max_n = limit->n.max;
787 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
789 for (clock.m1 = limit->m1.max;
790 clock.m1 >= limit->m1.min; clock.m1--) {
791 for (clock.m2 = limit->m2.max;
792 clock.m2 >= limit->m2.min; clock.m2--) {
793 for (clock.p1 = limit->p1.max;
794 clock.p1 >= limit->p1.min; clock.p1--) {
799 limit,
862 vlv_find_best_dpll(const struct intel_limit *limit,
872 int max_n = min(limit->n.max, refclk / 19200);
878 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
879 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
880 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
884 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
893 limit,
919 chv_find_best_dpll(const struct intel_limit *limit,
942 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
943 for (clock.p2 = limit->p2.p2_fast;
944 clock.p2 >= limit->p2.p2_slow;
960 if (!intel_pll_is_valid(display, limit, &clock))
979 const struct intel_limit *limit = &intel_limits_bxt;
982 return chv_find_best_dpll(limit, crtc_state,
1297 * We'll limit this to IVB with 3 pipes, since it has only two
1357 const struct intel_limit *limit;
1375 limit = &ilk_limits_dual_lvds_100m;
1377 limit = &ilk_limits_dual_lvds;
1380 limit = &ilk_limits_single_lvds_100m;
1382 limit = &ilk_limits_single_lvds;
1385 limit = &ilk_limits_dac;
1389 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1478 const struct intel_limit *limit = &intel_limits_chv;
1482 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1505 const struct intel_limit *limit = &intel_limits_vlv;
1509 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1533 const struct intel_limit *limit;
1545 limit = &intel_limits_g4x_dual_channel_lvds;
1547 limit = &intel_limits_g4x_single_channel_lvds;
1550 limit = &intel_limits_g4x_hdmi;
1552 limit = &intel_limits_g4x_sdvo;
1555 limit = &intel_limits_i9xx_sdvo;
1559 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1582 const struct intel_limit *limit;
1593 limit = &pnv_limits_lvds;
1595 limit = &pnv_limits_sdvo;
1599 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1620 const struct intel_limit *limit;
1631 limit = &intel_limits_i9xx_lvds;
1633 limit = &intel_limits_i9xx_sdvo;
1637 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1660 const struct intel_limit *limit;
1671 limit = &intel_limits_i8xx_lvds;
1673 limit = &intel_limits_i8xx_dvo;
1675 limit = &intel_limits_i8xx_dac;
1679 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,