Lines Matching full:lane

51  * houses a common lane part which contains the PLL and other common
52  * logic. CH0 common lane also contains the IOSF-SB logic for the
67  * Additionally the PHY also contains an AUX lane with AUX blocks
73  * Generally on VLV/CHV the common lane corresponds to the pipe and
278  * Like intel_de_rmw() but reads from a single per-lane register and
302 	int lane, n_entries;
312 	 * can read only lane registers and we pick lanes 0/1 for that.
318 	for (lane = 0; lane < crtc_state->lane_count; lane++) {
319 		int level = intel_ddi_level(encoder, crtc_state, lane);
321 		intel_de_rmw(display, BXT_PORT_TX_DW2_LN(phy, ch, lane),
327 	for (lane = 0; lane < crtc_state->lane_count; lane++) {
328 		int level = intel_ddi_level(encoder, crtc_state, lane);
331 		intel_de_rmw(display, BXT_PORT_TX_DW3_LN(phy, ch, lane),
336 		val = intel_de_read(display, BXT_PORT_TX_DW3_LN(phy, ch, lane));
342 	for (lane = 0; lane < crtc_state->lane_count; lane++) {
343 		int level = intel_ddi_level(encoder, crtc_state, lane);
345 		intel_de_rmw(display, BXT_PORT_TX_DW4_LN(phy, ch, lane),
620 	int lane;
624 	for (lane = 0; lane < 4; lane++) {
629 		intel_de_rmw(display, BXT_PORT_TX_DW14_LN(phy, ch, lane),
631 			     lane_lat_optim_mask & BIT(lane) ? LATENCY_OPTIM : 0);
642 	int lane;
648 	for (lane = 0; lane < 4; lane++) {
650 					BXT_PORT_TX_DW14_LN(phy, ch, lane));
653 			mask |= BIT(lane);
881 	 * Must trick the second common lane into life.
892 	/* Assert data lane reset */
972 	/* Program Tx lane latency optimal setting*/
982 	/* Data lane stagger programming */
1020 	/* Deassert data lane reset */
1062 	 * lane so that chv_powergate_phy_ch() will power
1108 	/* Program Tx lane resets to default */
1149 	/* Program lane clock */