Lines Matching full:dmc
46 * DOC: DMC Firmware Support
48 * From gen9 onwards we have newly added DMC (Display microcontroller) in display
89 return display->dmc.dmc;
115 * New DMC additions should not use this. This is used solely to remain
116 * compatible with systems that have not yet updated DMC blobs to use
263 /* 0x09 for DMC */
266 /* Includes the DMC specific header in dwords */
281 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
323 /* DMC container header length in dwords */
339 /* DMC binary header length */
379 /* DMC RAM start MMIO address */
412 struct intel_dmc *dmc = display_to_dmc(display);
414 return dmc && dmc->dmc_info[dmc_id].payload;
594 * TGL/ADL-S DMC firmware incorrectly uses the undelayed vblank
618 /* keep all pipe DMC events disabled by default */
622 /* also disable the flip queue event on the main DMC on TGL */
627 /* also disable the HRR event on the main DMC on TGL/ADLS */
636 struct intel_dmc *dmc,
640 dmc->dmc_info[dmc_id].mmioaddr[i],
641 dmc->dmc_info[dmc_id].mmiodata[i]))
642 return dmc_evt_ctl_disable(dmc->dmc_info[dmc_id].mmiodata[i]);
644 return dmc->dmc_info[dmc_id].mmiodata[i];
649 struct intel_dmc *dmc = display_to_dmc(display);
652 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) {
653 intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i],
654 dmc_mmiodata(display, dmc, dmc_id, i));
660 struct intel_dmc *dmc = display_to_dmc(display);
667 for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) {
669 DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i),
670 dmc->dmc_info[dmc_id].payload[i]);
681 struct intel_dmc *dmc = display_to_dmc(display);
688 found = intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, 0));
689 expected = dmc->dmc_info[dmc_id].payload[0];
692 "DMC %d program storage start incorrect (expected 0x%x, current 0x%x)\n",
695 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) {
696 i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i];
699 expected = dmc_mmiodata(display, dmc, dmc_id, i);
702 "DMC %d mmio[%d]/0x%x incorrect (expected 0x%x, current 0x%x)\n",
714 /* On TGL/derivatives pipe DMC state is lost when PG1 is disabled */
722 * - pipe A/B DMC doesn't need save/restore
723 * - pipe C/D DMC is in PG0, needs manual save/restore
729 * FIXME LNL unclear, main DMC firmware has the pipe DMC A/B PG0
730 * save/restore, but so far unable to see the loss of pipe DMC state
738 * FIXME BMG untested, main DMC firmware has the
739 * pipe DMC A/B PG0 save/restore...
748 * in loss of DMC state for whatever reason
755 * - pipe A/B DMC is in PG0, saved/restored by the main DMC
756 * - pipe C/D DMC is in PG0, needs manual save/restore
769 * On TGL/derivatives pipe DMC state is lost when PG1 is disabled.
770 * Do not even enable the pipe DMC when that can happen outside
842 struct intel_dmc *dmc = display_to_dmc(display);
846 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) {
847 i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i];
848 u32 data = dmc->dmc_info[dmc_id].mmiodata[i];
858 "DMC %d has %d handlers for event 0x%x\n",
901 * DMC firmware is read from a .bin file and kept in internal memory one time.
979 static void dmc_set_fw_offset(struct intel_dmc *dmc,
985 struct intel_display *display = dmc->display;
1001 if (dmc->dmc_info[dmc_id].present)
1005 dmc->dmc_info[dmc_id].present = true;
1006 dmc->dmc_info[dmc_id].dmc_offset = fw_info[i].offset;
1011 static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc,
1015 struct intel_display *display = dmc->display;
1044 static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
1048 struct intel_display *display = dmc->display;
1049 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id];
1096 drm_err(display->drm, "Unknown DMC fw header version: %u\n",
1102 drm_err(display->drm, "DMC firmware has wrong dmc header length "
1107 /* Cache the dmc header info. */
1109 drm_err(display->drm, "DMC firmware has wrong mmio count %u\n", mmio_count);
1113 if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count,
1115 drm_err(display->drm, "DMC firmware has Wrong MMIO Addresses\n");
1119 drm_dbg_kms(display->drm, "DMC %d:\n", dmc_id);
1164 if (payload_size > dmc->max_fw_size) {
1165 drm_err(display->drm, "DMC FW too big (%u bytes)\n", payload_size);
1180 drm_err(display->drm, "Truncated DMC firmware, refusing.\n");
1185 parse_dmc_fw_package(struct intel_dmc *dmc,
1190 struct intel_display *display = dmc->display;
1203 drm_err(display->drm, "DMC firmware has unknown header version %u\n",
1217 drm_err(display->drm, "DMC firmware has wrong package header length "
1228 dmc_set_fw_offset(dmc, fw_info, num_entries, si,
1235 drm_err(display->drm, "Truncated DMC firmware, refusing.\n");
1240 static u32 parse_dmc_fw_css(struct intel_dmc *dmc,
1244 struct intel_display *display = dmc->display;
1247 drm_err(display->drm, "Truncated DMC firmware, refusing.\n");
1253 drm_err(display->drm, "DMC firmware has wrong CSS header length "
1259 dmc->version = css_header->version;
1264 static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw)
1266 struct intel_display *display = dmc->display;
1281 r = parse_dmc_fw_css(dmc, css_header, fw->size);
1289 r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount);
1296 if (!dmc->dmc_info[dmc_id].present)
1299 offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4;
1306 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, dmc_id);
1310 drm_err(display->drm, "DMC firmware main program not found\n");
1319 drm_WARN_ON(display->drm, display->dmc.wakeref);
1320 display->dmc.wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT);
1326 fetch_and_zero(&display->dmc.wakeref);
1341 struct intel_dmc *dmc = container_of(work, typeof(*dmc), work);
1342 struct intel_display *display = dmc->display;
1347 err = request_firmware(&fw, dmc->fw_path, display->drm->dev);
1353 dmc->fw_path, fallback_path);
1356 dmc->fw_path = fallback_path;
1362 "Failed to load DMC firmware %s (%pe). Disabling runtime power management.\n",
1363 dmc->fw_path, ERR_PTR(err));
1364 drm_notice(display->drm, "DMC firmware homepage: %s",
1369 err = parse_dmc_fw(dmc, fw);
1372 "Failed to parse DMC firmware %s (%pe). Disabling runtime power management.\n",
1373 dmc->fw_path, ERR_PTR(err));
1380 drm_info(display->drm, "Finished loading DMC firmware %s (v%u.%u)\n",
1381 dmc->fw_path, DMC_VERSION_MAJOR(dmc->version),
1382 DMC_VERSION_MINOR(dmc->version));
1397 struct intel_dmc *dmc;
1403 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering
1407 * suspend as runtime suspend *requires* a working DMC for whatever
1412 dmc = kzalloc(sizeof(*dmc), GFP_KERNEL);
1413 if (!dmc)
1416 dmc->display = display;
1418 INIT_WORK(&dmc->work, dmc_load_work_fn);
1420 dmc->fw_path = dmc_firmware_default(display, &dmc->max_fw_size);
1423 drm_info(display->drm, "Disabling DMC firmware and runtime PM\n");
1428 dmc->fw_path = dmc_firmware_param(display);
1430 if (!dmc->fw_path) {
1432 "No known DMC firmware for platform, disabling runtime PM\n");
1436 display->dmc.dmc = dmc;
1438 drm_dbg_kms(display->drm, "Loading %s\n", dmc->fw_path);
1439 queue_work(display->wq.unordered, &dmc->work);
1444 kfree(dmc);
1448 * intel_dmc_suspend() - prepare DMC firmware before system suspend
1451 * Prepare the DMC firmware before entering system suspend. This includes
1457 struct intel_dmc *dmc = display_to_dmc(display);
1462 if (dmc)
1463 flush_work(&dmc->work);
1465 /* Drop the reference held in case DMC isn't loaded. */
1472 struct intel_dmc *dmc = display_to_dmc(display);
1477 if (dmc)
1478 flush_work(&dmc->work);
1482 * intel_dmc_resume() - init DMC firmware during system resume
1485 * Reinitialize the DMC firmware during system resume, reacquiring any
1494 * Reacquire the reference to keep RPM disabled in case DMC isn't
1502 * intel_dmc_fini() - unload the DMC firmware.
1510 struct intel_dmc *dmc = display_to_dmc(display);
1517 drm_WARN_ON(display->drm, display->dmc.wakeref);
1519 if (dmc) {
1521 kfree(dmc->dmc_info[dmc_id].payload);
1523 kfree(dmc);
1524 display->dmc.dmc = NULL;
1536 struct intel_dmc *dmc = display_to_dmc(display);
1546 snapshot->initialized = dmc;
1548 if (dmc)
1549 snapshot->version = dmc->version;
1559 drm_printf(p, "DMC initialized: %s\n", str_yes_no(snapshot->initialized));
1560 drm_printf(p, "DMC loaded: %s\n", str_yes_no(snapshot->loaded));
1562 drm_printf(p, "DMC fw version: %d.%d\n",
1570 struct intel_dmc *dmc = display_to_dmc(display);
1573 if (DISPLAY_VER(dmc->display) < 14)
1576 dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT);
1579 dmc->dc6_allowed.count += dc5_cur_count - dmc->dc6_allowed.dc5_start;
1581 dmc->dc6_allowed.dc5_start = dc5_cur_count;
1587 struct intel_dmc *dmc = display_to_dmc(display);
1599 *count = dmc->dc6_allowed.count;
1608 struct intel_dmc *dmc = display_to_dmc(display);
1618 seq_printf(m, "DMC initialized: %s\n", str_yes_no(dmc));
1621 seq_printf(m, "path: %s\n", dmc ? dmc->fw_path : "N/A");
1635 seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version),
1636 DMC_VERSION_MINOR(dmc->version));
1669 intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
1753 struct intel_dmc *dmc = display_to_dmc(display);
1756 return dmc ? dmc->dmc_info[dmc_id].start_mmioaddr : 0;