2  * Copyright © 2006-2007 Intel Corporation
27 #include <linux/dma-resv.h>
147 	return (crtc_state->active_planes &  in is_hdr_mode()
183 	return crtc_state->master_transcoder != INVALID_TRANSCODER;  in is_trans_port_sync_slave()
189 	return crtc_state->sync_mode_slaves_mask != 0;  in is_trans_port_sync_master()
201 	return ffs(crtc_state->joiner_pipes) - 1;  in joiner_primary_pipe()
210 	return hweight8(crtc_state->joiner_pipes) >= 2;  in is_bigjoiner()
218 	return crtc_state->joiner_pipes & (0b01010101 << joiner_primary_pipe(crtc_state));  in bigjoiner_primary_pipes()
226 	return crtc_state->joiner_pipes & (0b10101010 << joiner_primary_pipe(crtc_state));  in bigjoiner_secondary_pipes()
231 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_is_bigjoiner_primary()
236 	return BIT(crtc->pipe) & bigjoiner_primary_pipes(crtc_state);  in intel_crtc_is_bigjoiner_primary()
241 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_is_bigjoiner_secondary()
246 	return BIT(crtc->pipe) & bigjoiner_secondary_pipes(crtc_state);  in intel_crtc_is_bigjoiner_secondary()
251 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in _intel_modeset_primary_pipes()
254 		return BIT(crtc->pipe);  in _intel_modeset_primary_pipes()
274 	return crtc_state->joiner_pipes & (0b00010001 << joiner_primary_pipe(crtc_state));  in ultrajoiner_primary_pipes()
279 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_is_ultrajoiner_primary()
282 	       BIT(crtc->pipe) & ultrajoiner_primary_pipes(crtc_state);  in intel_crtc_is_ultrajoiner_primary()
295 	return crtc_state->joiner_pipes & (0b01110111 << joiner_primary_pipe(crtc_state));  in ultrajoiner_enable_pipes()
300 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_ultrajoiner_enable_needed()
303 	       BIT(crtc->pipe) & ultrajoiner_enable_pipes(crtc_state);  in intel_crtc_ultrajoiner_enable_needed()
308 	if (crtc_state->joiner_pipes)  in intel_crtc_joiner_secondary_pipes()
309 		return crtc_state->joiner_pipes & ~BIT(joiner_primary_pipe(crtc_state));  in intel_crtc_joiner_secondary_pipes()
316 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_is_joiner_secondary()
318 	return crtc_state->joiner_pipes &&  in intel_crtc_is_joiner_secondary()
319 		crtc->pipe != joiner_primary_pipe(crtc_state);  in intel_crtc_is_joiner_secondary()
324 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_is_joiner_primary()
326 	return crtc_state->joiner_pipes &&  in intel_crtc_is_joiner_primary()
327 		crtc->pipe == joiner_primary_pipe(crtc_state);  in intel_crtc_is_joiner_primary()
337 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_joined_pipe_mask()
339 	return BIT(crtc->pipe) | crtc_state->joiner_pipes;  in intel_crtc_joined_pipe_mask()
349 		return to_intel_crtc(crtc_state->uapi.crtc);  in intel_primary_crtc()
356 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);  in intel_wait_for_pipe_off()
359 		enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;  in intel_wait_for_pipe_off()
364 			drm_WARN(display->drm, 1, "pipe_off wait timed out\n");  in intel_wait_for_pipe_off()
378 	if (display->platform.i830)  in assert_transcoder()
401 	struct intel_display *display = to_intel_display(plane->base.dev);  in assert_plane()
405 	cur_state = plane->get_hw_state(plane, &pipe);  in assert_plane()
409 				 plane->base.name, str_on_off(state),  in assert_plane()
421 	for_each_intel_plane_on_crtc(display->drm, crtc, plane)  in assert_planes_disabled()
428 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);  in intel_enable_transcoder()
429 	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;  in intel_enable_transcoder()
430 	enum pipe pipe = crtc->pipe;  in intel_enable_transcoder()
433 	drm_dbg_kms(display->drm, "enabling pipe %c\n", pipe_name(pipe));  in intel_enable_transcoder()
448 		if (new_crtc_state->has_pch_encoder) {  in intel_enable_transcoder()
458 	/* Wa_22012358565:adl-p */  in intel_enable_transcoder()
477 		drm_WARN_ON(display->drm, !display->platform.i830);  in intel_enable_transcoder()
483 	    new_crtc_state->dsc.compression_enable) {  in intel_enable_transcoder()
507 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);  in intel_disable_transcoder()
508 	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;  in intel_disable_transcoder()
509 	enum pipe pipe = crtc->pipe;  in intel_disable_transcoder()
512 	drm_dbg_kms(display->drm, "disabling pipe %c\n", pipe_name(pipe));  in intel_disable_transcoder()
528 	if (old_crtc_state->double_wide)  in intel_disable_transcoder()
532 	if (!display->platform.i830)  in intel_disable_transcoder()
537 	    old_crtc_state->dsc.compression_enable)  in intel_disable_transcoder()
566 	plane = to_intel_plane(crtc->base.primary);  in intel_plane_fb_max_stride()
568 	return plane->max_stride(plane, info, modifier,  in intel_plane_fb_max_stride()
589 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);  in intel_set_plane_visible()
591 	plane_state->uapi.visible = visible;  in intel_set_plane_visible()
594 		crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);  in intel_set_plane_visible()
596 		crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);  in intel_set_plane_visible()
609 	crtc_state->enabled_planes = 0;  in intel_plane_fixup_bitmasks()
610 	crtc_state->active_planes = 0;  in intel_plane_fixup_bitmasks()
612 	drm_for_each_plane_mask(plane, display->drm,  in intel_plane_fixup_bitmasks()
613 				crtc_state->uapi.plane_mask) {  in intel_plane_fixup_bitmasks()
614 		crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);  in intel_plane_fixup_bitmasks()
615 		crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);  in intel_plane_fixup_bitmasks()
624 		to_intel_crtc_state(crtc->base.state);  in intel_plane_disable_noatomic()
626 		to_intel_plane_state(plane->base.state);  in intel_plane_disable_noatomic()
628 	drm_dbg_kms(display->drm,  in intel_plane_disable_noatomic()
630 		    plane->base.base.id, plane->base.name,  in intel_plane_disable_noatomic()
631 		    crtc->base.base.id, crtc->base.name);  in intel_plane_disable_noatomic()
639 	if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&  in intel_plane_disable_noatomic()
641 		crtc_state->ips_enabled = false;  in intel_plane_disable_noatomic()
647 	 * are blocked if the memory self-refresh mode is active at that  in intel_plane_disable_noatomic()
649 	 * first the self-refresh mode. The self-refresh enable bit in turn  in intel_plane_disable_noatomic()
652 	 * wait-for-vblank between disabling the plane and the pipe.  in intel_plane_disable_noatomic()
662 	if (DISPLAY_VER(display) == 2 && !crtc_state->active_planes)  in intel_plane_disable_noatomic()
663 		intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, false);  in intel_plane_disable_noatomic()
675 					  plane_state->view.color_plane[0].offset, 0);  in intel_plane_fence_y_offset()
683 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in icl_set_pipe_chicken()
684 	enum pipe pipe = crtc->pipe;  in icl_set_pipe_chicken()
692 	 * and rounding for per-pixel values 00 and 0xff  in icl_set_pipe_chicken()
707 	if (display->platform.dg2)  in icl_set_pipe_chicken()
713 	if (display->platform.dg2)  in icl_set_pipe_chicken()
724 	drm_for_each_crtc(crtc, display->drm) {  in intel_has_pending_fb_unpin()
726 		spin_lock(&crtc->commit_lock);  in intel_has_pending_fb_unpin()
727 		commit = list_first_entry_or_null(&crtc->commit_list,  in intel_has_pending_fb_unpin()
730 			try_wait_for_completion(&commit->cleanup_done) : true;  in intel_has_pending_fb_unpin()
731 		spin_unlock(&crtc->commit_lock);  in intel_has_pending_fb_unpin()
761 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in intel_get_crtc_new_encoder()
762 		if (connector_state->crtc != &primary_crtc->base)  in intel_get_crtc_new_encoder()
765 		encoder = to_intel_encoder(connector_state->best_encoder);  in intel_get_crtc_new_encoder()
769 	drm_WARN(state->base.dev, num_encoders != 1,  in intel_get_crtc_new_encoder()
771 		 num_encoders, pipe_name(primary_crtc->pipe));  in intel_get_crtc_new_encoder()
778 	if (crtc->overlay)  in intel_crtc_dpms_overlay_disable()
779 		(void) intel_overlay_switch_off(crtc->overlay);  in intel_crtc_dpms_overlay_disable()
790 	if (!crtc_state->nv12_planes)  in needs_nv12_wa()
805 	if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(display) == 11)  in needs_scalerclk_wa()
817 	    crtc_state->active_planes & BIT(PLANE_CURSOR) &&  in needs_cursorclk_wa()
847 	return crtc_state->uapi.async_flip && intel_display_vtd_active(display) &&  in needs_async_flip_vtd_wa()
848 		(DISPLAY_VER(display) == 9 || display->platform.broadwell ||  in needs_async_flip_vtd_wa()
849 		 display->platform.haswell);  in needs_async_flip_vtd_wa()
861 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_audio_enable()
863 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_audio_enable()
865 		if (conn_state->crtc != &crtc->base)  in intel_encoders_audio_enable()
868 		if (encoder->audio_enable)  in intel_encoders_audio_enable()
869 			encoder->audio_enable(encoder, crtc_state, conn_state);  in intel_encoders_audio_enable()
882 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {  in intel_encoders_audio_disable()
884 			to_intel_encoder(old_conn_state->best_encoder);  in intel_encoders_audio_disable()
886 		if (old_conn_state->crtc != &crtc->base)  in intel_encoders_audio_disable()
889 		if (encoder->audio_disable)  in intel_encoders_audio_disable()
890 			encoder->audio_disable(encoder, old_crtc_state, old_conn_state);  in intel_encoders_audio_disable()
895 	((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \
896 	 (new_crtc_state)->feature)
898 	((old_crtc_state)->feature && \
899 	 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)))
904 	if (!new_crtc_state->hw.active)  in planes_enabling()
913 	if (!old_crtc_state->hw.active)  in planes_disabling()
922 	return old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline ||  in vrr_params_changed()
923 		old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin ||  in vrr_params_changed()
924 		old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax ||  in vrr_params_changed()
925 		old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband ||  in vrr_params_changed()
926 		old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full ||  in vrr_params_changed()
927 		old_crtc_state->vrr.vsync_start != new_crtc_state->vrr.vsync_start ||  in vrr_params_changed()
928 		old_crtc_state->vrr.vsync_end != new_crtc_state->vrr.vsync_end;  in vrr_params_changed()
934 	return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||  in cmrr_params_changed()
935 		old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;  in cmrr_params_changed()
946 	if (!new_crtc_state->hw.active)  in intel_crtc_vrr_enabling()
950 		(new_crtc_state->vrr.enable &&  in intel_crtc_vrr_enabling()
951 		 (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||  in intel_crtc_vrr_enabling()
963 	if (!old_crtc_state->hw.active)  in intel_crtc_vrr_disabling()
967 		(old_crtc_state->vrr.enable &&  in intel_crtc_vrr_disabling()
968 		 (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||  in intel_crtc_vrr_disabling()
975 	if (!new_crtc_state->hw.active)  in audio_enabling()
979 		(new_crtc_state->has_audio &&  in audio_enabling()
980 		 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0);  in audio_enabling()
986 	if (!old_crtc_state->hw.active)  in audio_disabling()
990 		(old_crtc_state->has_audio &&  in audio_disabling()
991 		 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0);  in audio_disabling()
997 	if (!new_crtc_state->hw.active)  in intel_casf_enabling()
1006 	if (!new_crtc_state->hw.active)  in intel_casf_disabling()
1023 	enum pipe pipe = crtc->pipe;  in intel_post_plane_update()
1025 	intel_frontbuffer_flip(display, new_crtc_state->fb_bits);  in intel_post_plane_update()
1027 	if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)  in intel_post_plane_update()
1055 		if (old_crtc_state->pch_pfit.enabled != new_crtc_state->pch_pfit.enabled)  in intel_post_plane_update()
1085 	u8 update_planes = crtc_state->update_planes;  in intel_crtc_enable_flip_done()
1091 		if (plane->pipe == crtc->pipe &&  in intel_crtc_enable_flip_done()
1092 		    update_planes & BIT(plane->id))  in intel_crtc_enable_flip_done()
1093 			plane->enable_flip_done(plane);  in intel_crtc_enable_flip_done()
1102 	u8 update_planes = crtc_state->update_planes;  in intel_crtc_disable_flip_done()
1108 		if (plane->pipe == crtc->pipe &&  in intel_crtc_disable_flip_done()
1109 		    update_planes & BIT(plane->id))  in intel_crtc_disable_flip_done()
1110 			plane->disable_flip_done(plane);  in intel_crtc_disable_flip_done()
1121 	u8 disable_async_flip_planes = old_crtc_state->async_flip_planes &  in intel_crtc_async_flip_disable_wa()
1122 				       ~new_crtc_state->async_flip_planes;  in intel_crtc_async_flip_disable_wa()
1129 		if (plane->need_async_flip_toggle_wa &&  in intel_crtc_async_flip_disable_wa()
1130 		    plane->pipe == crtc->pipe &&  in intel_crtc_async_flip_disable_wa()
1131 		    disable_async_flip_planes & BIT(plane->id)) {  in intel_crtc_async_flip_disable_wa()
1154 	enum pipe pipe = crtc->pipe;  in intel_pre_plane_update()
1199 	 * are blocked if the memory self-refresh mode is active at that  in intel_pre_plane_update()
1201 	 * first the self-refresh mode. The self-refresh enable bit in turn  in intel_pre_plane_update()
1204 	 * wait-for-vblank between disabling the plane and the pipe.  in intel_pre_plane_update()
1206 	if (HAS_GMCH(display) && old_crtc_state->hw.active &&  in intel_pre_plane_update()
1207 	    new_crtc_state->disable_cxsr && intel_set_memory_cxsr(display, false))  in intel_pre_plane_update()
1212 	 * one frame before enabling scaling.  LP watermarks can be re-enabled  in intel_pre_plane_update()
1217 	if (!HAS_GMCH(display) && old_crtc_state->hw.active &&  in intel_pre_plane_update()
1218 	    new_crtc_state->disable_cxsr && ilk_disable_cxsr(display))  in intel_pre_plane_update()
1223 	 * pre-vblank watermark programming here.  in intel_pre_plane_update()
1228 		 * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these  in intel_pre_plane_update()
1229 		 * will be the intermediate values that are safe for both pre- and  in intel_pre_plane_update()
1230 		 * post- vblank; when vblank happens, the 'active' values will be set  in intel_pre_plane_update()
1241 			if (new_crtc_state->update_wm_pre)  in intel_pre_plane_update()
1260 	if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes)  in intel_pre_plane_update()
1270 	unsigned int update_mask = new_crtc_state->update_planes;  in intel_crtc_disable_planes()
1279 		if (crtc->pipe != plane->pipe ||  in intel_crtc_disable_planes()
1280 		    !(update_mask & BIT(plane->id)))  in intel_crtc_disable_planes()
1285 		if (old_plane_state->uapi.visible)  in intel_crtc_disable_planes()
1286 			fb_bits |= plane->frontbuffer_bit;  in intel_crtc_disable_planes()
1300 	 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.  in intel_encoders_update_prepare()
1301 	 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.  in intel_encoders_update_prepare()
1303 	if (display->dpll.mgr) {  in intel_encoders_update_prepare()
1308 			new_crtc_state->intel_dpll = old_crtc_state->intel_dpll;  in intel_encoders_update_prepare()
1309 			new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;  in intel_encoders_update_prepare()
1323 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_pre_pll_enable()
1325 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_pre_pll_enable()
1327 		if (conn_state->crtc != &crtc->base)  in intel_encoders_pre_pll_enable()
1330 		if (encoder->pre_pll_enable)  in intel_encoders_pre_pll_enable()
1331 			encoder->pre_pll_enable(state, encoder,  in intel_encoders_pre_pll_enable()
1345 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_pre_enable()
1347 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_pre_enable()
1349 		if (conn_state->crtc != &crtc->base)  in intel_encoders_pre_enable()
1352 		if (encoder->pre_enable)  in intel_encoders_pre_enable()
1353 			encoder->pre_enable(state, encoder,  in intel_encoders_pre_enable()
1367 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_enable()
1369 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_enable()
1371 		if (conn_state->crtc != &crtc->base)  in intel_encoders_enable()
1374 		if (encoder->enable)  in intel_encoders_enable()
1375 			encoder->enable(state, encoder,  in intel_encoders_enable()
1390 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {  in intel_encoders_disable()
1392 			to_intel_encoder(old_conn_state->best_encoder);  in intel_encoders_disable()
1394 		if (old_conn_state->crtc != &crtc->base)  in intel_encoders_disable()
1398 		if (encoder->disable)  in intel_encoders_disable()
1399 			encoder->disable(state, encoder,  in intel_encoders_disable()
1413 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {  in intel_encoders_post_disable()
1415 			to_intel_encoder(old_conn_state->best_encoder);  in intel_encoders_post_disable()
1417 		if (old_conn_state->crtc != &crtc->base)  in intel_encoders_post_disable()
1420 		if (encoder->post_disable)  in intel_encoders_post_disable()
1421 			encoder->post_disable(state, encoder,  in intel_encoders_post_disable()
1435 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {  in intel_encoders_post_pll_disable()
1437 			to_intel_encoder(old_conn_state->best_encoder);  in intel_encoders_post_pll_disable()
1439 		if (old_conn_state->crtc != &crtc->base)  in intel_encoders_post_pll_disable()
1442 		if (encoder->post_pll_disable)  in intel_encoders_post_pll_disable()
1443 			encoder->post_pll_disable(state, encoder,  in intel_encoders_post_pll_disable()
1457 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_update_pipe()
1459 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_update_pipe()
1461 		if (conn_state->crtc != &crtc->base)  in intel_encoders_update_pipe()
1464 		if (encoder->update_pipe)  in intel_encoders_update_pipe()
1465 			encoder->update_pipe(state, encoder,  in intel_encoders_update_pipe()
1472 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in ilk_configure_cpu_transcoder()
1473 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in ilk_configure_cpu_transcoder()
1475 	if (crtc_state->has_pch_encoder) {  in ilk_configure_cpu_transcoder()
1477 					       &crtc_state->fdi_m_n);  in ilk_configure_cpu_transcoder()
1480 					       &crtc_state->dp_m_n);  in ilk_configure_cpu_transcoder()
1482 					       &crtc_state->dp_m2_n2);  in ilk_configure_cpu_transcoder()
1496 	enum pipe pipe = crtc->pipe;  in ilk_crtc_enable()
1498 	if (drm_WARN_ON(display->drm, crtc->active))  in ilk_crtc_enable()
1518 	crtc->active = true;  in ilk_crtc_enable()
1522 	if (new_crtc_state->has_pch_encoder) {  in ilk_crtc_enable()
1540 	if (new_crtc_state->has_pch_encoder)  in ilk_crtc_enable()
1556 	if (new_crtc_state->has_pch_encoder) {  in ilk_crtc_enable()
1569 	return DISPLAY_VER(display) == 10 && crtc_state->pch_pfit.enabled;  in glk_need_scaler_clock_gating_wa()
1577 	intel_de_rmw(display, CLKGATE_DIS_PSL(crtc->pipe),  in glk_pipe_scaler_clock_gating_wa()
1584 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_set_linetime_wm()
1586 	intel_de_write(display, WM_LINETIME(crtc->pipe),  in hsw_set_linetime_wm()
1587 		       HSW_LINETIME(crtc_state->linetime) |  in hsw_set_linetime_wm()
1588 		       HSW_IPS_LINETIME(crtc_state->ips_linetime));  in hsw_set_linetime_wm()
1595 	intel_de_rmw(display, CHICKEN_TRANS(display, crtc_state->cpu_transcoder),  in hsw_set_frame_start_delay()
1597 		     HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1));  in hsw_set_frame_start_delay()
1603 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_configure_cpu_transcoder()
1604 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in hsw_configure_cpu_transcoder()
1606 	if (crtc_state->has_pch_encoder) {  in hsw_configure_cpu_transcoder()
1608 					       &crtc_state->fdi_m_n);  in hsw_configure_cpu_transcoder()
1611 					       &crtc_state->dp_m_n);  in hsw_configure_cpu_transcoder()
1613 					       &crtc_state->dp_m2_n2);  in hsw_configure_cpu_transcoder()
1621 			       crtc_state->pixel_multiplier - 1);  in hsw_configure_cpu_transcoder()
1634 	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;  in hsw_crtc_enable()
1638 	if (drm_WARN_ON(display->drm, crtc->active))  in hsw_crtc_enable()
1649 	if (new_crtc_state->intel_dpll)  in hsw_crtc_enable()
1665 		if (DISPLAY_VER(display) >= 9 || display->platform.broadwell)  in hsw_crtc_enable()
1676 		pipe_crtc->active = true;  in hsw_crtc_enable()
1716 		hsw_workaround_pipe = pipe_crtc_state->hsw_workaround_pipe;  in hsw_crtc_enable()
1717 		if (display->platform.haswell && hsw_workaround_pipe != INVALID_PIPE) {  in hsw_crtc_enable()
1733 	enum pipe pipe = crtc->pipe;  in ilk_crtc_disable()
1751 	if (old_crtc_state->has_pch_encoder)  in ilk_crtc_disable()
1756 	if (old_crtc_state->has_pch_encoder)  in ilk_crtc_disable()
1774 	 * Need care with mst->ddi interactions.  in hsw_crtc_disable()
1796 	else if (display->platform.alderlake_s)  in intel_phy_is_combo()
1798 	else if (display->platform.dg1 || display->platform.rocketlake)  in intel_phy_is_combo()
1800 	else if (display->platform.jasperlake || display->platform.elkhartlake)  in intel_phy_is_combo()
1802 	else if (display->platform.alderlake_p || IS_DISPLAY_VER(display, 11, 12))  in intel_phy_is_combo()
1818 	 * subsystem Legacy or non-legacy, and only support native DP/HDMI  in intel_phy_is_tc()
1820 	if (display->platform.dgfx)  in intel_phy_is_tc()
1825 	else if (display->platform.tigerlake)  in intel_phy_is_tc()
1827 	else if (display->platform.icelake)  in intel_phy_is_tc()
1840 	return display->platform.dg2 && phy > PHY_NONE && phy <= PHY_E;  in intel_phy_is_snps()
1847 		return PHY_D + port - PORT_D_XELPD;  in intel_port_to_phy()
1849 		return PHY_F + port - PORT_TC1;  in intel_port_to_phy()
1850 	else if (display->platform.alderlake_s && port >= PORT_TC1)  in intel_port_to_phy()
1851 		return PHY_B + port - PORT_TC1;  in intel_port_to_phy()
1852 	else if ((display->platform.dg1 || display->platform.rocketlake) && port >= PORT_TC1)  in intel_port_to_phy()
1853 		return PHY_C + port - PORT_TC1;  in intel_port_to_phy()
1854 	else if ((display->platform.jasperlake || display->platform.elkhartlake) &&  in intel_port_to_phy()
1858 	return PHY_A + port - PORT_A;  in intel_port_to_phy()
1868 		return TC_PORT_1 + port - PORT_TC1;  in intel_port_to_tc()
1870 		return TC_PORT_1 + port - PORT_C;  in intel_port_to_tc()
1877 	return intel_port_to_phy(display, encoder->port);  in intel_encoder_to_phy()
1905 	return intel_port_to_tc(display, encoder->port);  in intel_encoder_to_tc()
1914 		return intel_display_power_tbt_aux_domain(display, dig_port->aux_ch);  in intel_aux_power_domain()
1916 	return intel_display_power_legacy_aux_domain(display, dig_port->aux_ch);  in intel_aux_power_domain()
1923 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in get_crtc_power_domains()
1924 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in get_crtc_power_domains()
1926 	enum pipe pipe = crtc->pipe;  in get_crtc_power_domains()
1928 	bitmap_zero(mask->bits, POWER_DOMAIN_NUM);  in get_crtc_power_domains()
1930 	if (!crtc_state->hw.active)  in get_crtc_power_domains()
1933 	set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);  in get_crtc_power_domains()
1934 	set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);  in get_crtc_power_domains()
1935 	if (crtc_state->pch_pfit.enabled ||  in get_crtc_power_domains()
1936 	    crtc_state->pch_pfit.force_thru)  in get_crtc_power_domains()
1937 		set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);  in get_crtc_power_domains()
1939 	drm_for_each_encoder_mask(encoder, display->drm,  in get_crtc_power_domains()
1940 				  crtc_state->uapi.encoder_mask) {  in get_crtc_power_domains()
1943 		set_bit(intel_encoder->power_domain, mask->bits);  in get_crtc_power_domains()
1946 	if (HAS_DDI(display) && crtc_state->has_audio)  in get_crtc_power_domains()
1947 		set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);  in get_crtc_power_domains()
1949 	if (crtc_state->intel_dpll)  in get_crtc_power_domains()
1950 		set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);  in get_crtc_power_domains()
1952 	if (crtc_state->dsc.compression_enable)  in get_crtc_power_domains()
1953 		set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);  in get_crtc_power_domains()
1960 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_modeset_get_crtc_power_domains()
1968 		      crtc->enabled_power_domains.mask.bits,  in intel_modeset_get_crtc_power_domains()
1970 	bitmap_andnot(old_domains->bits,  in intel_modeset_get_crtc_power_domains()
1971 		      crtc->enabled_power_domains.mask.bits,  in intel_modeset_get_crtc_power_domains()
1977 					       &crtc->enabled_power_domains,  in intel_modeset_get_crtc_power_domains()
1987 					    &crtc->enabled_power_domains,  in intel_modeset_put_crtc_power_domains()
1993 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in i9xx_configure_cpu_transcoder()
1994 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in i9xx_configure_cpu_transcoder()
1998 					       &crtc_state->dp_m_n);  in i9xx_configure_cpu_transcoder()
2000 					       &crtc_state->dp_m2_n2);  in i9xx_configure_cpu_transcoder()
2014 	enum pipe pipe = crtc->pipe;  in valleyview_crtc_enable()
2016 	if (drm_WARN_ON(display->drm, crtc->active))  in valleyview_crtc_enable()
2025 	if (display->platform.cherryview && pipe == PIPE_B) {  in valleyview_crtc_enable()
2031 	crtc->active = true;  in valleyview_crtc_enable()
2037 	if (display->platform.cherryview)  in valleyview_crtc_enable()
2062 	enum pipe pipe = crtc->pipe;  in i9xx_crtc_enable()
2064 	if (drm_WARN_ON(display->drm, crtc->active))  in i9xx_crtc_enable()
2071 	crtc->active = true;  in i9xx_crtc_enable()
2103 	enum pipe pipe = crtc->pipe;  in i9xx_crtc_disable()
2123 		if (display->platform.cherryview)  in i9xx_crtc_disable()
2125 		else if (display->platform.valleyview)  in i9xx_crtc_disable()
2136 	if (!display->funcs.wm->initial_watermarks)  in i9xx_crtc_disable()
2140 	if (display->platform.i830)  in i9xx_crtc_disable()
2158 		(crtc->pipe == PIPE_A || display->platform.i915g);  in intel_crtc_supports_double_wide()
2163 	u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;  in ilk_pipe_pixel_rate()
2167 	 * We only use IF-ID interlacing. If we ever use  in ilk_pipe_pixel_rate()
2168 	 * PF-ID we'll need to adjust the pixel_rate here.  in ilk_pipe_pixel_rate()
2171 	if (!crtc_state->pch_pfit.enabled)  in ilk_pipe_pixel_rate()
2175 		      drm_rect_width(&crtc_state->pipe_src) << 16,  in ilk_pipe_pixel_rate()
2176 		      drm_rect_height(&crtc_state->pipe_src) << 16);  in ilk_pipe_pixel_rate()
2178 	return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,  in ilk_pipe_pixel_rate()
2185 	mode->hdisplay = timings->crtc_hdisplay;  in intel_mode_from_crtc_timings()
2186 	mode->htotal = timings->crtc_htotal;  in intel_mode_from_crtc_timings()
2187 	mode->hsync_start = timings->crtc_hsync_start;  in intel_mode_from_crtc_timings()
2188 	mode->hsync_end = timings->crtc_hsync_end;  in intel_mode_from_crtc_timings()
2190 	mode->vdisplay = timings->crtc_vdisplay;  in intel_mode_from_crtc_timings()
2191 	mode->vtotal = timings->crtc_vtotal;  in intel_mode_from_crtc_timings()
2192 	mode->vsync_start = timings->crtc_vsync_start;  in intel_mode_from_crtc_timings()
2193 	mode->vsync_end = timings->crtc_vsync_end;  in intel_mode_from_crtc_timings()
2195 	mode->flags = timings->flags;  in intel_mode_from_crtc_timings()
2196 	mode->type = DRM_MODE_TYPE_DRIVER;  in intel_mode_from_crtc_timings()
2198 	mode->clock = timings->crtc_clock;  in intel_mode_from_crtc_timings()
2209 		crtc_state->pixel_rate =  in intel_crtc_compute_pixel_rate()
2210 			crtc_state->hw.pipe_mode.crtc_clock;  in intel_crtc_compute_pixel_rate()
2212 		crtc_state->pixel_rate =  in intel_crtc_compute_pixel_rate()
2224 	mode->crtc_clock /= num_pipes;  in intel_joiner_adjust_timings()
2225 	mode->crtc_hdisplay /= num_pipes;  in intel_joiner_adjust_timings()
2226 	mode->crtc_hblank_start /= num_pipes;  in intel_joiner_adjust_timings()
2227 	mode->crtc_hblank_end /= num_pipes;  in intel_joiner_adjust_timings()
2228 	mode->crtc_hsync_start /= num_pipes;  in intel_joiner_adjust_timings()
2229 	mode->crtc_hsync_end /= num_pipes;  in intel_joiner_adjust_timings()
2230 	mode->crtc_htotal /= num_pipes;  in intel_joiner_adjust_timings()
2236 	int overlap = crtc_state->splitter.pixel_overlap;  in intel_splitter_adjust_timings()
2237 	int n = crtc_state->splitter.link_count;  in intel_splitter_adjust_timings()
2239 	if (!crtc_state->splitter.enable)  in intel_splitter_adjust_timings()
2246 	 * h_full = (h_segment - pixel_overlap) * link_count  in intel_splitter_adjust_timings()
2248 	mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n;  in intel_splitter_adjust_timings()
2249 	mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n;  in intel_splitter_adjust_timings()
2250 	mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n;  in intel_splitter_adjust_timings()
2251 	mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n;  in intel_splitter_adjust_timings()
2252 	mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n;  in intel_splitter_adjust_timings()
2253 	mode->crtc_htotal = (mode->crtc_htotal - overlap) * n;  in intel_splitter_adjust_timings()
2254 	mode->crtc_clock *= n;  in intel_splitter_adjust_timings()
2259 	struct drm_display_mode *mode = &crtc_state->hw.mode;  in intel_crtc_readout_derived_state()
2260 	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;  in intel_crtc_readout_derived_state()
2261 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_crtc_readout_derived_state()
2269 	/* Expand MSO per-segment transcoder timings to full */  in intel_crtc_readout_derived_state()
2282 	mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *  in intel_crtc_readout_derived_state()
2284 	mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);  in intel_crtc_readout_derived_state()
2286 	/* Derive per-pipe timings in case joiner is used */  in intel_crtc_readout_derived_state()
2296 	encoder->get_config(encoder, crtc_state);  in intel_encoder_get_config()
2309 	width = drm_rect_width(&crtc_state->pipe_src);  in intel_joiner_compute_pipe_src()
2310 	height = drm_rect_height(&crtc_state->pipe_src);  in intel_joiner_compute_pipe_src()
2312 	drm_rect_init(&crtc_state->pipe_src, 0, 0,  in intel_joiner_compute_pipe_src()
2319 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_compute_pipe_src()
2325 	 * - DVO ganged mode  in intel_crtc_compute_pipe_src()
2326 	 * - LVDS dual channel mode  in intel_crtc_compute_pipe_src()
2327 	 * - Double wide pipe  in intel_crtc_compute_pipe_src()
2329 	if (drm_rect_width(&crtc_state->pipe_src) & 1) {  in intel_crtc_compute_pipe_src()
2330 		if (crtc_state->double_wide) {  in intel_crtc_compute_pipe_src()
2331 			drm_dbg_kms(display->drm,  in intel_crtc_compute_pipe_src()
2333 				    crtc->base.base.id, crtc->base.name);  in intel_crtc_compute_pipe_src()
2334 			return -EINVAL;  in intel_crtc_compute_pipe_src()
2339 			drm_dbg_kms(display->drm,  in intel_crtc_compute_pipe_src()
2341 				    crtc->base.base.id, crtc->base.name);  in intel_crtc_compute_pipe_src()
2342 			return -EINVAL;  in intel_crtc_compute_pipe_src()
2352 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_compute_pipe_mode()
2353 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_crtc_compute_pipe_mode()
2354 	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;  in intel_crtc_compute_pipe_mode()
2355 	int clock_limit = display->cdclk.max_dotclk_freq;  in intel_crtc_compute_pipe_mode()
2363 	/* Expand MSO per-segment transcoder timings to full */  in intel_crtc_compute_pipe_mode()
2366 	/* Derive per-pipe timings in case joiner is used */  in intel_crtc_compute_pipe_mode()
2371 		clock_limit = display->cdclk.max_cdclk_freq * 9 / 10;  in intel_crtc_compute_pipe_mode()
2378 		    pipe_mode->crtc_clock > clock_limit) {  in intel_crtc_compute_pipe_mode()
2379 			clock_limit = display->cdclk.max_dotclk_freq;  in intel_crtc_compute_pipe_mode()
2380 			crtc_state->double_wide = true;  in intel_crtc_compute_pipe_mode()
2384 	if (pipe_mode->crtc_clock > clock_limit) {  in intel_crtc_compute_pipe_mode()
2385 		drm_dbg_kms(display->drm,  in intel_crtc_compute_pipe_mode()
2387 			    crtc->base.base.id, crtc->base.name,  in intel_crtc_compute_pipe_mode()
2388 			    pipe_mode->crtc_clock, clock_limit,  in intel_crtc_compute_pipe_mode()
2389 			    str_yes_no(crtc_state->double_wide));  in intel_crtc_compute_pipe_mode()
2390 		return -EINVAL;  in intel_crtc_compute_pipe_mode()
2417 		&crtc_state->hw.adjusted_mode;  in intel_crtc_compute_set_context_latency()
2422 	max_vblank_delay = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start - 1;  in intel_crtc_compute_set_context_latency()
2425 		drm_dbg_kms(display->drm, "[CRTC:%d:%s] set context latency (%d) exceeds max (%d)\n",  in intel_crtc_compute_set_context_latency()
2426 			    crtc->base.base.id, crtc->base.name,  in intel_crtc_compute_set_context_latency()
2429 		return -EINVAL;  in intel_crtc_compute_set_context_latency()
2432 	crtc_state->set_context_latency = set_context_latency;  in intel_crtc_compute_set_context_latency()
2433 	adjusted_mode->crtc_vblank_start += set_context_latency;  in intel_crtc_compute_set_context_latency()
2463 	if (crtc_state->has_pch_encoder)  in intel_crtc_compute_config()
2511 	m_n->tu = 64;  in intel_link_compute_m_n()
2512 	compute_m_n(&m_n->data_m, &m_n->data_n,  in intel_link_compute_m_n()
2516 	compute_m_n(&m_n->link_m, &m_n->link_n,  in intel_link_compute_m_n()
2534 		if (display->vbt.lvds_use_ssc != bios_lvds_use_ssc) {  in intel_panel_sanitize_ssc()
2535 			drm_dbg_kms(display->drm,  in intel_panel_sanitize_ssc()
2538 				    str_enabled_disabled(display->vbt.lvds_use_ssc));  in intel_panel_sanitize_ssc()
2539 			display->vbt.lvds_use_ssc = bios_lvds_use_ssc;  in intel_panel_sanitize_ssc()
2548 	m_n->tu = 1;  in intel_zero_m_n()
2556 	intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);  in intel_set_m_n()
2557 	intel_de_write(display, data_n_reg, m_n->data_n);  in intel_set_m_n()
2558 	intel_de_write(display, link_m_reg, m_n->link_m);  in intel_set_m_n()
2563 	intel_de_write(display, link_n_reg, m_n->link_n);  in intel_set_m_n()
2569 	if (display->platform.haswell)  in intel_cpu_transcoder_has_m2_n2()
2572 	return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview;  in intel_cpu_transcoder_has_m2_n2()
2580 	enum pipe pipe = crtc->pipe;  in intel_cpu_transcoder_set_m1_n1()
2614 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in transcoder_has_vrr()
2622 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_set_transcoder_timings()
2623 	enum pipe pipe = crtc->pipe;  in intel_set_transcoder_timings()
2624 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_set_transcoder_timings()
2625 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_set_transcoder_timings()
2629 	drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));  in intel_set_transcoder_timings()
2633 	crtc_vdisplay = adjusted_mode->crtc_vdisplay;  in intel_set_transcoder_timings()
2634 	crtc_vtotal = adjusted_mode->crtc_vtotal;  in intel_set_transcoder_timings()
2635 	crtc_vblank_start = adjusted_mode->crtc_vblank_start;  in intel_set_transcoder_timings()
2636 	crtc_vblank_end = adjusted_mode->crtc_vblank_end;  in intel_set_transcoder_timings()
2638 	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {  in intel_set_transcoder_timings()
2640 		crtc_vtotal -= 1;  in intel_set_transcoder_timings()
2641 		crtc_vblank_end -= 1;  in intel_set_transcoder_timings()
2644 			vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;  in intel_set_transcoder_timings()
2646 			vsyncshift = adjusted_mode->crtc_hsync_start -  in intel_set_transcoder_timings()
2647 				adjusted_mode->crtc_htotal / 2;  in intel_set_transcoder_timings()
2649 			vsyncshift += adjusted_mode->crtc_htotal;  in intel_set_transcoder_timings()
2659 			       crtc_state->set_context_latency);  in intel_set_transcoder_timings()
2667 		/* VBLANK_START - VACTIVE defines SCL on TGL */  in intel_set_transcoder_timings()
2668 		crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency;  in intel_set_transcoder_timings()
2677 		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |  in intel_set_transcoder_timings()
2678 		       HTOTAL(adjusted_mode->crtc_htotal - 1));  in intel_set_transcoder_timings()
2680 		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |  in intel_set_transcoder_timings()
2681 		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));  in intel_set_transcoder_timings()
2683 		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |  in intel_set_transcoder_timings()
2684 		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));  in intel_set_transcoder_timings()
2696 		       VACTIVE(crtc_vdisplay - 1) |  in intel_set_transcoder_timings()
2697 		       VTOTAL(crtc_vtotal - 1));  in intel_set_transcoder_timings()
2699 		       VBLANK_START(crtc_vblank_start - 1) |  in intel_set_transcoder_timings()
2700 		       VBLANK_END(crtc_vblank_end - 1));  in intel_set_transcoder_timings()
2702 		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |  in intel_set_transcoder_timings()
2703 		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));  in intel_set_transcoder_timings()
2709 	if (display->platform.haswell && cpu_transcoder == TRANSCODER_EDP &&  in intel_set_transcoder_timings()
2712 			       VACTIVE(crtc_vdisplay - 1) |  in intel_set_transcoder_timings()
2713 			       VTOTAL(crtc_vtotal - 1));  in intel_set_transcoder_timings()
2725 			       crtc_state->min_hblank);  in intel_set_transcoder_timings()
2732 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_set_transcoder_timings_lrr()
2733 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_set_transcoder_timings_lrr()
2736 	drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));  in intel_set_transcoder_timings_lrr()
2738 	crtc_vdisplay = adjusted_mode->crtc_vdisplay;  in intel_set_transcoder_timings_lrr()
2739 	crtc_vtotal = adjusted_mode->crtc_vtotal;  in intel_set_transcoder_timings_lrr()
2740 	crtc_vblank_start = adjusted_mode->crtc_vblank_start;  in intel_set_transcoder_timings_lrr()
2741 	crtc_vblank_end = adjusted_mode->crtc_vblank_end;  in intel_set_transcoder_timings_lrr()
2743 	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {  in intel_set_transcoder_timings_lrr()
2745 		crtc_vtotal -= 1;  in intel_set_transcoder_timings_lrr()
2746 		crtc_vblank_end -= 1;  in intel_set_transcoder_timings_lrr()
2752 			       crtc_state->set_context_latency);  in intel_set_transcoder_timings_lrr()
2760 		/* VBLANK_START - VACTIVE defines SCL on TGL */  in intel_set_transcoder_timings_lrr()
2761 		crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency;  in intel_set_transcoder_timings_lrr()
2769 		       VBLANK_START(crtc_vblank_start - 1) |  in intel_set_transcoder_timings_lrr()
2770 		       VBLANK_END(crtc_vblank_end - 1));  in intel_set_transcoder_timings_lrr()
2785 		       VACTIVE(crtc_vdisplay - 1) |  in intel_set_transcoder_timings_lrr()
2786 		       VTOTAL(crtc_vtotal - 1));  in intel_set_transcoder_timings_lrr()
2795 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_set_pipe_src_size()
2796 	int width = drm_rect_width(&crtc_state->pipe_src);  in intel_set_pipe_src_size()
2797 	int height = drm_rect_height(&crtc_state->pipe_src);  in intel_set_pipe_src_size()
2798 	enum pipe pipe = crtc->pipe;  in intel_set_pipe_src_size()
2804 		       PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));  in intel_set_pipe_src_size()
2810 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_pipe_is_interlaced()
2816 	    display->platform.broadwell || display->platform.haswell)  in intel_pipe_is_interlaced()
2828 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;  in intel_get_transcoder_timings()
2829 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;  in intel_get_transcoder_timings()
2833 	adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2834 	adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2839 		adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2840 		adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2844 	adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2845 	adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2848 	adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2849 	adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2855 		adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2856 		adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2859 	adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2860 	adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2863 		adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;  in intel_get_transcoder_timings()
2864 		adjusted_mode->crtc_vtotal += 1;  in intel_get_transcoder_timings()
2865 		adjusted_mode->crtc_vblank_end += 1;  in intel_get_transcoder_timings()
2869 		pipe_config->set_context_latency =  in intel_get_transcoder_timings()
2872 		adjusted_mode->crtc_vblank_start =  in intel_get_transcoder_timings()
2873 			adjusted_mode->crtc_vdisplay +  in intel_get_transcoder_timings()
2874 			pipe_config->set_context_latency;  in intel_get_transcoder_timings()
2881 		 * Vblank start - Vactive.  in intel_get_transcoder_timings()
2883 		pipe_config->set_context_latency =  in intel_get_transcoder_timings()
2884 			adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;  in intel_get_transcoder_timings()
2888 		pipe_config->min_hblank = intel_de_read(display,  in intel_get_transcoder_timings()
2894 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_joiner_adjust_pipe_src()
2896 	enum pipe primary_pipe, pipe = crtc->pipe;  in intel_joiner_adjust_pipe_src()
2903 	width = drm_rect_width(&crtc_state->pipe_src);  in intel_joiner_adjust_pipe_src()
2905 	drm_rect_translate_to(&crtc_state->pipe_src,  in intel_joiner_adjust_pipe_src()
2906 			      (pipe - primary_pipe) * width, 0);  in intel_joiner_adjust_pipe_src()
2915 	tmp = intel_de_read(display, PIPESRC(display, crtc->pipe));  in intel_get_pipe_src_size()
2917 	drm_rect_init(&pipe_config->pipe_src, 0, 0,  in intel_get_pipe_src_size()
2927 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in i9xx_set_pipeconf()
2931 	 * - We keep both pipes enabled on 830  in i9xx_set_pipeconf()
2932 	 * - During modeset the pipe is still disabled and must remain so  in i9xx_set_pipeconf()
2933 	 * - During fastset the pipe is already enabled and must remain so  in i9xx_set_pipeconf()
2935 	if (display->platform.i830 || !intel_crtc_needs_modeset(crtc_state))  in i9xx_set_pipeconf()
2938 	if (crtc_state->double_wide)  in i9xx_set_pipeconf()
2942 	if (display->platform.g4x || display->platform.valleyview ||  in i9xx_set_pipeconf()
2943 	    display->platform.cherryview) {  in i9xx_set_pipeconf()
2945 		if (crtc_state->dither && crtc_state->pipe_bpp != 30)  in i9xx_set_pipeconf()
2949 		switch (crtc_state->pipe_bpp) {  in i9xx_set_pipeconf()
2952 			MISSING_CASE(crtc_state->pipe_bpp);  in i9xx_set_pipeconf()
2966 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {  in i9xx_set_pipeconf()
2976 	if ((display->platform.valleyview || display->platform.cherryview) &&  in i9xx_set_pipeconf()
2977 	    crtc_state->limited_color_range)  in i9xx_set_pipeconf()
2980 	val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);  in i9xx_set_pipeconf()
2982 	if (crtc_state->wgc_enable)  in i9xx_set_pipeconf()
2985 	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);  in i9xx_set_pipeconf()
2997 	tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));  in bdw_get_pipe_misc_output_format()
3006 			drm_WARN_ON(display->drm,  in bdw_get_pipe_misc_output_format()
3022 	enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe;  in i9xx_get_pipe_config()
3027 	power_domain = POWER_DOMAIN_PIPE(crtc->pipe);  in i9xx_get_pipe_config()
3036 	pipe_config->cpu_transcoder = cpu_transcoder;  in i9xx_get_pipe_config()
3038 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;  in i9xx_get_pipe_config()
3039 	pipe_config->sink_format = pipe_config->output_format;  in i9xx_get_pipe_config()
3041 	if (display->platform.g4x || display->platform.valleyview ||  in i9xx_get_pipe_config()
3042 	    display->platform.cherryview) {  in i9xx_get_pipe_config()
3045 			pipe_config->pipe_bpp = 18;  in i9xx_get_pipe_config()
3048 			pipe_config->pipe_bpp = 24;  in i9xx_get_pipe_config()
3051 			pipe_config->pipe_bpp = 30;  in i9xx_get_pipe_config()
3059 	if ((display->platform.valleyview || display->platform.cherryview) &&  in i9xx_get_pipe_config()
3061 		pipe_config->limited_color_range = true;  in i9xx_get_pipe_config()
3063 	pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp);  in i9xx_get_pipe_config()
3065 	pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;  in i9xx_get_pipe_config()
3067 	if ((display->platform.valleyview || display->platform.cherryview) &&  in i9xx_get_pipe_config()
3069 		pipe_config->wgc_enable = true;  in i9xx_get_pipe_config()
3074 		pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE;  in i9xx_get_pipe_config()
3081 	i9xx_dpll_get_hw_state(crtc, &pipe_config->dpll_hw_state);  in i9xx_get_pipe_config()
3084 		tmp = pipe_config->dpll_hw_state.i9xx.dpll_md;  in i9xx_get_pipe_config()
3085 		pipe_config->pixel_multiplier =  in i9xx_get_pipe_config()
3088 	} else if (display->platform.i945g || display->platform.i945gm ||  in i9xx_get_pipe_config()
3089 		   display->platform.g33 || display->platform.pineview) {  in i9xx_get_pipe_config()
3090 		tmp = pipe_config->dpll_hw_state.i9xx.dpll;  in i9xx_get_pipe_config()
3091 		pipe_config->pixel_multiplier =  in i9xx_get_pipe_config()
3096 		 * port and will be fixed up in the encoder->get_config  in i9xx_get_pipe_config()
3098 		pipe_config->pixel_multiplier = 1;  in i9xx_get_pipe_config()
3101 	if (display->platform.cherryview)  in i9xx_get_pipe_config()
3103 	else if (display->platform.valleyview)  in i9xx_get_pipe_config()
3113 	pipe_config->hw.adjusted_mode.crtc_clock =  in i9xx_get_pipe_config()
3114 		pipe_config->port_clock / pipe_config->pixel_multiplier;  in i9xx_get_pipe_config()
3127 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in ilk_set_pipeconf()
3131 	 * - During modeset the pipe is still disabled and must remain so  in ilk_set_pipeconf()
3132 	 * - During fastset the pipe is already enabled and must remain so  in ilk_set_pipeconf()
3137 	switch (crtc_state->pipe_bpp) {  in ilk_set_pipeconf()
3140 		MISSING_CASE(crtc_state->pipe_bpp);  in ilk_set_pipeconf()
3156 	if (crtc_state->dither)  in ilk_set_pipeconf()
3159 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)  in ilk_set_pipeconf()
3168 	drm_WARN_ON(display->drm, crtc_state->limited_color_range &&  in ilk_set_pipeconf()
3169 		    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);  in ilk_set_pipeconf()
3171 	if (crtc_state->limited_color_range &&  in ilk_set_pipeconf()
3175 	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)  in ilk_set_pipeconf()
3178 	val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);  in ilk_set_pipeconf()
3180 	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);  in ilk_set_pipeconf()
3181 	val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);  in ilk_set_pipeconf()
3190 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in hsw_set_transconf()
3194 	 * - During modeset the pipe is still disabled and must remain so  in hsw_set_transconf()
3195 	 * - During fastset the pipe is already enabled and must remain so  in hsw_set_transconf()
3200 	if (display->platform.haswell && crtc_state->dither)  in hsw_set_transconf()
3204 		if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)  in hsw_set_transconf()
3210 	if (display->platform.haswell &&  in hsw_set_transconf()
3211 	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)  in hsw_set_transconf()
3222 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in bdw_set_pipe_misc()
3225 	switch (crtc_state->pipe_bpp) {  in bdw_set_pipe_misc()
3241 		MISSING_CASE(crtc_state->pipe_bpp);  in bdw_set_pipe_misc()
3245 	if (crtc_state->dither)  in bdw_set_pipe_misc()
3248 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||  in bdw_set_pipe_misc()
3249 	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)  in bdw_set_pipe_misc()
3252 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)  in bdw_set_pipe_misc()
3263 	if (display->platform.broadwell)  in bdw_set_pipe_misc()
3266 	intel_de_write_dsb(display, dsb, PIPE_MISC(crtc->pipe), val);  in bdw_set_pipe_misc()
3274 	tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));  in bdw_get_pipe_misc_bpp()
3306 	 * Account for spread spectrum to avoid  in ilk_get_lanes_required()
3307 	 * oversubscribing the link. Max center spread  in ilk_get_lanes_required()
3319 	m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK;  in intel_get_m_n()
3320 	m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK;  in intel_get_m_n()
3321 	m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK;  in intel_get_m_n()
3322 	m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK;  in intel_get_m_n()
3323 	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;  in intel_get_m_n()
3331 	enum pipe pipe = crtc->pipe;  in intel_cpu_transcoder_get_m1_n1()
3366 	enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe;  in ilk_get_pipe_config()
3371 	power_domain = POWER_DOMAIN_PIPE(crtc->pipe);  in ilk_get_pipe_config()
3380 	pipe_config->cpu_transcoder = cpu_transcoder;  in ilk_get_pipe_config()
3384 		pipe_config->pipe_bpp = 18;  in ilk_get_pipe_config()
3387 		pipe_config->pipe_bpp = 24;  in ilk_get_pipe_config()
3390 		pipe_config->pipe_bpp = 30;  in ilk_get_pipe_config()
3393 		pipe_config->pipe_bpp = 36;  in ilk_get_pipe_config()
3400 		pipe_config->limited_color_range = true;  in ilk_get_pipe_config()
3405 		pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;  in ilk_get_pipe_config()
3408 		pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;  in ilk_get_pipe_config()
3412 	pipe_config->sink_format = pipe_config->output_format;  in ilk_get_pipe_config()
3414 	pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp);  in ilk_get_pipe_config()
3416 	pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;  in ilk_get_pipe_config()
3418 	pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);  in ilk_get_pipe_config()
3422 	pipe_config->pixel_multiplier = 1;  in ilk_get_pipe_config()
3450 	return pipes & DISPLAY_RUNTIME_INFO(display)->pipe_mask;  in joiner_pipes()
3480 	for_each_intel_crtc_in_pipe_mask(display->drm, crtc,  in enabled_uncompressed_joiner_pipes()
3483 		enum pipe pipe = crtc->pipe;  in enabled_uncompressed_joiner_pipes()
3509 	for_each_intel_crtc_in_pipe_mask(display->drm, crtc,  in enabled_bigjoiner_pipes()
3512 		enum pipe pipe = crtc->pipe;  in enabled_bigjoiner_pipes()
3554 	return primary_pipes ? BIT(fls(primary_pipes) - 1) : 0;  in get_joiner_primary_pipe()
3579 	for_each_intel_crtc_in_pipe_mask(display->drm, crtc,  in enabled_ultrajoiner_pipes()
3582 		enum pipe pipe = crtc->pipe;  in enabled_ultrajoiner_pipes()
3618 	drm_WARN_ON(display->drm,  in enabled_joiner_pipes()
3625 	drm_WARN_ON(display->drm, (primary_ultrajoiner_pipes & secondary_ultrajoiner_pipes) != 0);  in enabled_joiner_pipes()
3630 	drm_WARN_ON(display->drm,  in enabled_joiner_pipes()
3636 	drm_WARN_ON(display->drm,  in enabled_joiner_pipes()
3644 	drm_WARN(display->drm, (ultrajoiner_pipes & bigjoiner_pipes) != ultrajoiner_pipes,  in enabled_joiner_pipes()
3648 	drm_WARN(display->drm, secondary_ultrajoiner_pipes !=  in enabled_joiner_pipes()
3654 	drm_WARN(display->drm, (uncompressed_joiner_pipes & bigjoiner_pipes) != 0,  in enabled_joiner_pipes()
3658 	drm_WARN(display->drm, secondary_bigjoiner_pipes !=  in enabled_joiner_pipes()
3664 	drm_WARN(display->drm, secondary_uncompressed_joiner_pipes !=  in enabled_joiner_pipes()
3678 		drm_WARN(display->drm,  in enabled_joiner_pipes()
3693 		drm_WARN(display->drm,  in enabled_joiner_pipes()
3708 		drm_WARN(display->drm,  in enabled_joiner_pipes()
3758 			drm_WARN(display->drm, 1,  in hsw_enabled_transcoders()
3777 		if (trans_pipe == crtc->pipe)  in hsw_enabled_transcoders()
3782 	cpu_transcoder = (enum transcoder) crtc->pipe;  in hsw_enabled_transcoders()
3786 	/* joiner secondary -> consider the primary pipe's transcoder as well */  in hsw_enabled_transcoders()
3787 	enabled_joiner_pipes(display, crtc->pipe, &primary_pipe, &secondary_pipes);  in hsw_enabled_transcoders()
3788 	if (secondary_pipes & BIT(crtc->pipe)) {  in hsw_enabled_transcoders()
3789 		cpu_transcoder = (enum transcoder)ffs(primary_pipe) - 1;  in hsw_enabled_transcoders()
3819 	drm_WARN_ON(display->drm,  in assert_enabled_transcoders()
3825 	drm_WARN_ON(display->drm,  in assert_enabled_transcoders()
3849 	pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1;  in hsw_get_transcoder_state()
3852 						       POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))  in hsw_get_transcoder_state()
3855 	if (hsw_panel_transcoders(display) & BIT(pipe_config->cpu_transcoder)) {  in hsw_get_transcoder_state()
3857 				    TRANS_DDI_FUNC_CTL(display, pipe_config->cpu_transcoder));  in hsw_get_transcoder_state()
3860 			pipe_config->pch_pfit.force_thru = true;  in hsw_get_transcoder_state()
3864 			    TRANSCONF(display, pipe_config->cpu_transcoder));  in hsw_get_transcoder_state()
3904 		if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))  in bxt_get_dsi_transcoder_state()
3907 		pipe_config->cpu_transcoder = cpu_transcoder;  in bxt_get_dsi_transcoder_state()
3911 	return transcoder_is_dsi(pipe_config->cpu_transcoder);  in bxt_get_dsi_transcoder_state()
3917 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_joiner_get_config()
3919 	enum pipe pipe = crtc->pipe;  in intel_joiner_get_config()
3926 	crtc_state->joiner_pipes = primary_pipe | secondary_pipes;  in intel_joiner_get_config()
3936 	if (!intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains,  in hsw_get_pipe_config()
3937 						       POWER_DOMAIN_PIPE(crtc->pipe)))  in hsw_get_pipe_config()
3940 	active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains);  in hsw_get_pipe_config()
3942 	if ((display->platform.geminilake || display->platform.broxton) &&  in hsw_get_pipe_config()
3943 	    bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) {  in hsw_get_pipe_config()
3944 		drm_WARN_ON(display->drm, active);  in hsw_get_pipe_config()
3955 	if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {  in hsw_get_pipe_config()
3956 		tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));  in hsw_get_pipe_config()
3958 		pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;  in hsw_get_pipe_config()
3961 		pipe_config->framestart_delay = 1;  in hsw_get_pipe_config()
3968 	if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||  in hsw_get_pipe_config()
3977 	if (display->platform.haswell) {  in hsw_get_pipe_config()
3979 					TRANSCONF(display, pipe_config->cpu_transcoder));  in hsw_get_pipe_config()
3982 			pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;  in hsw_get_pipe_config()
3984 			pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;  in hsw_get_pipe_config()
3986 		pipe_config->output_format =  in hsw_get_pipe_config()
3990 	pipe_config->sink_format = pipe_config->output_format;  in hsw_get_pipe_config()
3994 	tmp = intel_de_read(display, WM_LINETIME(crtc->pipe));  in hsw_get_pipe_config()
3995 	pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);  in hsw_get_pipe_config()
3996 	if (display->platform.broadwell || display->platform.haswell)  in hsw_get_pipe_config()
3997 		pipe_config->ips_linetime =  in hsw_get_pipe_config()
4000 	if (intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains,  in hsw_get_pipe_config()
4001 						      POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {  in hsw_get_pipe_config()
4010 	if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&  in hsw_get_pipe_config()
4011 	    !transcoder_is_dsi(pipe_config->cpu_transcoder)) {  in hsw_get_pipe_config()
4012 		pipe_config->pixel_multiplier =  in hsw_get_pipe_config()
4014 				      TRANS_MULT(display, pipe_config->cpu_transcoder)) + 1;  in hsw_get_pipe_config()
4016 		pipe_config->pixel_multiplier = 1;  in hsw_get_pipe_config()
4020 	intel_display_power_put_all_in_set(display, &crtc->hw_readout_power_domains);  in hsw_get_pipe_config()
4028 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_get_pipe_config()
4030 	if (!display->funcs.display->get_pipe_config(crtc, crtc_state))  in intel_crtc_get_pipe_config()
4033 	crtc_state->hw.active = true;  in intel_crtc_get_pipe_config()
4044 	 * The calculation for the data clock -> pixel clock is:  in intel_dotclock_calculate()
4049 	 * and for link freq (10kbs units) -> pixel clock it is:  in intel_dotclock_calculate()
4056 	if (!m_n->link_n)  in intel_dotclock_calculate()
4059 	return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq * 10),  in intel_dotclock_calculate()
4060 				m_n->link_n * intel_dp_link_symbol_size(link_freq));  in intel_dotclock_calculate()
4068 		dotclock = intel_dotclock_calculate(pipe_config->port_clock,  in intel_crtc_dotclock()
4069 						    &pipe_config->dp_m_n);  in intel_crtc_dotclock()
4070 	else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)  in intel_crtc_dotclock()
4071 		dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24,  in intel_crtc_dotclock()
4072 					     pipe_config->pipe_bpp);  in intel_crtc_dotclock()
4074 		dotclock = pipe_config->port_clock;  in intel_crtc_dotclock()
4076 	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&  in intel_crtc_dotclock()
4080 	if (pipe_config->pixel_multiplier)  in intel_crtc_dotclock()
4081 		dotclock /= pipe_config->pixel_multiplier;  in intel_crtc_dotclock()
4096 	if (!encoder->get_hw_state(encoder, &pipe))  in intel_encoder_current_mode()
4112 		intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);  in intel_encoder_current_mode()
4119 	intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);  in intel_encoder_current_mode()
4121 	intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);  in intel_encoder_current_mode()
4130 	return a == b || (a->cloneable & BIT(b->type) &&  in encoders_cloneable()
4131 			  b->cloneable & BIT(a->type));  in encoders_cloneable()
4143 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in check_single_encoder_cloning()
4144 		if (connector_state->crtc != &crtc->base)  in check_single_encoder_cloning()
4148 			to_intel_encoder(connector_state->best_encoder);  in check_single_encoder_cloning()
4159 		&crtc_state->hw.pipe_mode;  in hsw_linetime_wm()
4162 	if (!crtc_state->hw.enable)  in hsw_linetime_wm()
4165 	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,  in hsw_linetime_wm()
4166 					pipe_mode->crtc_clock);  in hsw_linetime_wm()
4175 		&crtc_state->hw.pipe_mode;  in hsw_ips_linetime_wm()
4178 	if (!crtc_state->hw.enable)  in hsw_ips_linetime_wm()
4181 	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,  in hsw_ips_linetime_wm()
4191 		&crtc_state->hw.pipe_mode;  in skl_linetime_wm()
4194 	if (!crtc_state->hw.enable)  in skl_linetime_wm()
4197 	linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,  in skl_linetime_wm()
4198 				   crtc_state->pixel_rate);  in skl_linetime_wm()
4201 	if ((display->platform.geminilake || display->platform.broxton) &&  in skl_linetime_wm()
4217 		crtc_state->linetime = skl_linetime_wm(crtc_state);  in hsw_compute_linetime_wm()
4219 		crtc_state->linetime = hsw_linetime_wm(crtc_state);  in hsw_compute_linetime_wm()
4228 	crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,  in hsw_compute_linetime_wm()
4242 	if (DISPLAY_VER(display) < 5 && !display->platform.g4x &&  in intel_crtc_atomic_check()
4244 	    !crtc_state->hw.active)  in intel_crtc_atomic_check()
4245 		crtc_state->update_wm_post = true;  in intel_crtc_atomic_check()
4259 		drm_dbg_kms(display->drm,  in intel_crtc_atomic_check()
4261 			    crtc->base.base.id, crtc->base.name);  in intel_crtc_atomic_check()
4290 	    display->platform.broadwell || display->platform.haswell) {  in intel_crtc_atomic_check()
4309 	struct drm_connector *connector = conn_state->connector;  in compute_sink_pipe_bpp()
4310 	const struct drm_display_info *info = &connector->display_info;  in compute_sink_pipe_bpp()
4313 	switch (conn_state->max_bpc) {  in compute_sink_pipe_bpp()
4327 		MISSING_CASE(conn_state->max_bpc);  in compute_sink_pipe_bpp()
4328 		return -EINVAL;  in compute_sink_pipe_bpp()
4331 	if (bpp < crtc_state->pipe_bpp) {  in compute_sink_pipe_bpp()
4332 		drm_dbg_kms(display->drm,  in compute_sink_pipe_bpp()
4335 			    connector->base.id, connector->name,  in compute_sink_pipe_bpp()
4336 			    bpp, 3 * info->bpc,  in compute_sink_pipe_bpp()
4337 			    3 * conn_state->max_requested_bpc,  in compute_sink_pipe_bpp()
4338 			    crtc_state->pipe_bpp);  in compute_sink_pipe_bpp()
4340 		crtc_state->pipe_bpp = bpp;  in compute_sink_pipe_bpp()
4353 	if (display->platform.g4x || display->platform.valleyview ||  in intel_display_max_pipe_bpp()
4354 	    display->platform.cherryview)  in intel_display_max_pipe_bpp()
4373 	crtc_state->pipe_bpp = intel_display_max_pipe_bpp(display);  in compute_baseline_pipe_bpp()
4376 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in compute_baseline_pipe_bpp()
4379 		if (connector_state->crtc != &crtc->base)  in compute_baseline_pipe_bpp()
4400 	 * We're going to peek into connector->state,  in check_digital_port_conflicts()
4403 	drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex);  in check_digital_port_conflicts()
4410 	drm_connector_list_iter_begin(display->drm, &conn_iter);  in check_digital_port_conflicts()
4416 			drm_atomic_get_new_connector_state(&state->base,  in check_digital_port_conflicts()
4419 			connector_state = connector->state;  in check_digital_port_conflicts()
4421 		if (!connector_state->best_encoder)  in check_digital_port_conflicts()
4424 		encoder = to_intel_encoder(connector_state->best_encoder);  in check_digital_port_conflicts()
4426 		drm_WARN_ON(display->drm, !connector_state->crtc);  in check_digital_port_conflicts()
4428 		switch (encoder->type) {  in check_digital_port_conflicts()
4430 			if (drm_WARN_ON(display->drm, !HAS_DDI(display)))  in check_digital_port_conflicts()
4437 			if (used_ports & BIT(encoder->port))  in check_digital_port_conflicts()
4440 			used_ports |= BIT(encoder->port);  in check_digital_port_conflicts()
4444 				1 << encoder->port;  in check_digital_port_conflicts()
4468 	drm_property_replace_blob(&crtc_state->hw.degamma_lut,  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4469 				  crtc_state->uapi.degamma_lut);  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4470 	drm_property_replace_blob(&crtc_state->hw.gamma_lut,  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4471 				  crtc_state->uapi.gamma_lut);  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4472 	drm_property_replace_blob(&crtc_state->hw.ctm,  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4473 				  crtc_state->uapi.ctm);  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4485 	crtc_state->hw.enable = crtc_state->uapi.enable;  in intel_crtc_copy_uapi_to_hw_state_modeset()
4486 	crtc_state->hw.active = crtc_state->uapi.active;  in intel_crtc_copy_uapi_to_hw_state_modeset()
4487 	drm_mode_copy(&crtc_state->hw.mode,  in intel_crtc_copy_uapi_to_hw_state_modeset()
4488 		      &crtc_state->uapi.mode);  in intel_crtc_copy_uapi_to_hw_state_modeset()
4489 	drm_mode_copy(&crtc_state->hw.adjusted_mode,  in intel_crtc_copy_uapi_to_hw_state_modeset()
4490 		      &crtc_state->uapi.adjusted_mode);  in intel_crtc_copy_uapi_to_hw_state_modeset()
4491 	crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;  in intel_crtc_copy_uapi_to_hw_state_modeset()
4506 	drm_property_replace_blob(&secondary_crtc_state->hw.degamma_lut,  in copy_joiner_crtc_state_nomodeset()
4507 				  primary_crtc_state->hw.degamma_lut);  in copy_joiner_crtc_state_nomodeset()
4508 	drm_property_replace_blob(&secondary_crtc_state->hw.gamma_lut,  in copy_joiner_crtc_state_nomodeset()
4509 				  primary_crtc_state->hw.gamma_lut);  in copy_joiner_crtc_state_nomodeset()
4510 	drm_property_replace_blob(&secondary_crtc_state->hw.ctm,  in copy_joiner_crtc_state_nomodeset()
4511 				  primary_crtc_state->hw.ctm);  in copy_joiner_crtc_state_nomodeset()
4513 	secondary_crtc_state->uapi.color_mgmt_changed = primary_crtc_state->uapi.color_mgmt_changed;  in copy_joiner_crtc_state_nomodeset()
4527 	WARN_ON(primary_crtc_state->joiner_pipes !=  in copy_joiner_crtc_state_modeset()
4528 		secondary_crtc_state->joiner_pipes);  in copy_joiner_crtc_state_modeset()
4532 		return -ENOMEM;  in copy_joiner_crtc_state_modeset()
4535 	saved_state->uapi = secondary_crtc_state->uapi;  in copy_joiner_crtc_state_modeset()
4536 	saved_state->scaler_state = secondary_crtc_state->scaler_state;  in copy_joiner_crtc_state_modeset()
4537 	saved_state->intel_dpll = secondary_crtc_state->intel_dpll;  in copy_joiner_crtc_state_modeset()
4538 	saved_state->crc_enabled = secondary_crtc_state->crc_enabled;  in copy_joiner_crtc_state_modeset()
4541 	if (secondary_crtc_state->dp_tunnel_ref.tunnel)  in copy_joiner_crtc_state_modeset()
4542 		drm_dp_tunnel_ref_put(&secondary_crtc_state->dp_tunnel_ref);  in copy_joiner_crtc_state_modeset()
4546 	/* Re-init hw state */  in copy_joiner_crtc_state_modeset()
4547 	memset(&secondary_crtc_state->hw, 0, sizeof(secondary_crtc_state->hw));  in copy_joiner_crtc_state_modeset()
4548 	secondary_crtc_state->hw.enable = primary_crtc_state->hw.enable;  in copy_joiner_crtc_state_modeset()
4549 	secondary_crtc_state->hw.active = primary_crtc_state->hw.active;  in copy_joiner_crtc_state_modeset()
4550 	drm_mode_copy(&secondary_crtc_state->hw.mode,  in copy_joiner_crtc_state_modeset()
4551 		      &primary_crtc_state->hw.mode);  in copy_joiner_crtc_state_modeset()
4552 	drm_mode_copy(&secondary_crtc_state->hw.pipe_mode,  in copy_joiner_crtc_state_modeset()
4553 		      &primary_crtc_state->hw.pipe_mode);  in copy_joiner_crtc_state_modeset()
4554 	drm_mode_copy(&secondary_crtc_state->hw.adjusted_mode,  in copy_joiner_crtc_state_modeset()
4555 		      &primary_crtc_state->hw.adjusted_mode);  in copy_joiner_crtc_state_modeset()
4556 	secondary_crtc_state->hw.scaling_filter = primary_crtc_state->hw.scaling_filter;  in copy_joiner_crtc_state_modeset()
4558 	if (primary_crtc_state->dp_tunnel_ref.tunnel)  in copy_joiner_crtc_state_modeset()
4559 		drm_dp_tunnel_ref_get(primary_crtc_state->dp_tunnel_ref.tunnel,  in copy_joiner_crtc_state_modeset()
4560 				      &secondary_crtc_state->dp_tunnel_ref);  in copy_joiner_crtc_state_modeset()
4564 	secondary_crtc_state->uapi.mode_changed = primary_crtc_state->uapi.mode_changed;  in copy_joiner_crtc_state_modeset()
4565 	secondary_crtc_state->uapi.connectors_changed = primary_crtc_state->uapi.connectors_changed;  in copy_joiner_crtc_state_modeset()
4566 	secondary_crtc_state->uapi.active_changed = primary_crtc_state->uapi.active_changed;  in copy_joiner_crtc_state_modeset()
4568 	WARN_ON(primary_crtc_state->joiner_pipes !=  in copy_joiner_crtc_state_modeset()
4569 		secondary_crtc_state->joiner_pipes);  in copy_joiner_crtc_state_modeset()
4585 		return -ENOMEM;  in intel_crtc_prepare_cleared_state()
4587 	/* free the old crtc_state->hw members */  in intel_crtc_prepare_cleared_state()
4597 	saved_state->uapi = crtc_state->uapi;  in intel_crtc_prepare_cleared_state()
4598 	saved_state->inherited = crtc_state->inherited;  in intel_crtc_prepare_cleared_state()
4599 	saved_state->scaler_state = crtc_state->scaler_state;  in intel_crtc_prepare_cleared_state()
4600 	saved_state->intel_dpll = crtc_state->intel_dpll;  in intel_crtc_prepare_cleared_state()
4601 	saved_state->dpll_hw_state = crtc_state->dpll_hw_state;  in intel_crtc_prepare_cleared_state()
4602 	memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,  in intel_crtc_prepare_cleared_state()
4603 	       sizeof(saved_state->icl_port_dplls));  in intel_crtc_prepare_cleared_state()
4604 	saved_state->crc_enabled = crtc_state->crc_enabled;  in intel_crtc_prepare_cleared_state()
4605 	if (display->platform.g4x ||  in intel_crtc_prepare_cleared_state()
4606 	    display->platform.valleyview || display->platform.cherryview)  in intel_crtc_prepare_cleared_state()
4607 		saved_state->wm = crtc_state->wm;  in intel_crtc_prepare_cleared_state()
4630 	crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;  in intel_modeset_pipe_config()
4632 	crtc_state->framestart_delay = 1;  in intel_modeset_pipe_config()
4639 	if (!(crtc_state->hw.adjusted_mode.flags &  in intel_modeset_pipe_config()
4641 		crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;  in intel_modeset_pipe_config()
4643 	if (!(crtc_state->hw.adjusted_mode.flags &  in intel_modeset_pipe_config()
4645 		crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;  in intel_modeset_pipe_config()
4651 	crtc_state->dsc.compression_enabled_on_link = limits->link_dsc_pipes & BIT(crtc->pipe);  in intel_modeset_pipe_config()
4652 	crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];  in intel_modeset_pipe_config()
4654 	if (crtc_state->pipe_bpp > fxp_q4_to_int(crtc_state->max_link_bpp_x16)) {  in intel_modeset_pipe_config()
4655 		drm_dbg_kms(display->drm,  in intel_modeset_pipe_config()
4657 			    crtc->base.base.id, crtc->base.name,  in intel_modeset_pipe_config()
4658 			    FXP_Q4_ARGS(crtc_state->max_link_bpp_x16));  in intel_modeset_pipe_config()
4659 		crtc_state->bw_constrained = true;  in intel_modeset_pipe_config()
4662 	base_bpp = crtc_state->pipe_bpp;  in intel_modeset_pipe_config()
4672 	drm_mode_get_hv_timing(&crtc_state->hw.mode,  in intel_modeset_pipe_config()
4674 	drm_rect_init(&crtc_state->pipe_src, 0, 0,  in intel_modeset_pipe_config()
4677 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in intel_modeset_pipe_config()
4679 			to_intel_encoder(connector_state->best_encoder);  in intel_modeset_pipe_config()
4681 		if (connector_state->crtc != &crtc->base)  in intel_modeset_pipe_config()
4685 			drm_dbg_kms(display->drm,  in intel_modeset_pipe_config()
4687 				    encoder->base.base.id, encoder->base.name);  in intel_modeset_pipe_config()
4688 			return -EINVAL;  in intel_modeset_pipe_config()
4695 		if (encoder->compute_output_type)  in intel_modeset_pipe_config()
4696 			crtc_state->output_types |=  in intel_modeset_pipe_config()
4697 				BIT(encoder->compute_output_type(encoder, crtc_state,  in intel_modeset_pipe_config()
4700 			crtc_state->output_types |= BIT(encoder->type);  in intel_modeset_pipe_config()
4704 	crtc_state->port_clock = 0;  in intel_modeset_pipe_config()
4705 	crtc_state->pixel_multiplier = 1;  in intel_modeset_pipe_config()
4708 	drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,  in intel_modeset_pipe_config()
4715 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in intel_modeset_pipe_config()
4717 			to_intel_encoder(connector_state->best_encoder);  in intel_modeset_pipe_config()
4719 		if (connector_state->crtc != &crtc->base)  in intel_modeset_pipe_config()
4722 		ret = encoder->compute_config(encoder, crtc_state,  in intel_modeset_pipe_config()
4724 		if (ret == -EDEADLK)  in intel_modeset_pipe_config()
4727 			drm_dbg_kms(display->drm, "[ENCODER:%d:%s] config failure: %d\n",  in intel_modeset_pipe_config()
4728 				    encoder->base.base.id, encoder->base.name, ret);  in intel_modeset_pipe_config()
4735 	if (!crtc_state->port_clock)  in intel_modeset_pipe_config()
4736 		crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock  in intel_modeset_pipe_config()
4737 			* crtc_state->pixel_multiplier;  in intel_modeset_pipe_config()
4740 	if (ret == -EDEADLK)  in intel_modeset_pipe_config()
4743 		drm_dbg_kms(display->drm, "[CRTC:%d:%s] config failure: %d\n",  in intel_modeset_pipe_config()
4744 			    crtc->base.base.id, crtc->base.name, ret);  in intel_modeset_pipe_config()
4748 	/* Dithering seems to not pass-through bits correctly when it should, so  in intel_modeset_pipe_config()
4752 	crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&  in intel_modeset_pipe_config()
4753 		!crtc_state->dither_force_disable;  in intel_modeset_pipe_config()
4754 	drm_dbg_kms(display->drm,  in intel_modeset_pipe_config()
4756 		    crtc->base.base.id, crtc->base.name,  in intel_modeset_pipe_config()
4757 		    base_bpp, crtc_state->pipe_bpp, crtc_state->dither);  in intel_modeset_pipe_config()
4772 	for_each_new_connector_in_state(&state->base, connector,  in intel_modeset_pipe_config_late()
4775 			to_intel_encoder(conn_state->best_encoder);  in intel_modeset_pipe_config_late()
4778 		if (conn_state->crtc != &crtc->base ||  in intel_modeset_pipe_config_late()
4779 		    !encoder->compute_config_late)  in intel_modeset_pipe_config_late()
4782 		ret = encoder->compute_config_late(encoder, crtc_state,  in intel_modeset_pipe_config_late()
4801 	diff = abs(clock1 - clock2);  in intel_fuzzy_clock_check()
4813 	return m_n->tu == m2_n2->tu &&  in intel_compare_link_m_n()
4814 		m_n->data_m == m2_n2->data_m &&  in intel_compare_link_m_n()
4815 		m_n->data_n == m2_n2->data_n &&  in intel_compare_link_m_n()
4816 		m_n->link_m == m2_n2->link_m &&  in intel_compare_link_m_n()
4817 		m_n->link_n == m2_n2->link_n;  in intel_compare_link_m_n()
4831 	return a->pixelformat == b->pixelformat &&  in intel_compare_dp_vsc_sdp()
4832 		a->colorimetry == b->colorimetry &&  in intel_compare_dp_vsc_sdp()
4833 		a->bpc == b->bpc &&  in intel_compare_dp_vsc_sdp()
4834 		a->dynamic_range == b->dynamic_range &&  in intel_compare_dp_vsc_sdp()
4835 		a->content_type == b->content_type;  in intel_compare_dp_vsc_sdp()
4842 	return a->vtotal == b->vtotal &&  in intel_compare_dp_as_sdp()
4843 		a->target_rr == b->target_rr &&  in intel_compare_dp_as_sdp()
4844 		a->duration_incr_ms == b->duration_incr_ms &&  in intel_compare_dp_as_sdp()
4845 		a->duration_decr_ms == b->duration_decr_ms &&  in intel_compare_dp_as_sdp()
4846 		a->mode == b->mode;  in intel_compare_dp_as_sdp()
4869 			   crtc->base.base.id, crtc->base.name, name, &vaf);  in pipe_config_mismatch()
4872 			   crtc->base.base.id, crtc->base.name, name, &vaf);  in pipe_config_mismatch()
4899 	hdmi_infoframe_log(loglevel, display->drm->dev, a);  in pipe_config_infoframe_mismatch()
4901 	hdmi_infoframe_log(loglevel, display->drm->dev, b);  in pipe_config_infoframe_mismatch()
4940 	for (i = len - 1; i >= 0; i--) {  in memcmp_diff_len()
4972 	pipe_config_mismatch(p, fastset, crtc, name, " "); /* stupid -Werror=format-zero-length */  in pipe_config_pll_mismatch()
4988 	char *chipname = a->use_c10 ? "C10" : "C20";  in pipe_config_cx0pll_mismatch()
5013 	       (old_crtc_state->inherited || intel_vrr_always_use_vrr_tg(display)) &&  in allow_vblank_delay_fastset()
5041 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);  in intel_pipe_config_compare()
5047 		p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);  in intel_pipe_config_compare()
5049 		p = drm_err_printer(display->drm, NULL);  in intel_pipe_config_compare()
5052 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
5053 		BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \  in intel_pipe_config_compare()
5057 				     current_config->name, \  in intel_pipe_config_compare()
5058 				     pipe_config->name); \  in intel_pipe_config_compare()
5064 	if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \  in intel_pipe_config_compare()
5065 		BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \  in intel_pipe_config_compare()
5069 				     current_config->name & (mask), \  in intel_pipe_config_compare()
5070 				     pipe_config->name & (mask)); \  in intel_pipe_config_compare()
5076 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
5077 		BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \  in intel_pipe_config_compare()
5081 				     current_config->name, \  in intel_pipe_config_compare()
5082 				     pipe_config->name); \  in intel_pipe_config_compare()
5088 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
5091 				     current_config->name, \  in intel_pipe_config_compare()
5092 				     pipe_config->name); \  in intel_pipe_config_compare()
5098 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
5099 		BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \  in intel_pipe_config_compare()
5103 				     str_yes_no(current_config->name), \  in intel_pipe_config_compare()
5104 				     str_yes_no(pipe_config->name)); \  in intel_pipe_config_compare()
5110 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
5113 				     current_config->name, \  in intel_pipe_config_compare()
5114 				     pipe_config->name); \  in intel_pipe_config_compare()
5120 	if (!intel_compare_link_m_n(&current_config->name, \  in intel_pipe_config_compare()
5121 				    &pipe_config->name)) { \  in intel_pipe_config_compare()
5125 				     current_config->name.tu, \  in intel_pipe_config_compare()
5126 				     current_config->name.data_m, \  in intel_pipe_config_compare()
5127 				     current_config->name.data_n, \  in intel_pipe_config_compare()
5128 				     current_config->name.link_m, \  in intel_pipe_config_compare()
5129 				     current_config->name.link_n, \  in intel_pipe_config_compare()
5130 				     pipe_config->name.tu, \  in intel_pipe_config_compare()
5131 				     pipe_config->name.data_m, \  in intel_pipe_config_compare()
5132 				     pipe_config->name.data_n, \  in intel_pipe_config_compare()
5133 				     pipe_config->name.link_m, \  in intel_pipe_config_compare()
5134 				     pipe_config->name.link_n); \  in intel_pipe_config_compare()
5140 	if (!intel_dpll_compare_hw_state(display, &current_config->name, \  in intel_pipe_config_compare()
5141 					 &pipe_config->name)) { \  in intel_pipe_config_compare()
5143 					 &current_config->name, \  in intel_pipe_config_compare()
5144 					 &pipe_config->name); \  in intel_pipe_config_compare()
5150 	if (!intel_cx0pll_compare_hw_state(&current_config->name, \  in intel_pipe_config_compare()
5151 					   &pipe_config->name)) { \  in intel_pipe_config_compare()
5153 					    &current_config->name, \  in intel_pipe_config_compare()
5154 					    &pipe_config->name); \  in intel_pipe_config_compare()
5160 	if (!intel_lt_phy_pll_compare_hw_state(&current_config->name, \  in intel_pipe_config_compare()
5161 					       &pipe_config->name)) { \  in intel_pipe_config_compare()
5163 						&current_config->name, \  in intel_pipe_config_compare()
5164 						&pipe_config->name); \  in intel_pipe_config_compare()
5181 	if (!fastset || !pipe_config->update_lrr) { \  in intel_pipe_config_compare()
5195 	if ((current_config->name ^ pipe_config->name) & (mask)) { \  in intel_pipe_config_compare()
5199 				     current_config->name & (mask), \  in intel_pipe_config_compare()
5200 				     pipe_config->name & (mask)); \  in intel_pipe_config_compare()
5206 	if (!intel_compare_infoframe(&current_config->infoframes.name, \  in intel_pipe_config_compare()
5207 				     &pipe_config->infoframes.name)) { \  in intel_pipe_config_compare()
5209 					       &current_config->infoframes.name, \  in intel_pipe_config_compare()
5210 					       &pipe_config->infoframes.name); \  in intel_pipe_config_compare()
5216 	if (!intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \  in intel_pipe_config_compare()
5217 				      &pipe_config->infoframes.name)) { \  in intel_pipe_config_compare()
5219 						&current_config->infoframes.name, \  in intel_pipe_config_compare()
5220 						&pipe_config->infoframes.name); \  in intel_pipe_config_compare()
5226 	if (!intel_compare_dp_as_sdp(&current_config->infoframes.name, \  in intel_pipe_config_compare()
5227 				      &pipe_config->infoframes.name)) { \  in intel_pipe_config_compare()
5229 						&current_config->infoframes.name, \  in intel_pipe_config_compare()
5230 						&pipe_config->infoframes.name); \  in intel_pipe_config_compare()
5236 	BUILD_BUG_ON(sizeof(current_config->name) != (len)); \  in intel_pipe_config_compare()
5237 	BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \  in intel_pipe_config_compare()
5238 	if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \  in intel_pipe_config_compare()
5240 					    current_config->name, \  in intel_pipe_config_compare()
5241 					    pipe_config->name, \  in intel_pipe_config_compare()
5248 	if (current_config->gamma_mode == pipe_config->gamma_mode && \  in intel_pipe_config_compare()
5250 				   current_config->lut, pipe_config->lut, \  in intel_pipe_config_compare()
5277 	((current_config->quirks | pipe_config->quirks) & (quirk))  in intel_pipe_config_compare()
5295 		if (!fastset || !pipe_config->update_m_n)  in intel_pipe_config_compare()
5328 	if ((DISPLAY_VER(display) < 8 && !display->platform.haswell) ||  in intel_pipe_config_compare()
5329 	    display->platform.valleyview || display->platform.cherryview)  in intel_pipe_config_compare()
5368 		if (display->platform.cherryview)  in intel_pipe_config_compare()
5388 	if (display->dpll.mgr)  in intel_pipe_config_compare()
5392 	if (display->dpll.mgr || HAS_GMCH(display))  in intel_pipe_config_compare()
5404 	if (display->platform.g4x || DISPLAY_VER(display) >= 5)  in intel_pipe_config_compare()
5407 	if (!fastset || !pipe_config->update_m_n) {  in intel_pipe_config_compare()
5415 	if (current_config->has_psr || pipe_config->has_psr)  in intel_pipe_config_compare()
5418 	if (current_config->vrr.enable || pipe_config->vrr.enable)  in intel_pipe_config_compare()
5517 		assert_plane(plane, plane_state->is_y_plane ||  in intel_verify_planes()
5518 			     plane_state->uapi.visible);  in intel_verify_planes()
5526 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_modeset_pipe()
5529 	drm_dbg_kms(display->drm, "[CRTC:%d:%s] Full modeset due to %s\n",  in intel_modeset_pipe()
5530 		    crtc->base.base.id, crtc->base.name, reason);  in intel_modeset_pipe()
5532 	ret = drm_atomic_add_affected_connectors(&state->base,  in intel_modeset_pipe()
5533 						 &crtc->base);  in intel_modeset_pipe()
5549 	crtc_state->uapi.mode_changed = true;  in intel_modeset_pipe()
5555  * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes
5572 	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, mask) {  in intel_modeset_pipes_in_mask_early()
5576 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in intel_modeset_pipes_in_mask_early()
5580 		if (!crtc_state->hw.enable ||  in intel_modeset_pipes_in_mask_early()
5595 	crtc_state->uapi.mode_changed = true;  in intel_crtc_flag_modeset()
5597 	crtc_state->update_pipe = false;  in intel_crtc_flag_modeset()
5598 	crtc_state->update_m_n = false;  in intel_crtc_flag_modeset()
5599 	crtc_state->update_lrr = false;  in intel_crtc_flag_modeset()
5603  * intel_modeset_all_pipes_late - force a full modeset on all pipes
5619 	for_each_intel_crtc(display->drm, crtc) {  in intel_modeset_all_pipes_late()
5623 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in intel_modeset_all_pipes_late()
5627 		if (!crtc_state->hw.active ||  in intel_modeset_all_pipes_late()
5637 		crtc_state->update_planes |= crtc_state->active_planes;  in intel_modeset_all_pipes_late()
5638 		crtc_state->async_flip_planes = 0;  in intel_modeset_all_pipes_late()
5639 		crtc_state->do_async_flip = false;  in intel_modeset_all_pipes_late()
5653 	state = drm_atomic_state_alloc(display->drm);  in intel_modeset_commit_pipes()
5655 		return -ENOMEM;  in intel_modeset_commit_pipes()
5657 	state->acquire_ctx = ctx;  in intel_modeset_commit_pipes()
5658 	to_intel_atomic_state(state)->internal = true;  in intel_modeset_commit_pipes()
5660 	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) {  in intel_modeset_commit_pipes()
5669 		crtc_state->uapi.connectors_changed = true;  in intel_modeset_commit_pipes()
5696 		if (!crtc_state->hw.active ||  in hsw_mode_set_planes_workaround()
5705 			first_pipe = crtc->pipe;  in hsw_mode_set_planes_workaround()
5714 	for_each_intel_crtc(state->base.dev, crtc) {  in hsw_mode_set_planes_workaround()
5715 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in hsw_mode_set_planes_workaround()
5719 		crtc_state->hsw_workaround_pipe = INVALID_PIPE;  in hsw_mode_set_planes_workaround()
5721 		if (!crtc_state->hw.active ||  in hsw_mode_set_planes_workaround()
5729 		enabled_pipe = crtc->pipe;  in hsw_mode_set_planes_workaround()
5733 		first_crtc_state->hsw_workaround_pipe = enabled_pipe;  in hsw_mode_set_planes_workaround()
5735 		other_crtc_state->hsw_workaround_pipe = first_pipe;  in hsw_mode_set_planes_workaround()
5748 		if (crtc_state->hw.enable)  in intel_calc_enabled_pipes()
5749 			enabled_pipes |= BIT(crtc->pipe);  in intel_calc_enabled_pipes()
5751 			enabled_pipes &= ~BIT(crtc->pipe);  in intel_calc_enabled_pipes()
5765 		if (crtc_state->hw.active)  in intel_calc_active_pipes()
5766 			active_pipes |= BIT(crtc->pipe);  in intel_calc_active_pipes()
5768 			active_pipes &= ~BIT(crtc->pipe);  in intel_calc_active_pipes()
5778 	state->modeset = true;  in intel_modeset_checks()
5780 	if (display->platform.haswell)  in intel_modeset_checks()
5789 	const struct drm_display_mode *old_adjusted_mode = &old_crtc_state->hw.adjusted_mode;  in lrr_params_changed()
5790 	const struct drm_display_mode *new_adjusted_mode = &new_crtc_state->hw.adjusted_mode;  in lrr_params_changed()
5792 	return old_adjusted_mode->crtc_vblank_start != new_adjusted_mode->crtc_vblank_start ||  in lrr_params_changed()
5793 		old_adjusted_mode->crtc_vblank_end != new_adjusted_mode->crtc_vblank_end ||  in lrr_params_changed()
5794 		old_adjusted_mode->crtc_vtotal != new_adjusted_mode->crtc_vtotal ||  in lrr_params_changed()
5795 		old_crtc_state->set_context_latency != new_crtc_state->set_context_latency;  in lrr_params_changed()
5802 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);  in intel_crtc_check_fastset()
5805 	if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)  in intel_crtc_check_fastset()
5806 		new_crtc_state->update_lrr = false;  in intel_crtc_check_fastset()
5809 		drm_dbg_kms(display->drm, "[CRTC:%d:%s] fastset requirement not met, forcing full modeset\n",  in intel_crtc_check_fastset()
5810 			    crtc->base.base.id, crtc->base.name);  in intel_crtc_check_fastset()
5813 			new_crtc_state->update_lrr = true;  in intel_crtc_check_fastset()
5814 		new_crtc_state->uapi.mode_changed = false;  in intel_crtc_check_fastset()
5817 	if (intel_compare_link_m_n(&old_crtc_state->dp_m_n,  in intel_crtc_check_fastset()
5818 				   &new_crtc_state->dp_m_n))  in intel_crtc_check_fastset()
5819 		new_crtc_state->update_m_n = false;  in intel_crtc_check_fastset()
5822 		new_crtc_state->update_lrr = false;  in intel_crtc_check_fastset()
5827 		new_crtc_state->update_pipe = true;  in intel_crtc_check_fastset()
5842 			drm_dbg_atomic(display->drm,  in intel_atomic_check_crtcs()
5844 				       crtc->base.base.id, crtc->base.name);  in intel_atomic_check_crtcs()
5860 		if (new_crtc_state->hw.enable &&  in intel_cpu_transcoders_need_modeset()
5861 		    transcoders & BIT(new_crtc_state->cpu_transcoder) &&  in intel_cpu_transcoders_need_modeset()
5877 		if (new_crtc_state->hw.enable &&  in intel_pipes_need_modeset()
5878 		    pipes & BIT(crtc->pipe) &&  in intel_pipes_need_modeset()
5894 	if (!primary_crtc_state->joiner_pipes)  in intel_atomic_check_joiner()
5898 	if (drm_WARN_ON(display->drm,  in intel_atomic_check_joiner()
5899 			primary_crtc->pipe != joiner_primary_pipe(primary_crtc_state)))  in intel_atomic_check_joiner()
5900 		return -EINVAL;  in intel_atomic_check_joiner()
5902 	if (primary_crtc_state->joiner_pipes & ~joiner_pipes(display)) {  in intel_atomic_check_joiner()
5903 		drm_dbg_kms(display->drm,  in intel_atomic_check_joiner()
5906 			    primary_crtc->base.base.id, primary_crtc->base.name,  in intel_atomic_check_joiner()
5907 			    primary_crtc_state->joiner_pipes, joiner_pipes(display));  in intel_atomic_check_joiner()
5908 		return -EINVAL;  in intel_atomic_check_joiner()
5911 	for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc,  in intel_atomic_check_joiner()
5916 		secondary_crtc_state = intel_atomic_get_crtc_state(&state->base, secondary_crtc);  in intel_atomic_check_joiner()
5921 		if (secondary_crtc_state->uapi.enable) {  in intel_atomic_check_joiner()
5922 			drm_dbg_kms(display->drm,  in intel_atomic_check_joiner()
5925 				    secondary_crtc->base.base.id, secondary_crtc->base.name,  in intel_atomic_check_joiner()
5926 				    primary_crtc->base.base.id, primary_crtc->base.name);  in intel_atomic_check_joiner()
5927 			return -EINVAL;  in intel_atomic_check_joiner()
5937 		if (WARN_ON(drm_crtc_index(&primary_crtc->base) >  in intel_atomic_check_joiner()
5938 			    drm_crtc_index(&secondary_crtc->base)))  in intel_atomic_check_joiner()
5939 			return -EINVAL;  in intel_atomic_check_joiner()
5941 		drm_dbg_kms(display->drm,  in intel_atomic_check_joiner()
5943 			    secondary_crtc->base.base.id, secondary_crtc->base.name,  in intel_atomic_check_joiner()
5944 			    primary_crtc->base.base.id, primary_crtc->base.name);  in intel_atomic_check_joiner()
5946 		secondary_crtc_state->joiner_pipes =  in intel_atomic_check_joiner()
5947 			primary_crtc_state->joiner_pipes;  in intel_atomic_check_joiner()
5965 	for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc,  in kill_joiner_secondaries()
5970 		secondary_crtc_state->joiner_pipes = 0;  in kill_joiner_secondaries()
5975 	primary_crtc_state->joiner_pipes = 0;  in kill_joiner_secondaries()
6007 	if (!new_crtc_state->uapi.async_flip)  in intel_async_flip_check_uapi()
6010 	if (!new_crtc_state->uapi.active) {  in intel_async_flip_check_uapi()
6011 		drm_dbg_kms(display->drm,  in intel_async_flip_check_uapi()
6013 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_uapi()
6014 		return -EINVAL;  in intel_async_flip_check_uapi()
6018 		drm_dbg_kms(display->drm,  in intel_async_flip_check_uapi()
6020 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_uapi()
6021 		return -EINVAL;  in intel_async_flip_check_uapi()
6028 	if (new_crtc_state->joiner_pipes) {  in intel_async_flip_check_uapi()
6029 		drm_dbg_kms(display->drm,  in intel_async_flip_check_uapi()
6031 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_uapi()
6032 		return -EINVAL;  in intel_async_flip_check_uapi()
6036 	if (new_crtc_state->enable_psr2_sel_fetch) {  in intel_async_flip_check_uapi()
6037 		drm_dbg_kms(display->drm,  in intel_async_flip_check_uapi()
6039 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_uapi()
6040 		return -EINVAL;  in intel_async_flip_check_uapi()
6045 		if (plane->pipe != crtc->pipe)  in intel_async_flip_check_uapi()
6055 		if (!plane->async_flip) {  in intel_async_flip_check_uapi()
6056 			drm_dbg_kms(display->drm,  in intel_async_flip_check_uapi()
6058 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_uapi()
6059 			return -EINVAL;  in intel_async_flip_check_uapi()
6062 		if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) {  in intel_async_flip_check_uapi()
6063 			drm_dbg_kms(display->drm,  in intel_async_flip_check_uapi()
6065 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_uapi()
6066 			return -EINVAL;  in intel_async_flip_check_uapi()
6084 	if (!new_crtc_state->uapi.async_flip)  in intel_async_flip_check_hw()
6087 	if (!new_crtc_state->hw.active) {  in intel_async_flip_check_hw()
6088 		drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6090 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_hw()
6091 		return -EINVAL;  in intel_async_flip_check_hw()
6095 		drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6097 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_hw()
6098 		return -EINVAL;  in intel_async_flip_check_hw()
6101 	if (old_crtc_state->active_planes != new_crtc_state->active_planes) {  in intel_async_flip_check_hw()
6102 		drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6104 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_hw()
6105 		return -EINVAL;  in intel_async_flip_check_hw()
6110 		if (plane->pipe != crtc->pipe)  in intel_async_flip_check_hw()
6118 		if (drm_WARN_ON(display->drm,  in intel_async_flip_check_hw()
6119 				new_crtc_state->do_async_flip && !plane->async_flip))  in intel_async_flip_check_hw()
6120 			return -EINVAL;  in intel_async_flip_check_hw()
6130 		if (!plane->async_flip)  in intel_async_flip_check_hw()
6133 		if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->format->format,  in intel_async_flip_check_hw()
6134 						new_plane_state->hw.fb->modifier)) {  in intel_async_flip_check_hw()
6135 			drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6137 				    plane->base.base.id, plane->base.name,  in intel_async_flip_check_hw()
6138 				    &new_plane_state->hw.fb->format->format,  in intel_async_flip_check_hw()
6139 				    new_plane_state->hw.fb->modifier);  in intel_async_flip_check_hw()
6140 			return -EINVAL;  in intel_async_flip_check_hw()
6147 		if (!new_crtc_state->do_async_flip)  in intel_async_flip_check_hw()
6150 		if (old_plane_state->view.color_plane[0].mapping_stride !=  in intel_async_flip_check_hw()
6151 		    new_plane_state->view.color_plane[0].mapping_stride) {  in intel_async_flip_check_hw()
6152 			drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6154 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6155 			return -EINVAL;  in intel_async_flip_check_hw()
6158 		if (old_plane_state->hw.fb->modifier !=  in intel_async_flip_check_hw()
6159 		    new_plane_state->hw.fb->modifier) {  in intel_async_flip_check_hw()
6160 			drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6162 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6163 			return -EINVAL;  in intel_async_flip_check_hw()
6166 		if (old_plane_state->hw.fb->format !=  in intel_async_flip_check_hw()
6167 		    new_plane_state->hw.fb->format) {  in intel_async_flip_check_hw()
6168 			drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6170 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6171 			return -EINVAL;  in intel_async_flip_check_hw()
6174 		if (old_plane_state->hw.rotation !=  in intel_async_flip_check_hw()
6175 		    new_plane_state->hw.rotation) {  in intel_async_flip_check_hw()
6176 			drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6178 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6179 			return -EINVAL;  in intel_async_flip_check_hw()
6184 			drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6186 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6187 			return -EINVAL;  in intel_async_flip_check_hw()
6190 		if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||  in intel_async_flip_check_hw()
6191 		    !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {  in intel_async_flip_check_hw()
6192 			drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6193 				    "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n",  in intel_async_flip_check_hw()
6194 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6195 			return -EINVAL;  in intel_async_flip_check_hw()
6198 		if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {  in intel_async_flip_check_hw()
6199 			drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6201 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6202 			return -EINVAL;  in intel_async_flip_check_hw()
6205 		if (old_plane_state->hw.pixel_blend_mode !=  in intel_async_flip_check_hw()
6206 		    new_plane_state->hw.pixel_blend_mode) {  in intel_async_flip_check_hw()
6207 			drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6209 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6210 			return -EINVAL;  in intel_async_flip_check_hw()
6213 		if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {  in intel_async_flip_check_hw()
6214 			drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6216 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6217 			return -EINVAL;  in intel_async_flip_check_hw()
6220 		if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {  in intel_async_flip_check_hw()
6221 			drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6223 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6224 			return -EINVAL;  in intel_async_flip_check_hw()
6228 		if (old_plane_state->decrypt != new_plane_state->decrypt) {  in intel_async_flip_check_hw()
6229 			drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6231 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6232 			return -EINVAL;  in intel_async_flip_check_hw()
6256 		crtc = to_intel_crtc(plane_state->hw.crtc);  in intel_joiner_add_affected_crtcs()
6260 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in intel_joiner_add_affected_crtcs()
6267 		affected_pipes |= crtc_state->joiner_pipes;  in intel_joiner_add_affected_crtcs()
6269 			modeset_pipes |= crtc_state->joiner_pipes;  in intel_joiner_add_affected_crtcs()
6272 	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, affected_pipes) {  in intel_joiner_add_affected_crtcs()
6273 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in intel_joiner_add_affected_crtcs()
6278 	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, modeset_pipes) {  in intel_joiner_add_affected_crtcs()
6283 		crtc_state->uapi.mode_changed = true;  in intel_joiner_add_affected_crtcs()
6285 		ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);  in intel_joiner_add_affected_crtcs()
6295 		/* Kill old joiner link, we may re-establish afterwards */  in intel_joiner_add_affected_crtcs()
6333 		if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))  in intel_atomic_check_config()
6340 		if (!new_crtc_state->hw.enable)  in intel_atomic_check_config()
6352 		if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))  in intel_atomic_check_config()
6355 		if (!new_crtc_state->hw.enable)  in intel_atomic_check_config()
6365 		*failed_pipe = crtc->pipe;  in intel_atomic_check_config()
6389 			if (ret == -EINVAL &&  in intel_atomic_check_config_and_link()
6402 		if (ret != -EAGAIN)  in intel_atomic_check_config_and_link()
6409  * intel_atomic_check - validate state object
6423 		return -ENODEV;  in intel_atomic_check()
6431 		if (!state->internal)  in intel_atomic_check()
6432 			new_crtc_state->inherited = false;  in intel_atomic_check()
6434 		if (new_crtc_state->inherited != old_crtc_state->inherited)  in intel_atomic_check()
6435 			new_crtc_state->uapi.mode_changed = true;  in intel_atomic_check()
6437 		if (new_crtc_state->uapi.scaling_filter !=  in intel_atomic_check()
6438 		    old_crtc_state->uapi.scaling_filter)  in intel_atomic_check()
6439 			new_crtc_state->uapi.mode_changed = true;  in intel_atomic_check()
6444 	ret = drm_atomic_helper_check_modeset(dev, &state->base);  in intel_atomic_check()
6463 			drm_WARN_ON(display->drm, new_crtc_state->uapi.enable);  in intel_atomic_check()
6494 		if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))  in intel_atomic_check()
6501 			enum transcoder master = new_crtc_state->mst_master_transcoder;  in intel_atomic_check()
6508 			u8 trans = new_crtc_state->sync_mode_slaves_mask;  in intel_atomic_check()
6510 			if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)  in intel_atomic_check()
6511 				trans |= BIT(new_crtc_state->master_transcoder);  in intel_atomic_check()
6517 		if (new_crtc_state->joiner_pipes) {  in intel_atomic_check()
6518 			if (intel_pipes_need_modeset(state, new_crtc_state->joiner_pipes))  in intel_atomic_check()
6532 		drm_dbg_kms(display->drm, "rejecting conflicting digital port configuration\n");  in intel_atomic_check()
6533 		ret = -EINVAL;  in intel_atomic_check()
6542 		new_crtc_state->min_cdclk = intel_crtc_min_cdclk(new_crtc_state);  in intel_atomic_check()
6583 		drm_WARN_ON(display->drm,  in intel_atomic_check()
6599 	if (ret == -EDEADLK)  in intel_atomic_check()
6617 	ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);  in intel_atomic_prepare_commit()
6629 	if (DISPLAY_VER(display) != 2 || crtc_state->active_planes)  in intel_crtc_arm_fifo_underrun()
6630 		intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true);  in intel_crtc_arm_fifo_underrun()
6632 	if (crtc_state->has_pch_encoder) {  in intel_crtc_arm_fifo_underrun()
6644 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);  in intel_pipe_fastset()
6658 		if (new_crtc_state->pch_pfit.enabled)  in intel_pipe_fastset()
6661 		if (new_crtc_state->pch_pfit.enabled)  in intel_pipe_fastset()
6663 		else if (old_crtc_state->pch_pfit.enabled)  in intel_pipe_fastset()
6676 	    display->platform.broadwell || display->platform.haswell)  in intel_pipe_fastset()
6679 	if (new_crtc_state->update_m_n)  in intel_pipe_fastset()
6680 		intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,  in intel_pipe_fastset()
6681 					       &new_crtc_state->dp_m_n);  in intel_pipe_fastset()
6683 	if (new_crtc_state->update_lrr)  in intel_pipe_fastset()
6697 	drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq);  in commit_pipe_pre_planes()
6707 		if (DISPLAY_VER(display) >= 9 || display->platform.broadwell)  in commit_pipe_pre_planes()
6727 	drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq);  in commit_pipe_post_planes()
6758 	for_each_intel_crtc_in_pipe_mask_reverse(display->drm, pipe_crtc,  in intel_enable_crtc()
6769 	display->funcs.display->crtc_enable(state, crtc);  in intel_enable_crtc()
6771 	/* vblanks work again, re-enable pipe CRC. */  in intel_enable_crtc()
6785 	if (old_crtc_state->inherited ||  in intel_pre_update_crtc()
6792 		if (new_crtc_state->preload_luts &&  in intel_pre_update_crtc()
6812 	else if (new_crtc_state->hw.casf_params.strength != old_crtc_state->hw.casf_params.strength)  in intel_pre_update_crtc()
6817 	drm_WARN_ON(display->drm, !intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF));  in intel_pre_update_crtc()
6821 	    !new_crtc_state->use_dsb && !new_crtc_state->use_flipq)  in intel_pre_update_crtc()
6824 	if (!new_crtc_state->use_dsb && !new_crtc_state->use_flipq)  in intel_pre_update_crtc()
6836 	if (new_crtc_state->use_flipq) {  in intel_update_crtc()
6839 		intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->flipq_event);  in intel_update_crtc()
6842 				new_crtc_state->dsb_commit);  in intel_update_crtc()
6843 	} else if (new_crtc_state->use_dsb) {  in intel_update_crtc()
6844 		intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->dsb_event);  in intel_update_crtc()
6846 		intel_dsb_commit(new_crtc_state->dsb_commit);  in intel_update_crtc()
6851 		if (new_crtc_state->dsb_commit)  in intel_update_crtc()
6852 			intel_dsb_commit(new_crtc_state->dsb_commit);  in intel_update_crtc()
6869 	    new_crtc_state->update_m_n || new_crtc_state->update_lrr)  in intel_update_crtc()
6871 						 new_crtc_state->vrr.enable);  in intel_update_crtc()
6880 	    old_crtc_state->inherited)  in intel_update_crtc()
6896 	for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,  in intel_old_crtc_state_disables()
6902 	display->funcs.display->crtc_disable(state, crtc);  in intel_old_crtc_state_disables()
6904 	for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,  in intel_old_crtc_state_disables()
6909 		pipe_crtc->active = false;  in intel_old_crtc_state_disables()
6912 		if (!new_pipe_crtc_state->hw.active)  in intel_old_crtc_state_disables()
6936 		if (!old_crtc_state->hw.active)  in intel_commit_modeset_disables()
6939 		disable_pipes |= BIT(crtc->pipe);  in intel_commit_modeset_disables()
6943 		if ((disable_pipes & BIT(crtc->pipe)) == 0)  in intel_commit_modeset_disables()
6948 		drm_vblank_work_flush_all(&crtc->base);  in intel_commit_modeset_disables()
6953 		if ((disable_pipes & BIT(crtc->pipe)) == 0)  in intel_commit_modeset_disables()
6975 		if ((disable_pipes & BIT(crtc->pipe)) == 0)  in intel_commit_modeset_disables()
6986 	drm_WARN_ON(display->drm, disable_pipes);  in intel_commit_modeset_disables()
6996 		if (!new_crtc_state->hw.active)  in intel_commit_modeset_enables()
7004 		if (!new_crtc_state->hw.active)  in intel_commit_modeset_enables()
7021 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
7023 		if (!new_crtc_state->hw.active)  in skl_commit_modeset_enables()
7028 			entries[pipe] = old_crtc_state->wm.skl.ddb;  in skl_commit_modeset_enables()
7045 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
7062 			enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
7067 			if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,  in skl_commit_modeset_enables()
7071 			entries[pipe] = new_crtc_state->wm.skl.ddb;  in skl_commit_modeset_enables()
7082 			if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,  in skl_commit_modeset_enables()
7083 						 &old_crtc_state->wm.skl.ddb) &&  in skl_commit_modeset_enables()
7098 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
7120 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
7137 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
7150 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
7155 		drm_WARN_ON(display->drm,  in skl_commit_modeset_enables()
7156 			    skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,  in skl_commit_modeset_enables()
7159 		entries[pipe] = new_crtc_state->wm.skl.ddb;  in skl_commit_modeset_enables()
7165 	drm_WARN_ON(display->drm, modeset_pipes);  in skl_commit_modeset_enables()
7166 	drm_WARN_ON(display->drm, update_pipes);  in skl_commit_modeset_enables()
7171 	struct drm_i915_private *i915 = to_i915(intel_state->base.dev);  in intel_atomic_commit_fence_wait()
7177 	for_each_new_plane_in_state(&intel_state->base, plane, new_plane_state, i) {  in intel_atomic_commit_fence_wait()
7178 		if (new_plane_state->fence) {  in intel_atomic_commit_fence_wait()
7179 			ret = dma_fence_wait_timeout(new_plane_state->fence, false,  in intel_atomic_commit_fence_wait()
7184 			dma_fence_put(new_plane_state->fence);  in intel_atomic_commit_fence_wait()
7185 			new_plane_state->fence = NULL;  in intel_atomic_commit_fence_wait()
7192 	if (crtc_state->dsb_commit)  in intel_atomic_dsb_wait_commit()
7193 		intel_dsb_wait(crtc_state->dsb_commit);  in intel_atomic_dsb_wait_commit()
7200 	if (crtc_state->dsb_commit) {  in intel_atomic_dsb_cleanup()
7201 		intel_dsb_cleanup(crtc_state->dsb_commit);  in intel_atomic_dsb_cleanup()
7202 		crtc_state->dsb_commit = NULL;  in intel_atomic_dsb_cleanup()
7220 	drm_atomic_helper_cleanup_planes(display->drm, &state->base);  in intel_atomic_cleanup_work()
7221 	drm_atomic_helper_commit_cleanup_done(&state->base);  in intel_atomic_cleanup_work()
7222 	drm_atomic_state_put(&state->base);  in intel_atomic_cleanup_work()
7233 		struct drm_framebuffer *fb = plane_state->hw.fb;  in intel_atomic_prepare_plane_clear_colors()
7249 		 * - 4 x 4 bytes per-channel value  in intel_atomic_prepare_plane_clear_colors()
7251 		 * - 8 bytes native color value used by the display  in intel_atomic_prepare_plane_clear_colors()
7253 		 *    above per-channel values)  in intel_atomic_prepare_plane_clear_colors()
7260 					      fb->offsets[cc_plane] + 16,  in intel_atomic_prepare_plane_clear_colors()
7261 					      &plane_state->ccval,  in intel_atomic_prepare_plane_clear_colors()
7262 					      sizeof(plane_state->ccval));  in intel_atomic_prepare_plane_clear_colors()
7264 		drm_WARN_ON(display->drm, ret);  in intel_atomic_prepare_plane_clear_colors()
7275 	if (!new_crtc_state->hw.active)  in intel_atomic_dsb_prepare()
7278 	if (state->base.legacy_cursor_update)  in intel_atomic_dsb_prepare()
7282 	new_crtc_state->use_flipq =  in intel_atomic_dsb_prepare()
7284 		!new_crtc_state->do_async_flip &&  in intel_atomic_dsb_prepare()
7285 		!new_crtc_state->vrr.enable &&  in intel_atomic_dsb_prepare()
7286 		!new_crtc_state->has_psr &&  in intel_atomic_dsb_prepare()
7291 	new_crtc_state->use_dsb =  in intel_atomic_dsb_prepare()
7292 		!new_crtc_state->use_flipq &&  in intel_atomic_dsb_prepare()
7293 		!new_crtc_state->do_async_flip &&  in intel_atomic_dsb_prepare()
7294 		(DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) &&  in intel_atomic_dsb_prepare()
7307 	unsigned int size = new_crtc_state->plane_color_changed ? 8192 : 1024;  in intel_atomic_dsb_finish()
7309 	if (!new_crtc_state->use_flipq &&  in intel_atomic_dsb_finish()
7310 	    !new_crtc_state->use_dsb &&  in intel_atomic_dsb_finish()
7311 	    !new_crtc_state->dsb_color)  in intel_atomic_dsb_finish()
7321 	new_crtc_state->dsb_commit = intel_dsb_prepare(state, crtc, INTEL_DSB_0,  in intel_atomic_dsb_finish()
7322 						       new_crtc_state->use_dsb ||  in intel_atomic_dsb_finish()
7323 						       new_crtc_state->use_flipq ? size : 16);  in intel_atomic_dsb_finish()
7324 	if (!new_crtc_state->dsb_commit) {  in intel_atomic_dsb_finish()
7325 		new_crtc_state->use_flipq = false;  in intel_atomic_dsb_finish()
7326 		new_crtc_state->use_dsb = false;  in intel_atomic_dsb_finish()
7331 	if (new_crtc_state->use_flipq || new_crtc_state->use_dsb) {  in intel_atomic_dsb_finish()
7333 		if (new_crtc_state->use_flipq)  in intel_atomic_dsb_finish()
7334 			intel_flipq_wait_dmc_halt(new_crtc_state->dsb_commit, crtc);  in intel_atomic_dsb_finish()
7337 			intel_color_commit_noarm(new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7339 		intel_crtc_planes_update_noarm(new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7347 		intel_psr_trigger_frame_change_event(new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7350 		intel_psr_wait_for_idle_dsb(new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7353 		if (new_crtc_state->use_dsb)  in intel_atomic_dsb_finish()
7354 			intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit);  in intel_atomic_dsb_finish()
7357 			intel_color_commit_arm(new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7359 		bdw_set_pipe_misc(new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7361 		intel_psr2_program_trans_man_trk_ctl(new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7363 		intel_crtc_planes_update_arm(new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7367 			skl_detach_scalers(new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7371 		if (new_crtc_state->use_flipq)  in intel_atomic_dsb_finish()
7372 			intel_flipq_unhalt_dmc(new_crtc_state->dsb_commit, crtc);  in intel_atomic_dsb_finish()
7376 		intel_dsb_chain(state, new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7377 				new_crtc_state->dsb_color, true);  in intel_atomic_dsb_finish()
7379 		intel_dsb_gosub(new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7380 				new_crtc_state->dsb_color);  in intel_atomic_dsb_finish()
7382 	if (new_crtc_state->use_dsb && !intel_color_uses_chained_dsb(new_crtc_state)) {  in intel_atomic_dsb_finish()
7383 		intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);  in intel_atomic_dsb_finish()
7385 		intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);  in intel_atomic_dsb_finish()
7386 		intel_dsb_wait_for_delayed_vblank(state, new_crtc_state->dsb_commit);  in intel_atomic_dsb_finish()
7387 		intel_vrr_check_push_sent(new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7389 		intel_dsb_interrupt(new_crtc_state->dsb_commit);  in intel_atomic_dsb_finish()
7392 	intel_dsb_finish(new_crtc_state->dsb_commit);  in intel_atomic_dsb_finish()
7398 	struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm);  in intel_atomic_commit_tail()
7420 	drm_atomic_helper_wait_for_dependencies(&state->base);  in intel_atomic_commit_tail()
7421 	drm_dp_mst_atomic_wait_for_dependencies(&state->base);  in intel_atomic_commit_tail()
7433 	 * 3. Due to some long delay PSR is re-entered  in intel_atomic_commit_tail()
7434 	 * 4. DC5 entry -> DMC saves the already written new  in intel_atomic_commit_tail()
7437 	 * 5. DC5 exit -> DMC restores a mixture of old and  in intel_atomic_commit_tail()
7439 	 * 6. PSR exit -> hardware latches a mixture of old and  in intel_atomic_commit_tail()
7440 	 *    new register values -> corrupted frame, or worse  in intel_atomic_commit_tail()
7457 			intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);  in intel_atomic_commit_tail()
7464 	/* FIXME: Eventually get rid of our crtc->config pointer */  in intel_atomic_commit_tail()
7466 		crtc->config = new_crtc_state;  in intel_atomic_commit_tail()
7476 	if (state->modeset)  in intel_atomic_commit_tail()
7477 		drm_atomic_helper_update_legacy_modeset_state(display->drm, &state->base);  in intel_atomic_commit_tail()
7481 	if (state->modeset)  in intel_atomic_commit_tail()
7491 		if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {  in intel_atomic_commit_tail()
7492 			spin_lock_irq(&display->drm->event_lock);  in intel_atomic_commit_tail()
7493 			drm_crtc_send_vblank_event(&crtc->base,  in intel_atomic_commit_tail()
7494 						   new_crtc_state->uapi.event);  in intel_atomic_commit_tail()
7495 			spin_unlock_irq(&display->drm->event_lock);  in intel_atomic_commit_tail()
7497 			new_crtc_state->uapi.event = NULL;  in intel_atomic_commit_tail()
7506 		if (new_crtc_state->do_async_flip)  in intel_atomic_commit_tail()
7511 	display->funcs.display->commit_modeset_enables(state);  in intel_atomic_commit_tail()
7521 	 * - wrap the optimization/post_plane_update stuff into a per-crtc work.  in intel_atomic_commit_tail()
7522 	 * - schedule that vblank worker _before_ calling hw_done  in intel_atomic_commit_tail()
7523 	 * - at the start of commit_tail, cancel it _synchrously  in intel_atomic_commit_tail()
7524 	 * - switch over to the vblank wait helper in the core after that since  in intel_atomic_commit_tail()
7527 	drm_atomic_helper_wait_for_flip_done(display->drm, &state->base);  in intel_atomic_commit_tail()
7530 		if (new_crtc_state->do_async_flip)  in intel_atomic_commit_tail()
7535 		if (!state->base.legacy_cursor_update && !new_crtc_state->use_dsb)  in intel_atomic_commit_tail()
7538 		if (new_crtc_state->use_flipq)  in intel_atomic_commit_tail()
7544 	 * optimal watermarks on platforms that need two-step watermark  in intel_atomic_commit_tail()
7553 		 * So re-enable underrun reporting after some planes get enabled.  in intel_atomic_commit_tail()
7560 			intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true);  in intel_atomic_commit_tail()
7570 		intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);  in intel_atomic_commit_tail()
7581 		 * FIXME get rid of this funny new->old swapping  in intel_atomic_commit_tail()
7583 		old_crtc_state->dsb_color = fetch_and_zero(&new_crtc_state->dsb_color);  in intel_atomic_commit_tail()
7584 		old_crtc_state->dsb_commit = fetch_and_zero(&new_crtc_state->dsb_commit);  in intel_atomic_commit_tail()
7591 	if (state->modeset)  in intel_atomic_commit_tail()
7598 	drm_atomic_helper_commit_hw_done(&state->base);  in intel_atomic_commit_tail()
7601 	if (state->modeset) {  in intel_atomic_commit_tail()
7605 		 * so enable debugging for the next modeset - and hope we catch  in intel_atomic_commit_tail()
7608 		intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);  in intel_atomic_commit_tail()
7611 	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off  in intel_atomic_commit_tail()
7615 	intel_display_rpm_put(display, state->wakeref);  in intel_atomic_commit_tail()
7620 	 * are executed inline. For out-of-line asynchronous modesets/flips,  in intel_atomic_commit_tail()
7625 	INIT_WORK(&state->cleanup_work, intel_atomic_cleanup_work);  in intel_atomic_commit_tail()
7626 	queue_work(display->wq.cleanup, &state->cleanup_work);  in intel_atomic_commit_tail()
7645 		intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),  in intel_atomic_track_fbs()
7646 					to_intel_frontbuffer(new_plane_state->hw.fb),  in intel_atomic_track_fbs()
7647 					plane->frontbuffer_bit);  in intel_atomic_track_fbs()
7654 	ret = drm_atomic_helper_setup_commit(&state->base, nonblock);  in intel_atomic_setup_commit()
7669 	ret = drm_atomic_helper_swap_state(&state->base, true);  in intel_atomic_swap_state()
7689 	state->wakeref = intel_display_rpm_get(display);  in intel_atomic_commit()
7699 	 * Unset state->legacy_cursor_update before the call to  in intel_atomic_commit()
7708 	if (DISPLAY_VER(display) < 9 && state->base.legacy_cursor_update) {  in intel_atomic_commit()
7714 			if (new_crtc_state->wm.need_postvbl_update ||  in intel_atomic_commit()
7715 			    new_crtc_state->update_wm_post)  in intel_atomic_commit()
7716 				state->base.legacy_cursor_update = false;  in intel_atomic_commit()
7721 		drm_dbg_atomic(display->drm,  in intel_atomic_commit()
7723 		intel_display_rpm_put(display, state->wakeref);  in intel_atomic_commit()
7732 		drm_atomic_helper_unprepare_planes(dev, &state->base);  in intel_atomic_commit()
7733 		intel_display_rpm_put(display, state->wakeref);  in intel_atomic_commit()
7737 	drm_atomic_state_get(&state->base);  in intel_atomic_commit()
7738 	INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);  in intel_atomic_commit()
7740 	if (nonblock && state->modeset) {  in intel_atomic_commit()
7741 		queue_work(display->wq.modeset, &state->base.commit_work);  in intel_atomic_commit()
7743 		queue_work(display->wq.flip, &state->base.commit_work);  in intel_atomic_commit()
7745 		if (state->modeset)  in intel_atomic_commit()
7746 			flush_workqueue(display->wq.modeset);  in intel_atomic_commit()
7759 	for_each_intel_encoder(display->drm, source_encoder) {  in intel_encoder_possible_clones()
7761 			possible_clones |= drm_encoder_mask(&source_encoder->base);  in intel_encoder_possible_clones()
7773 	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, encoder->pipe_mask)  in intel_encoder_possible_crtcs()
7774 		possible_crtcs |= drm_crtc_mask(&crtc->base);  in intel_encoder_possible_crtcs()
7781 	if (!display->platform.mobile)  in ilk_has_edp_a()
7787 	if (display->platform.ironlake && (intel_de_read(display, FUSE_STRAP) & ILK_eDP_A_DISABLE))  in ilk_has_edp_a()
7798 	if (display->platform.haswell_ult || display->platform.broadwell_ult)  in intel_ddi_crt_present()
7809 	if (!display->vbt.int_crt_support)  in intel_ddi_crt_present()
7817 	return !drm_WARN(display->drm, !(DISPLAY_RUNTIME_INFO(display)->port_mask & BIT(port)),  in assert_port_valid()
7837 		if (display->platform.geminilake || display->platform.broxton)  in intel_setup_outputs()
7875 	} else if (display->platform.valleyview || display->platform.cherryview) {  in intel_setup_outputs()
7878 		if (display->platform.valleyview && display->vbt.int_crt_support)  in intel_setup_outputs()
7884 		 * (no way to plug in a DP->HDMI dongle) the DDC pins for  in intel_setup_outputs()
7891 		 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap  in intel_setup_outputs()
7910 		if (display->platform.cherryview) {  in intel_setup_outputs()
7923 	} else if (display->platform.pineview) {  in intel_setup_outputs()
7929 		if (display->platform.mobile)  in intel_setup_outputs()
7935 			drm_dbg_kms(display->drm, "probing SDVOB\n");  in intel_setup_outputs()
7937 			if (!found && display->platform.g4x) {  in intel_setup_outputs()
7938 				drm_dbg_kms(display->drm,  in intel_setup_outputs()
7943 			if (!found && display->platform.g4x)  in intel_setup_outputs()
7950 			drm_dbg_kms(display->drm, "probing SDVOC\n");  in intel_setup_outputs()
7956 			if (display->platform.g4x) {  in intel_setup_outputs()
7957 				drm_dbg_kms(display->drm,  in intel_setup_outputs()
7961 			if (display->platform.g4x)  in intel_setup_outputs()
7965 		if (display->platform.g4x && (intel_de_read(display, DP_D) & DP_DETECTED))  in intel_setup_outputs()
7971 		if (display->platform.i85x)  in intel_setup_outputs()
7978 	for_each_intel_encoder(display->drm, encoder) {  in intel_setup_outputs()
7979 		encoder->base.possible_crtcs =  in intel_setup_outputs()
7981 		encoder->base.possible_clones =  in intel_setup_outputs()
7987 	drm_helper_move_panel_connectors_to_head(display->drm);  in intel_setup_outputs()
7992 	int max_dotclock = display->cdclk.max_dotclk_freq;  in max_dotclock()
8017 	 * reject modes with the DBLSCAN flag in encoder->compute_config().  in intel_mode_valid()
8018 	 * And we always reject DBLSCAN modes in connector->mode_valid()  in intel_mode_valid()
8022 	if (mode->vscan > 1)  in intel_mode_valid()
8025 	if (mode->flags & DRM_MODE_FLAG_HSKEW)  in intel_mode_valid()
8028 	if (mode->flags & (DRM_MODE_FLAG_CSYNC |  in intel_mode_valid()
8033 	if (mode->flags & (DRM_MODE_FLAG_BCAST |  in intel_mode_valid()
8042 	if (mode->clock > max_dotclock(display))  in intel_mode_valid()
8052 		   display->platform.broadwell || display->platform.haswell) {  in intel_mode_valid()
8069 	if (mode->hdisplay > hdisplay_max ||  in intel_mode_valid()
8070 	    mode->hsync_start > htotal_max ||  in intel_mode_valid()
8071 	    mode->hsync_end > htotal_max ||  in intel_mode_valid()
8072 	    mode->htotal > htotal_max)  in intel_mode_valid()
8075 	if (mode->vdisplay > vdisplay_max ||  in intel_mode_valid()
8076 	    mode->vsync_start > vtotal_max ||  in intel_mode_valid()
8077 	    mode->vsync_end > vtotal_max ||  in intel_mode_valid()
8078 	    mode->vtotal > vtotal_max)  in intel_mode_valid()
8086 	if (DIV_ROUND_UP(mode->htotal * 1000, mode->clock) > 64)  in intel_mode_valid()
8100 		if (mode->hdisplay < 64 ||  in intel_cpu_transcoder_mode_valid()
8101 		    mode->htotal - mode->hdisplay < 32)  in intel_cpu_transcoder_mode_valid()
8104 		if (mode->vtotal - mode->vdisplay < 5)  in intel_cpu_transcoder_mode_valid()
8107 		if (mode->htotal - mode->hdisplay < 32)  in intel_cpu_transcoder_mode_valid()
8110 		if (mode->vtotal - mode->vdisplay < 3)  in intel_cpu_transcoder_mode_valid()
8118 	if ((DISPLAY_VER(display) >= 5 || display->platform.g4x) &&  in intel_cpu_transcoder_mode_valid()
8119 	    mode->hsync_start == mode->hdisplay)  in intel_cpu_transcoder_mode_valid()
8155 	if (mode->hdisplay > plane_width_max)  in intel_mode_valid_max_plane_size()
8158 	if (mode->vdisplay > plane_height_max)  in intel_mode_valid_max_plane_size()
8210  * intel_init_display_hooks - initialize the display modesetting hooks
8216 		display->funcs.display = &skl_display_funcs;  in intel_init_display_hooks()
8218 		display->funcs.display = &ddi_display_funcs;  in intel_init_display_hooks()
8220 		display->funcs.display = &pch_split_display_funcs;  in intel_init_display_hooks()
8221 	} else if (display->platform.cherryview ||  in intel_init_display_hooks()
8222 		   display->platform.valleyview) {  in intel_init_display_hooks()
8223 		display->funcs.display = &vlv_display_funcs;  in intel_init_display_hooks()
8225 		display->funcs.display = &i9xx_display_funcs;  in intel_init_display_hooks()
8236 	state = drm_atomic_state_alloc(display->drm);  in intel_initial_commit()
8238 		return -ENOMEM;  in intel_initial_commit()
8242 	state->acquire_ctx = &ctx;  in intel_initial_commit()
8243 	to_intel_atomic_state(state)->internal = true;  in intel_initial_commit()
8246 	for_each_intel_crtc(display->drm, crtc) {  in intel_initial_commit()
8255 		if (!crtc_state->hw.active)  in intel_initial_commit()
8256 			crtc_state->inherited = false;  in intel_initial_commit()
8258 		if (crtc_state->hw.active) {  in intel_initial_commit()
8261 			ret = drm_atomic_add_affected_planes(state, &crtc->base);  in intel_initial_commit()
8271 			crtc_state->uapi.color_mgmt_changed = true;  in intel_initial_commit()
8273 			for_each_intel_encoder_mask(display->drm, encoder,  in intel_initial_commit()
8274 						    crtc_state->uapi.encoder_mask) {  in intel_initial_commit()
8275 				if (encoder->initial_fastset_check &&  in intel_initial_commit()
8276 				    !encoder->initial_fastset_check(encoder, crtc_state)) {  in intel_initial_commit()
8278 										 &crtc->base);  in intel_initial_commit()
8289 	if (ret == -EDEADLK) {  in intel_initial_commit()
8318 	drm_WARN_ON(display->drm,  in i830_enable_pipe()
8321 	drm_dbg_kms(display->drm,  in i830_enable_pipe()
8328 		((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |  in i830_enable_pipe()
8334 		       HACTIVE(640 - 1) | HTOTAL(800 - 1));  in i830_enable_pipe()
8336 		       HBLANK_START(640 - 1) | HBLANK_END(800 - 1));  in i830_enable_pipe()
8338 		       HSYNC_START(656 - 1) | HSYNC_END(752 - 1));  in i830_enable_pipe()
8340 		       VACTIVE(480 - 1) | VTOTAL(525 - 1));  in i830_enable_pipe()
8342 		       VBLANK_START(480 - 1) | VBLANK_END(525 - 1));  in i830_enable_pipe()
8344 		       VSYNC_START(490 - 1) | VSYNC_END(492 - 1));  in i830_enable_pipe()
8346 		       PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));  in i830_enable_pipe()
8388 	drm_dbg_kms(display->drm, "disabling pipe %c due to force quirk\n",  in i830_disable_pipe()
8391 	drm_WARN_ON(display->drm,  in i830_disable_pipe()
8393 	drm_WARN_ON(display->drm,  in i830_disable_pipe()
8395 	drm_WARN_ON(display->drm,  in i830_disable_pipe()
8397 	drm_WARN_ON(display->drm,  in i830_disable_pipe()
8399 	drm_WARN_ON(display->drm,  in i830_disable_pipe()