Lines Matching full:display
35 #include <drm/display/drm_dp_helper.h>
36 #include <drm/display/drm_dp_tunnel.h>
187 void intel_update_czclk(struct intel_display *display) in intel_update_czclk() argument
189 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_update_czclk()
191 if (!display->platform.valleyview && !display->platform.cherryview) in intel_update_czclk()
197 drm_dbg_kms(display->drm, "CZ clock rate: %d kHz\n", dev_priv->czclk_freq); in intel_update_czclk()
206 /* WA Display #0827: Gen9:all */
208 skl_wa_827(struct intel_display *display, enum pipe pipe, bool enable) in skl_wa_827() argument
210 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), in skl_wa_827()
217 icl_wa_scalerclkgating(struct intel_display *display, enum pipe pipe, in icl_wa_scalerclkgating() argument
220 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), in icl_wa_scalerclkgating()
227 icl_wa_cursorclkgating(struct intel_display *display, enum pipe pipe, in icl_wa_cursorclkgating() argument
230 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), in icl_wa_cursorclkgating()
399 struct intel_display *display = to_intel_display(crtc_state); in intel_primary_crtc() local
402 return intel_crtc_for_pipe(display, joiner_primary_pipe(crtc_state)); in intel_primary_crtc()
410 struct intel_display *display = to_intel_display(old_crtc_state); in intel_wait_for_pipe_off() local
413 if (DISPLAY_VER(display) >= 4) { in intel_wait_for_pipe_off()
417 if (intel_de_wait_for_clear(display, TRANSCONF(display, cpu_transcoder), in intel_wait_for_pipe_off()
419 drm_WARN(display->drm, 1, "pipe_off wait timed out\n"); in intel_wait_for_pipe_off()
425 void assert_transcoder(struct intel_display *display, in assert_transcoder() argument
433 if (display->platform.i830) in assert_transcoder()
437 wakeref = intel_display_power_get_if_enabled(display, power_domain); in assert_transcoder()
439 u32 val = intel_de_read(display, in assert_transcoder()
440 TRANSCONF(display, cpu_transcoder)); in assert_transcoder()
443 intel_display_power_put(display, power_domain, wakeref); in assert_transcoder()
448 INTEL_DISPLAY_STATE_WARN(display, cur_state != state, in assert_transcoder()
456 struct intel_display *display = to_intel_display(plane->base.dev); in assert_plane() local
462 INTEL_DISPLAY_STATE_WARN(display, cur_state != state, in assert_plane()
473 struct intel_display *display = to_intel_display(crtc); in assert_planes_disabled() local
476 for_each_intel_plane_on_crtc(display->drm, crtc, plane) in assert_planes_disabled()
482 struct intel_display *display = to_intel_display(new_crtc_state); in intel_enable_transcoder() local
488 drm_dbg_kms(display->drm, "enabling pipe %c\n", pipe_name(pipe)); in intel_enable_transcoder()
497 if (HAS_GMCH(display)) { in intel_enable_transcoder()
499 assert_dsi_pll_enabled(display); in intel_enable_transcoder()
501 assert_pll_enabled(display, pipe); in intel_enable_transcoder()
505 assert_fdi_rx_pll_enabled(display, in intel_enable_transcoder()
507 assert_fdi_tx_pll_enabled(display, in intel_enable_transcoder()
514 if (DISPLAY_VER(display) == 13) in intel_enable_transcoder()
515 intel_de_rmw(display, PIPE_ARB_CTL(display, pipe), in intel_enable_transcoder()
518 if (DISPLAY_VER(display) >= 14) { in intel_enable_transcoder()
522 if (DISPLAY_VER(display) == 14) in intel_enable_transcoder()
525 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), in intel_enable_transcoder()
529 val = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); in intel_enable_transcoder()
532 drm_WARN_ON(display->drm, !display->platform.i830); in intel_enable_transcoder()
537 if (DISPLAY_VER(display) >= 13 && in intel_enable_transcoder()
544 intel_de_write(display, TRANSCONF(display, cpu_transcoder), in intel_enable_transcoder()
546 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); in intel_enable_transcoder()
561 struct intel_display *display = to_intel_display(old_crtc_state); in intel_disable_transcoder() local
567 drm_dbg_kms(display->drm, "disabling pipe %c\n", pipe_name(pipe)); in intel_disable_transcoder()
571 * or we might hang the display. in intel_disable_transcoder()
575 val = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); in intel_disable_transcoder()
587 if (!display->platform.i830) in intel_disable_transcoder()
591 if (DISPLAY_VER(display) >= 13 && in intel_disable_transcoder()
595 intel_de_write(display, TRANSCONF(display, cpu_transcoder), val); in intel_disable_transcoder()
597 if (DISPLAY_VER(display) >= 12) in intel_disable_transcoder()
598 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), in intel_disable_transcoder()
608 struct intel_display *display = to_intel_display(drm); in intel_plane_fb_max_stride() local
612 if (!HAS_DISPLAY(display)) in intel_plane_fb_max_stride()
620 crtc = intel_first_crtc(display); in intel_plane_fb_max_stride()
646 struct intel_display *display = to_intel_display(crtc_state); in intel_plane_fixup_bitmasks() local
657 drm_for_each_plane_mask(plane, display->drm, in intel_plane_fixup_bitmasks()
667 struct intel_display *display = to_intel_display(crtc); in intel_plane_disable_noatomic() local
673 drm_dbg_kms(display->drm, in intel_plane_disable_noatomic()
699 if (HAS_GMCH(display) && in intel_plane_disable_noatomic()
700 intel_set_memory_cxsr(display, false)) in intel_plane_disable_noatomic()
707 if (DISPLAY_VER(display) == 2 && !crtc_state->active_planes) in intel_plane_disable_noatomic()
708 intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, false); in intel_plane_disable_noatomic()
727 struct intel_display *display = to_intel_display(crtc_state); in icl_set_pipe_chicken() local
732 tmp = intel_de_read(display, PIPE_CHICKEN(pipe)); in icl_set_pipe_chicken()
735 * Display WA #1153: icl in icl_set_pipe_chicken()
741 * Display WA # 1605353570: icl in icl_set_pipe_chicken()
749 * Underrun recovery must always be disabled on display 13+. in icl_set_pipe_chicken()
752 if (display->platform.dg2) in icl_set_pipe_chicken()
754 else if ((DISPLAY_VER(display) >= 13) && (DISPLAY_VER(display) < 30)) in icl_set_pipe_chicken()
758 if (display->platform.dg2) in icl_set_pipe_chicken()
761 intel_de_write(display, PIPE_CHICKEN(pipe), tmp); in icl_set_pipe_chicken()
764 bool intel_has_pending_fb_unpin(struct intel_display *display) in intel_has_pending_fb_unpin() argument
769 drm_for_each_crtc(crtc, display->drm) { in intel_has_pending_fb_unpin()
833 struct intel_display *display = to_intel_display(crtc_state); in needs_nv12_wa() local
838 /* WA Display #0827: Gen9:all */ in needs_nv12_wa()
839 if (DISPLAY_VER(display) == 9) in needs_nv12_wa()
847 struct intel_display *display = to_intel_display(crtc_state); in needs_scalerclk_wa() local
850 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(display) == 11) in needs_scalerclk_wa()
858 struct intel_display *display = to_intel_display(crtc_state); in needs_cursorclk_wa() local
863 DISPLAY_VER(display) == 11) in needs_cursorclk_wa()
869 static void intel_async_flip_vtd_wa(struct intel_display *display, in intel_async_flip_vtd_wa() argument
872 if (DISPLAY_VER(display) == 9) { in intel_async_flip_vtd_wa()
877 intel_de_rmw(display, CHICKEN_PIPESL_1(pipe), in intel_async_flip_vtd_wa()
882 intel_de_rmw(display, CHICKEN_PIPESL_1(pipe), in intel_async_flip_vtd_wa()
890 struct intel_display *display = to_intel_display(crtc_state); in needs_async_flip_vtd_wa() local
894 (DISPLAY_VER(display) == 9 || display->platform.broadwell || in needs_async_flip_vtd_wa()
895 display->platform.haswell); in needs_async_flip_vtd_wa()
1046 struct intel_display *display = to_intel_display(state); in intel_post_plane_update() local
1053 intel_frontbuffer_flip(display, new_crtc_state->fb_bits); in intel_post_plane_update()
1056 intel_update_watermarks(display); in intel_post_plane_update()
1062 intel_async_flip_vtd_wa(display, pipe, false); in intel_post_plane_update()
1066 skl_wa_827(display, pipe, false); in intel_post_plane_update()
1070 icl_wa_scalerclkgating(display, pipe, false); in intel_post_plane_update()
1074 icl_wa_cursorclkgating(display, pipe, false); in intel_post_plane_update()
1172 struct intel_display *display = to_intel_display(state); in intel_pre_plane_update() local
1200 intel_async_flip_vtd_wa(display, pipe, true); in intel_pre_plane_update()
1202 /* Display WA 827 */ in intel_pre_plane_update()
1205 skl_wa_827(display, pipe, true); in intel_pre_plane_update()
1210 icl_wa_scalerclkgating(display, pipe, true); in intel_pre_plane_update()
1215 icl_wa_cursorclkgating(display, pipe, true); in intel_pre_plane_update()
1226 if (HAS_GMCH(display) && old_crtc_state->hw.active && in intel_pre_plane_update()
1227 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(display, false)) in intel_pre_plane_update()
1237 if (!HAS_GMCH(display) && old_crtc_state->hw.active && in intel_pre_plane_update()
1238 new_crtc_state->disable_cxsr && ilk_disable_cxsr(display)) in intel_pre_plane_update()
1262 intel_update_watermarks(display); in intel_pre_plane_update()
1273 if (DISPLAY_VER(display) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) in intel_pre_plane_update()
1274 intel_set_cpu_fifo_underrun_reporting(display, pipe, false); in intel_pre_plane_update()
1287 struct intel_display *display = to_intel_display(state); in intel_crtc_disable_planes() local
1309 intel_frontbuffer_flip(display, fb_bits); in intel_crtc_disable_planes()
1314 struct intel_display *display = to_intel_display(state); in intel_encoders_update_prepare() local
1323 if (display->dpll.mgr) { in intel_encoders_update_prepare()
1513 struct intel_display *display = to_intel_display(crtc); in ilk_crtc_enable() local
1518 if (drm_WARN_ON(display->drm, crtc->active)) in ilk_crtc_enable()
1531 intel_set_cpu_fifo_underrun_reporting(display, pipe, false); in ilk_crtc_enable()
1532 intel_set_pch_fifo_underrun_reporting(display, pipe, false); in ilk_crtc_enable()
1545 assert_fdi_tx_disabled(display, pipe); in ilk_crtc_enable()
1546 assert_fdi_rx_disabled(display, pipe); in ilk_crtc_enable()
1567 if (HAS_PCH_CPT(display)) in ilk_crtc_enable()
1580 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); in ilk_crtc_enable()
1581 intel_set_pch_fifo_underrun_reporting(display, pipe, true); in ilk_crtc_enable()
1584 /* Display WA #1180: WaDisableScalarClockGating: glk */
1587 struct intel_display *display = to_intel_display(crtc_state); in glk_need_scaler_clock_gating_wa() local
1589 return DISPLAY_VER(display) == 10 && crtc_state->pch_pfit.enabled; in glk_need_scaler_clock_gating_wa()
1594 struct intel_display *display = to_intel_display(crtc); in glk_pipe_scaler_clock_gating_wa() local
1597 intel_de_rmw(display, CLKGATE_DIS_PSL(crtc->pipe), in glk_pipe_scaler_clock_gating_wa()
1603 struct intel_display *display = to_intel_display(crtc_state); in hsw_set_linetime_wm() local
1606 intel_de_write(display, WM_LINETIME(crtc->pipe), in hsw_set_linetime_wm()
1613 struct intel_display *display = to_intel_display(crtc_state); in hsw_set_frame_start_delay() local
1615 intel_de_rmw(display, CHICKEN_TRANS(display, crtc_state->cpu_transcoder), in hsw_set_frame_start_delay()
1622 struct intel_display *display = to_intel_display(crtc_state); in hsw_configure_cpu_transcoder() local
1637 if (HAS_VRR(display)) in hsw_configure_cpu_transcoder()
1641 intel_de_write(display, TRANS_MULT(display, cpu_transcoder), in hsw_configure_cpu_transcoder()
1652 struct intel_display *display = to_intel_display(state); in hsw_crtc_enable() local
1659 if (drm_WARN_ON(display->drm, crtc->active)) in hsw_crtc_enable()
1661 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) in hsw_crtc_enable()
1662 intel_dmc_enable_pipe(display, pipe_crtc->pipe); in hsw_crtc_enable()
1671 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) { in hsw_crtc_enable()
1677 if (HAS_UNCOMPRESSED_JOINER(display)) in hsw_crtc_enable()
1682 if (DISPLAY_VER(display) >= 9 || display->platform.broadwell) in hsw_crtc_enable()
1689 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) { in hsw_crtc_enable()
1698 if (DISPLAY_VER(display) >= 9) in hsw_crtc_enable()
1711 if (DISPLAY_VER(display) >= 11) in hsw_crtc_enable()
1719 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) { in hsw_crtc_enable()
1734 if (display->platform.haswell && hsw_workaround_pipe != INVALID_PIPE) { in hsw_crtc_enable()
1736 intel_crtc_for_pipe(display, hsw_workaround_pipe); in hsw_crtc_enable()
1747 struct intel_display *display = to_intel_display(crtc); in ilk_crtc_disable() local
1757 intel_set_cpu_fifo_underrun_reporting(display, pipe, false); in ilk_crtc_disable()
1758 intel_set_pch_fifo_underrun_reporting(display, pipe, false); in ilk_crtc_disable()
1776 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); in ilk_crtc_disable()
1777 intel_set_pch_fifo_underrun_reporting(display, pipe, true); in ilk_crtc_disable()
1783 struct intel_display *display = to_intel_display(state); in hsw_crtc_disable() local
1800 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) in hsw_crtc_disable()
1801 intel_dmc_disable_pipe(display, pipe_crtc->pipe); in hsw_crtc_disable()
1805 bool intel_phy_is_combo(struct intel_display *display, enum phy phy) in intel_phy_is_combo() argument
1809 else if (display->platform.alderlake_s) in intel_phy_is_combo()
1811 else if (display->platform.dg1 || display->platform.rocketlake) in intel_phy_is_combo()
1813 else if (display->platform.jasperlake || display->platform.elkhartlake) in intel_phy_is_combo()
1815 else if (display->platform.alderlake_p || IS_DISPLAY_VER(display, 11, 12)) in intel_phy_is_combo()
1827 bool intel_phy_is_tc(struct intel_display *display, enum phy phy) in intel_phy_is_tc() argument
1833 if (display->platform.dgfx) in intel_phy_is_tc()
1836 if (DISPLAY_VER(display) >= 13) in intel_phy_is_tc()
1838 else if (display->platform.tigerlake) in intel_phy_is_tc()
1840 else if (display->platform.icelake) in intel_phy_is_tc()
1847 bool intel_phy_is_snps(struct intel_display *display, enum phy phy) in intel_phy_is_snps() argument
1853 return display->platform.dg2 && phy > PHY_NONE && phy <= PHY_E; in intel_phy_is_snps()
1857 enum phy intel_port_to_phy(struct intel_display *display, enum port port) in intel_port_to_phy() argument
1859 if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) in intel_port_to_phy()
1861 else if (DISPLAY_VER(display) >= 13 && port >= PORT_TC1) in intel_port_to_phy()
1863 else if (display->platform.alderlake_s && port >= PORT_TC1) in intel_port_to_phy()
1865 else if ((display->platform.dg1 || display->platform.rocketlake) && port >= PORT_TC1) in intel_port_to_phy()
1867 else if ((display->platform.jasperlake || display->platform.elkhartlake) && in intel_port_to_phy()
1875 enum tc_port intel_port_to_tc(struct intel_display *display, enum port port) in intel_port_to_tc() argument
1877 if (!intel_phy_is_tc(display, intel_port_to_phy(display, port))) in intel_port_to_tc()
1880 if (DISPLAY_VER(display) >= 12) in intel_port_to_tc()
1888 struct intel_display *display = to_intel_display(encoder); in intel_encoder_to_phy() local
1890 return intel_port_to_phy(display, encoder->port); in intel_encoder_to_phy()
1895 struct intel_display *display = to_intel_display(encoder); in intel_encoder_is_combo() local
1897 return intel_phy_is_combo(display, intel_encoder_to_phy(encoder)); in intel_encoder_is_combo()
1902 struct intel_display *display = to_intel_display(encoder); in intel_encoder_is_snps() local
1904 return intel_phy_is_snps(display, intel_encoder_to_phy(encoder)); in intel_encoder_is_snps()
1909 struct intel_display *display = to_intel_display(encoder); in intel_encoder_is_tc() local
1911 return intel_phy_is_tc(display, intel_encoder_to_phy(encoder)); in intel_encoder_is_tc()
1916 struct intel_display *display = to_intel_display(encoder); in intel_encoder_to_tc() local
1918 return intel_port_to_tc(display, encoder->port); in intel_encoder_to_tc()
1924 struct intel_display *display = to_intel_display(dig_port); in intel_aux_power_domain() local
1927 return intel_display_power_tbt_aux_domain(display, dig_port->aux_ch); in intel_aux_power_domain()
1929 return intel_display_power_legacy_aux_domain(display, dig_port->aux_ch); in intel_aux_power_domain()
1935 struct intel_display *display = to_intel_display(crtc_state); in get_crtc_power_domains() local
1952 drm_for_each_encoder_mask(encoder, display->drm, in get_crtc_power_domains()
1959 if (HAS_DDI(display) && crtc_state->has_audio) in get_crtc_power_domains()
1972 struct intel_display *display = to_intel_display(crtc_state); in intel_modeset_get_crtc_power_domains() local
1989 intel_display_power_get_in_set(display, in intel_modeset_get_crtc_power_domains()
1997 struct intel_display *display = to_intel_display(crtc); in intel_modeset_put_crtc_power_domains() local
1999 intel_display_power_put_mask_in_set(display, in intel_modeset_put_crtc_power_domains()
2024 struct intel_display *display = to_intel_display(crtc); in valleyview_crtc_enable() local
2029 if (drm_WARN_ON(display->drm, crtc->active)) in valleyview_crtc_enable()
2036 intel_de_write(display, VLV_PIPE_MSA_MISC(display, pipe), 0); in valleyview_crtc_enable()
2038 if (display->platform.cherryview && pipe == PIPE_B) { in valleyview_crtc_enable()
2039 intel_de_write(display, CHV_BLEND(display, pipe), in valleyview_crtc_enable()
2041 intel_de_write(display, CHV_CANVAS(display, pipe), 0); in valleyview_crtc_enable()
2046 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); in valleyview_crtc_enable()
2050 if (display->platform.cherryview) in valleyview_crtc_enable()
2072 struct intel_display *display = to_intel_display(crtc); in i9xx_crtc_enable() local
2077 if (drm_WARN_ON(display->drm, crtc->active)) in i9xx_crtc_enable()
2086 if (DISPLAY_VER(display) != 2) in i9xx_crtc_enable()
2087 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); in i9xx_crtc_enable()
2098 intel_update_watermarks(display); in i9xx_crtc_enable()
2106 if (DISPLAY_VER(display) == 2) in i9xx_crtc_enable()
2113 struct intel_display *display = to_intel_display(state); in i9xx_crtc_disable() local
2122 if (DISPLAY_VER(display) == 2) in i9xx_crtc_disable()
2136 if (display->platform.cherryview) in i9xx_crtc_disable()
2137 chv_disable_pll(display, pipe); in i9xx_crtc_disable()
2138 else if (display->platform.valleyview) in i9xx_crtc_disable()
2139 vlv_disable_pll(display, pipe); in i9xx_crtc_disable()
2146 if (DISPLAY_VER(display) != 2) in i9xx_crtc_disable()
2147 intel_set_cpu_fifo_underrun_reporting(display, pipe, false); in i9xx_crtc_disable()
2149 if (!display->funcs.wm->initial_watermarks) in i9xx_crtc_disable()
2150 intel_update_watermarks(display); in i9xx_crtc_disable()
2153 if (display->platform.i830) in i9xx_crtc_disable()
2154 i830_enable_pipe(display, pipe); in i9xx_crtc_disable()
2167 struct intel_display *display = to_intel_display(crtc); in intel_crtc_supports_double_wide() local
2170 return HAS_DOUBLE_WIDE(display) && in intel_crtc_supports_double_wide()
2171 (crtc->pipe == PIPE_A || display->platform.i915g); in intel_crtc_supports_double_wide()
2218 struct intel_display *display = to_intel_display(crtc_state); in intel_crtc_compute_pixel_rate() local
2220 if (HAS_GMCH(display)) in intel_crtc_compute_pixel_rate()
2331 struct intel_display *display = to_intel_display(crtc_state); in intel_crtc_compute_pipe_src() local
2344 drm_dbg_kms(display->drm, in intel_crtc_compute_pipe_src()
2351 intel_is_dual_link_lvds(display)) { in intel_crtc_compute_pipe_src()
2352 drm_dbg_kms(display->drm, in intel_crtc_compute_pipe_src()
2364 struct intel_display *display = to_intel_display(crtc_state); in intel_crtc_compute_pipe_mode() local
2368 int clock_limit = display->cdclk.max_dotclk_freq; in intel_crtc_compute_pipe_mode()
2383 if (DISPLAY_VER(display) < 4) { in intel_crtc_compute_pipe_mode()
2384 clock_limit = display->cdclk.max_cdclk_freq * 9 / 10; in intel_crtc_compute_pipe_mode()
2388 * is > 90% of the (display) core speed. in intel_crtc_compute_pipe_mode()
2392 clock_limit = display->cdclk.max_dotclk_freq; in intel_crtc_compute_pipe_mode()
2398 drm_dbg_kms(display->drm, in intel_crtc_compute_pipe_mode()
2411 struct intel_display *display = to_intel_display(crtc_state); in intel_crtc_vblank_delay() local
2414 if (!HAS_DSB(display)) in intel_crtc_vblank_delay()
2425 struct intel_display *display = to_intel_display(state); in intel_crtc_compute_vblank_delay() local
2436 drm_dbg_kms(display->drm, "[CRTC:%d:%s] vblank delay (%d) exceeds max (%d)\n", in intel_crtc_compute_vblank_delay()
2527 void intel_panel_sanitize_ssc(struct intel_display *display) in intel_panel_sanitize_ssc() argument
2535 if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display)) { in intel_panel_sanitize_ssc()
2536 bool bios_lvds_use_ssc = intel_de_read(display, in intel_panel_sanitize_ssc()
2540 if (display->vbt.lvds_use_ssc != bios_lvds_use_ssc) { in intel_panel_sanitize_ssc()
2541 drm_dbg_kms(display->drm, in intel_panel_sanitize_ssc()
2544 str_enabled_disabled(display->vbt.lvds_use_ssc)); in intel_panel_sanitize_ssc()
2545 display->vbt.lvds_use_ssc = bios_lvds_use_ssc; in intel_panel_sanitize_ssc()
2557 void intel_set_m_n(struct intel_display *display, in intel_set_m_n() argument
2562 intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); in intel_set_m_n()
2563 intel_de_write(display, data_n_reg, m_n->data_n); in intel_set_m_n()
2564 intel_de_write(display, link_m_reg, m_n->link_m); in intel_set_m_n()
2569 intel_de_write(display, link_n_reg, m_n->link_n); in intel_set_m_n()
2572 bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display, in intel_cpu_transcoder_has_m2_n2() argument
2575 if (display->platform.haswell) in intel_cpu_transcoder_has_m2_n2()
2578 return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview; in intel_cpu_transcoder_has_m2_n2()
2585 struct intel_display *display = to_intel_display(crtc); in intel_cpu_transcoder_set_m1_n1() local
2588 if (DISPLAY_VER(display) >= 5) in intel_cpu_transcoder_set_m1_n1()
2589 intel_set_m_n(display, m_n, in intel_cpu_transcoder_set_m1_n1()
2590 PIPE_DATA_M1(display, transcoder), in intel_cpu_transcoder_set_m1_n1()
2591 PIPE_DATA_N1(display, transcoder), in intel_cpu_transcoder_set_m1_n1()
2592 PIPE_LINK_M1(display, transcoder), in intel_cpu_transcoder_set_m1_n1()
2593 PIPE_LINK_N1(display, transcoder)); in intel_cpu_transcoder_set_m1_n1()
2595 intel_set_m_n(display, m_n, in intel_cpu_transcoder_set_m1_n1()
2604 struct intel_display *display = to_intel_display(crtc); in intel_cpu_transcoder_set_m2_n2() local
2606 if (!intel_cpu_transcoder_has_m2_n2(display, transcoder)) in intel_cpu_transcoder_set_m2_n2()
2609 intel_set_m_n(display, m_n, in intel_cpu_transcoder_set_m2_n2()
2610 PIPE_DATA_M2(display, transcoder), in intel_cpu_transcoder_set_m2_n2()
2611 PIPE_DATA_N2(display, transcoder), in intel_cpu_transcoder_set_m2_n2()
2612 PIPE_LINK_M2(display, transcoder), in intel_cpu_transcoder_set_m2_n2()
2613 PIPE_LINK_N2(display, transcoder)); in intel_cpu_transcoder_set_m2_n2()
2619 struct intel_display *display = to_intel_display(crtc_state); in transcoder_has_vrr() local
2622 return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder); in transcoder_has_vrr()
2627 struct intel_display *display = to_intel_display(crtc_state); in intel_set_transcoder_timings() local
2635 drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)); in intel_set_transcoder_timings()
2662 if (DISPLAY_VER(display) >= 13) { in intel_set_transcoder_timings()
2663 intel_de_write(display, in intel_set_transcoder_timings()
2664 TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder), in intel_set_transcoder_timings()
2674 if (DISPLAY_VER(display) >= 4) in intel_set_transcoder_timings()
2675 intel_de_write(display, in intel_set_transcoder_timings()
2676 TRANS_VSYNCSHIFT(display, cpu_transcoder), in intel_set_transcoder_timings()
2679 intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder), in intel_set_transcoder_timings()
2682 intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder), in intel_set_transcoder_timings()
2685 intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder), in intel_set_transcoder_timings()
2695 if (intel_vrr_always_use_vrr_tg(display)) in intel_set_transcoder_timings()
2698 intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), in intel_set_transcoder_timings()
2701 intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), in intel_set_transcoder_timings()
2704 intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder), in intel_set_transcoder_timings()
2712 if (display->platform.haswell && cpu_transcoder == TRANSCODER_EDP && in intel_set_transcoder_timings()
2714 intel_de_write(display, TRANS_VTOTAL(display, pipe), in intel_set_transcoder_timings()
2718 if (DISPLAY_VER(display) >= 30) { in intel_set_transcoder_timings()
2727 intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder), in intel_set_transcoder_timings()
2734 struct intel_display *display = to_intel_display(crtc_state); in intel_set_transcoder_timings_lrr() local
2739 drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)); in intel_set_transcoder_timings_lrr()
2752 if (DISPLAY_VER(display) >= 13) { in intel_set_transcoder_timings_lrr()
2753 intel_de_write(display, in intel_set_transcoder_timings_lrr()
2754 TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder), in intel_set_transcoder_timings_lrr()
2768 intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), in intel_set_transcoder_timings_lrr()
2777 if (intel_vrr_always_use_vrr_tg(display)) in intel_set_transcoder_timings_lrr()
2784 intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), in intel_set_transcoder_timings_lrr()
2794 struct intel_display *display = to_intel_display(crtc_state); in intel_set_pipe_src_size() local
2803 intel_de_write(display, PIPESRC(display, pipe), in intel_set_pipe_src_size()
2809 struct intel_display *display = to_intel_display(crtc_state); in intel_pipe_is_interlaced() local
2812 if (DISPLAY_VER(display) == 2) in intel_pipe_is_interlaced()
2815 if (DISPLAY_VER(display) >= 9 || in intel_pipe_is_interlaced()
2816 display->platform.broadwell || display->platform.haswell) in intel_pipe_is_interlaced()
2817 return intel_de_read(display, in intel_pipe_is_interlaced()
2818 TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW; in intel_pipe_is_interlaced()
2820 return intel_de_read(display, in intel_pipe_is_interlaced()
2821 TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK; in intel_pipe_is_interlaced()
2827 struct intel_display *display = to_intel_display(crtc); in intel_get_transcoder_timings() local
2832 tmp = intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder)); in intel_get_transcoder_timings()
2837 tmp = intel_de_read(display, in intel_get_transcoder_timings()
2838 TRANS_HBLANK(display, cpu_transcoder)); in intel_get_transcoder_timings()
2843 tmp = intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder)); in intel_get_transcoder_timings()
2847 tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder)); in intel_get_transcoder_timings()
2853 tmp = intel_de_read(display, in intel_get_transcoder_timings()
2854 TRANS_VBLANK(display, cpu_transcoder)); in intel_get_transcoder_timings()
2858 tmp = intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder)); in intel_get_transcoder_timings()
2868 if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder)) in intel_get_transcoder_timings()
2871 intel_de_read(display, in intel_get_transcoder_timings()
2872 TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder)); in intel_get_transcoder_timings()
2874 if (DISPLAY_VER(display) >= 30) in intel_get_transcoder_timings()
2875 pipe_config->min_hblank = intel_de_read(display, in intel_get_transcoder_timings()
2899 struct intel_display *display = to_intel_display(crtc); in intel_get_pipe_src_size() local
2902 tmp = intel_de_read(display, PIPESRC(display, crtc->pipe)); in intel_get_pipe_src_size()
2913 struct intel_display *display = to_intel_display(crtc_state); in i9xx_set_pipeconf() local
2922 if (display->platform.i830 || !intel_crtc_needs_modeset(crtc_state)) in i9xx_set_pipeconf()
2929 if (display->platform.g4x || display->platform.valleyview || in i9xx_set_pipeconf()
2930 display->platform.cherryview) { in i9xx_set_pipeconf()
2954 if (DISPLAY_VER(display) < 4 || in i9xx_set_pipeconf()
2963 if ((display->platform.valleyview || display->platform.cherryview) && in i9xx_set_pipeconf()
2974 intel_de_write(display, TRANSCONF(display, cpu_transcoder), val); in i9xx_set_pipeconf()
2975 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); in i9xx_set_pipeconf()
2981 struct intel_display *display = to_intel_display(crtc); in bdw_get_pipe_misc_output_format() local
2984 tmp = intel_de_read(display, PIPE_MISC(crtc->pipe)); in bdw_get_pipe_misc_output_format()
2992 if (DISPLAY_VER(display) < 30) in bdw_get_pipe_misc_output_format()
2993 drm_WARN_ON(display->drm, in bdw_get_pipe_misc_output_format()
3007 struct intel_display *display = to_intel_display(crtc); in i9xx_get_pipe_config() local
3015 wakeref = intel_display_power_get_if_enabled(display, power_domain); in i9xx_get_pipe_config()
3019 tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); in i9xx_get_pipe_config()
3028 if (display->platform.g4x || display->platform.valleyview || in i9xx_get_pipe_config()
3029 display->platform.cherryview) { in i9xx_get_pipe_config()
3046 if ((display->platform.valleyview || display->platform.cherryview) && in i9xx_get_pipe_config()
3054 if ((display->platform.valleyview || display->platform.cherryview) && in i9xx_get_pipe_config()
3060 if (HAS_DOUBLE_WIDE(display)) in i9xx_get_pipe_config()
3070 if (DISPLAY_VER(display) >= 4) { in i9xx_get_pipe_config()
3075 } else if (display->platform.i945g || display->platform.i945gm || in i9xx_get_pipe_config()
3076 display->platform.g33 || display->platform.pineview) { in i9xx_get_pipe_config()
3088 if (display->platform.cherryview) in i9xx_get_pipe_config()
3090 else if (display->platform.valleyview) in i9xx_get_pipe_config()
3106 intel_display_power_put(display, power_domain, wakeref); in i9xx_get_pipe_config()
3113 struct intel_display *display = to_intel_display(crtc_state); in ilk_set_pipeconf() local
3153 * the entire display. Make sure we don't do it. in ilk_set_pipeconf()
3155 drm_WARN_ON(display->drm, crtc_state->limited_color_range && in ilk_set_pipeconf()
3170 intel_de_write(display, TRANSCONF(display, cpu_transcoder), val); in ilk_set_pipeconf()
3171 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); in ilk_set_pipeconf()
3176 struct intel_display *display = to_intel_display(crtc_state); in hsw_set_transconf() local
3187 if (display->platform.haswell && crtc_state->dither) in hsw_set_transconf()
3195 if (display->platform.haswell && in hsw_set_transconf()
3199 intel_de_write(display, TRANSCONF(display, cpu_transcoder), val); in hsw_set_transconf()
3200 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); in hsw_set_transconf()
3206 struct intel_display *display = to_intel_display(crtc_state); in bdw_set_pipe_misc() local
3222 if (DISPLAY_VER(display) >= 13) in bdw_set_pipe_misc()
3238 val |= DISPLAY_VER(display) >= 30 ? PIPE_MISC_YUV420_ENABLE : in bdw_set_pipe_misc()
3241 if (DISPLAY_VER(display) >= 11 && is_hdr_mode(crtc_state)) in bdw_set_pipe_misc()
3244 if (DISPLAY_VER(display) >= 12) in bdw_set_pipe_misc()
3248 if (display->platform.broadwell) in bdw_set_pipe_misc()
3251 intel_de_write_dsb(display, dsb, PIPE_MISC(crtc->pipe), val); in bdw_set_pipe_misc()
3256 struct intel_display *display = to_intel_display(crtc); in bdw_get_pipe_misc_bpp() local
3259 tmp = intel_de_read(display, PIPE_MISC(crtc->pipe)); in bdw_get_pipe_misc_bpp()
3279 if (DISPLAY_VER(display) >= 13) in bdw_get_pipe_misc_bpp()
3299 void intel_get_m_n(struct intel_display *display, in intel_get_m_n() argument
3304 m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK; in intel_get_m_n()
3305 m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK; in intel_get_m_n()
3306 m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK; in intel_get_m_n()
3307 m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK; in intel_get_m_n()
3308 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1; in intel_get_m_n()
3315 struct intel_display *display = to_intel_display(crtc); in intel_cpu_transcoder_get_m1_n1() local
3318 if (DISPLAY_VER(display) >= 5) in intel_cpu_transcoder_get_m1_n1()
3319 intel_get_m_n(display, m_n, in intel_cpu_transcoder_get_m1_n1()
3320 PIPE_DATA_M1(display, transcoder), in intel_cpu_transcoder_get_m1_n1()
3321 PIPE_DATA_N1(display, transcoder), in intel_cpu_transcoder_get_m1_n1()
3322 PIPE_LINK_M1(display, transcoder), in intel_cpu_transcoder_get_m1_n1()
3323 PIPE_LINK_N1(display, transcoder)); in intel_cpu_transcoder_get_m1_n1()
3325 intel_get_m_n(display, m_n, in intel_cpu_transcoder_get_m1_n1()
3334 struct intel_display *display = to_intel_display(crtc); in intel_cpu_transcoder_get_m2_n2() local
3336 if (!intel_cpu_transcoder_has_m2_n2(display, transcoder)) in intel_cpu_transcoder_get_m2_n2()
3339 intel_get_m_n(display, m_n, in intel_cpu_transcoder_get_m2_n2()
3340 PIPE_DATA_M2(display, transcoder), in intel_cpu_transcoder_get_m2_n2()
3341 PIPE_DATA_N2(display, transcoder), in intel_cpu_transcoder_get_m2_n2()
3342 PIPE_LINK_M2(display, transcoder), in intel_cpu_transcoder_get_m2_n2()
3343 PIPE_LINK_N2(display, transcoder)); in intel_cpu_transcoder_get_m2_n2()
3349 struct intel_display *display = to_intel_display(crtc); in ilk_get_pipe_config() local
3357 wakeref = intel_display_power_get_if_enabled(display, power_domain); in ilk_get_pipe_config()
3361 tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); in ilk_get_pipe_config()
3419 intel_display_power_put(display, power_domain, wakeref); in ilk_get_pipe_config()
3424 static u8 joiner_pipes(struct intel_display *display) in joiner_pipes() argument
3428 if (DISPLAY_VER(display) >= 12) in joiner_pipes()
3430 else if (DISPLAY_VER(display) >= 11) in joiner_pipes()
3435 return pipes & DISPLAY_RUNTIME_INFO(display)->pipe_mask; in joiner_pipes()
3438 static bool transcoder_ddi_func_is_enabled(struct intel_display *display, in transcoder_ddi_func_is_enabled() argument
3447 with_intel_display_power_if_enabled(display, power_domain, wakeref) in transcoder_ddi_func_is_enabled()
3448 tmp = intel_de_read(display, in transcoder_ddi_func_is_enabled()
3449 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); in transcoder_ddi_func_is_enabled()
3454 static void enabled_uncompressed_joiner_pipes(struct intel_display *display, in enabled_uncompressed_joiner_pipes() argument
3462 if (!HAS_UNCOMPRESSED_JOINER(display)) in enabled_uncompressed_joiner_pipes()
3465 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, in enabled_uncompressed_joiner_pipes()
3466 joiner_pipes(display)) { in enabled_uncompressed_joiner_pipes()
3472 with_intel_display_power_if_enabled(display, power_domain, wakeref) { in enabled_uncompressed_joiner_pipes()
3473 u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); in enabled_uncompressed_joiner_pipes()
3483 static void enabled_bigjoiner_pipes(struct intel_display *display, in enabled_bigjoiner_pipes() argument
3491 if (!HAS_BIGJOINER(display)) in enabled_bigjoiner_pipes()
3494 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, in enabled_bigjoiner_pipes()
3495 joiner_pipes(display)) { in enabled_bigjoiner_pipes()
3501 with_intel_display_power_if_enabled(display, power_domain, wakeref) { in enabled_bigjoiner_pipes()
3502 u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); in enabled_bigjoiner_pipes()
3553 static void enabled_ultrajoiner_pipes(struct intel_display *display, in enabled_ultrajoiner_pipes() argument
3561 if (!HAS_ULTRAJOINER(display)) in enabled_ultrajoiner_pipes()
3564 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, in enabled_ultrajoiner_pipes()
3565 joiner_pipes(display)) { in enabled_ultrajoiner_pipes()
3571 with_intel_display_power_if_enabled(display, power_domain, wakeref) { in enabled_ultrajoiner_pipes()
3572 u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); in enabled_ultrajoiner_pipes()
3585 static void enabled_joiner_pipes(struct intel_display *display, in enabled_joiner_pipes() argument
3596 enabled_ultrajoiner_pipes(display, &primary_ultrajoiner_pipes, in enabled_joiner_pipes()
3603 drm_WARN_ON(display->drm, in enabled_joiner_pipes()
3610 drm_WARN_ON(display->drm, (primary_ultrajoiner_pipes & secondary_ultrajoiner_pipes) != 0); in enabled_joiner_pipes()
3612 enabled_uncompressed_joiner_pipes(display, &primary_uncompressed_joiner_pipes, in enabled_joiner_pipes()
3615 drm_WARN_ON(display->drm, in enabled_joiner_pipes()
3618 enabled_bigjoiner_pipes(display, &primary_bigjoiner_pipes, in enabled_joiner_pipes()
3621 drm_WARN_ON(display->drm, in enabled_joiner_pipes()
3629 drm_WARN(display->drm, (ultrajoiner_pipes & bigjoiner_pipes) != ultrajoiner_pipes, in enabled_joiner_pipes()
3633 drm_WARN(display->drm, secondary_ultrajoiner_pipes != in enabled_joiner_pipes()
3639 drm_WARN(display->drm, (uncompressed_joiner_pipes & bigjoiner_pipes) != 0, in enabled_joiner_pipes()
3643 drm_WARN(display->drm, secondary_bigjoiner_pipes != in enabled_joiner_pipes()
3649 drm_WARN(display->drm, secondary_uncompressed_joiner_pipes != in enabled_joiner_pipes()
3663 drm_WARN(display->drm, in enabled_joiner_pipes()
3678 drm_WARN(display->drm, in enabled_joiner_pipes()
3693 drm_WARN(display->drm, in enabled_joiner_pipes()
3704 static u8 hsw_panel_transcoders(struct intel_display *display) in hsw_panel_transcoders() argument
3708 if (DISPLAY_VER(display) >= 11) in hsw_panel_transcoders()
3716 struct intel_display *display = to_intel_display(crtc); in hsw_enabled_transcoders() local
3717 u8 panel_transcoder_mask = hsw_panel_transcoders(display); in hsw_enabled_transcoders()
3726 for_each_cpu_transcoder_masked(display, cpu_transcoder, in hsw_enabled_transcoders()
3734 with_intel_display_power_if_enabled(display, power_domain, wakeref) in hsw_enabled_transcoders()
3735 tmp = intel_de_read(display, in hsw_enabled_transcoders()
3736 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); in hsw_enabled_transcoders()
3743 drm_WARN(display->drm, 1, in hsw_enabled_transcoders()
3768 if (transcoder_ddi_func_is_enabled(display, cpu_transcoder)) in hsw_enabled_transcoders()
3772 enabled_joiner_pipes(display, crtc->pipe, &primary_pipe, &secondary_pipes); in hsw_enabled_transcoders()
3775 if (transcoder_ddi_func_is_enabled(display, cpu_transcoder)) in hsw_enabled_transcoders()
3800 static void assert_enabled_transcoders(struct intel_display *display, in assert_enabled_transcoders() argument
3804 drm_WARN_ON(display->drm, in assert_enabled_transcoders()
3810 drm_WARN_ON(display->drm, in assert_enabled_transcoders()
3819 struct intel_display *display = to_intel_display(crtc); in hsw_get_transcoder_state() local
3827 assert_enabled_transcoders(display, enabled_transcoders); in hsw_get_transcoder_state()
3836 if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set, in hsw_get_transcoder_state()
3840 if (hsw_panel_transcoders(display) & BIT(pipe_config->cpu_transcoder)) { in hsw_get_transcoder_state()
3841 tmp = intel_de_read(display, in hsw_get_transcoder_state()
3842 TRANS_DDI_FUNC_CTL(display, pipe_config->cpu_transcoder)); in hsw_get_transcoder_state()
3848 tmp = intel_de_read(display, in hsw_get_transcoder_state()
3849 TRANSCONF(display, pipe_config->cpu_transcoder)); in hsw_get_transcoder_state()
3858 struct intel_display *display = to_intel_display(crtc); in bxt_get_dsi_transcoder_state() local
3869 if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set, in bxt_get_dsi_transcoder_state()
3876 * the machine. See BSpec North Display Engine in bxt_get_dsi_transcoder_state()
3880 if (!bxt_dsi_pll_is_enabled(display)) in bxt_get_dsi_transcoder_state()
3884 tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port)); in bxt_get_dsi_transcoder_state()
3888 tmp = intel_de_read(display, MIPI_CTRL(display, port)); in bxt_get_dsi_transcoder_state()
3901 struct intel_display *display = to_intel_display(crtc_state); in intel_joiner_get_config() local
3906 enabled_joiner_pipes(display, pipe, &primary_pipe, &secondary_pipes); in intel_joiner_get_config()
3917 struct intel_display *display = to_intel_display(crtc); in hsw_get_pipe_config() local
3921 if (!intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains, in hsw_get_pipe_config()
3927 if ((display->platform.geminilake || display->platform.broxton) && in hsw_get_pipe_config()
3929 drm_WARN_ON(display->drm, active); in hsw_get_pipe_config()
3940 DISPLAY_VER(display) >= 11) in hsw_get_pipe_config()
3948 if (display->platform.haswell) { in hsw_get_pipe_config()
3949 u32 tmp = intel_de_read(display, in hsw_get_pipe_config()
3950 TRANSCONF(display, pipe_config->cpu_transcoder)); in hsw_get_pipe_config()
3965 tmp = intel_de_read(display, WM_LINETIME(crtc->pipe)); in hsw_get_pipe_config()
3967 if (display->platform.broadwell || display->platform.haswell) in hsw_get_pipe_config()
3971 if (intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains, in hsw_get_pipe_config()
3973 if (DISPLAY_VER(display) >= 9) in hsw_get_pipe_config()
3984 intel_de_read(display, in hsw_get_pipe_config()
3985 TRANS_MULT(display, pipe_config->cpu_transcoder)) + 1; in hsw_get_pipe_config()
3991 tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder)); in hsw_get_pipe_config()
4000 intel_display_power_put_all_in_set(display, &crtc->hw_readout_power_domains); in hsw_get_pipe_config()
4007 struct intel_display *display = to_intel_display(crtc_state); in intel_crtc_get_pipe_config() local
4010 if (!display->funcs.display->get_pipe_config(crtc, crtc_state)) in intel_crtc_get_pipe_config()
4070 struct intel_display *display = to_intel_display(encoder); in intel_encoder_current_mode() local
4079 crtc = intel_crtc_for_pipe(display, pipe); in intel_encoder_current_mode()
4169 struct intel_display *display = to_intel_display(crtc_state); in skl_linetime_wm() local
4180 /* Display WA #1135: BXT:ALL GLK:ALL */ in skl_linetime_wm()
4181 if ((display->platform.geminilake || display->platform.broxton) && in skl_linetime_wm()
4182 skl_watermark_ipc_enabled(display)) in skl_linetime_wm()
4191 struct intel_display *display = to_intel_display(state); in hsw_compute_linetime_wm() local
4196 if (DISPLAY_VER(display) >= 9) in hsw_compute_linetime_wm()
4217 struct intel_display *display = to_intel_display(crtc); in intel_crtc_atomic_check() local
4222 if (DISPLAY_VER(display) < 5 && !display->platform.g4x && in intel_crtc_atomic_check()
4239 drm_dbg_kms(display->drm, in intel_crtc_atomic_check()
4245 if (DISPLAY_VER(display) >= 9) { in intel_crtc_atomic_check()
4258 if (HAS_IPS(display)) { in intel_crtc_atomic_check()
4264 if (DISPLAY_VER(display) >= 9 || in intel_crtc_atomic_check()
4265 display->platform.broadwell || display->platform.haswell) { in intel_crtc_atomic_check()
4283 struct intel_display *display = to_intel_display(crtc_state); in compute_sink_pipe_bpp() local
4307 drm_dbg_kms(display->drm, in compute_sink_pipe_bpp()
4308 "[CONNECTOR:%d:%s] Limiting display bpp to %d " in compute_sink_pipe_bpp()
4325 struct intel_display *display = to_intel_display(crtc); in compute_baseline_pipe_bpp() local
4332 if (display->platform.g4x || display->platform.valleyview || in compute_baseline_pipe_bpp()
4333 display->platform.cherryview) in compute_baseline_pipe_bpp()
4335 else if (DISPLAY_VER(display) >= 5) in compute_baseline_pipe_bpp()
4342 /* Clamp display bpp to connector max bpp */ in compute_baseline_pipe_bpp()
4359 struct intel_display *display = to_intel_display(state); in check_digital_port_conflicts() local
4370 drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex); in check_digital_port_conflicts()
4377 drm_connector_list_iter_begin(display->drm, &conn_iter); in check_digital_port_conflicts()
4393 drm_WARN_ON(display->drm, !connector_state->crtc); in check_digital_port_conflicts()
4397 if (drm_WARN_ON(display->drm, !HAS_DDI(display))) in check_digital_port_conflicts()
4545 struct intel_display *display = to_intel_display(state); in intel_crtc_prepare_cleared_state() local
4572 if (display->platform.g4x || in intel_crtc_prepare_cleared_state()
4573 display->platform.valleyview || display->platform.cherryview) in intel_crtc_prepare_cleared_state()
4589 struct intel_display *display = to_intel_display(crtc); in intel_modeset_pipe_config() local
4622 drm_dbg_kms(display->drm, in intel_modeset_pipe_config()
4652 drm_dbg_kms(display->drm, in intel_modeset_pipe_config()
4694 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] config failure: %d\n", in intel_modeset_pipe_config()
4710 drm_dbg_kms(display->drm, "[CRTC:%d:%s] config failure: %d\n", in intel_modeset_pipe_config()
4721 drm_dbg_kms(display->drm, in intel_modeset_pipe_config()
4853 struct intel_display *display = to_intel_display(crtc); in pipe_config_infoframe_mismatch() local
4868 hdmi_infoframe_log(loglevel, display->drm->dev, a); in pipe_config_infoframe_mismatch()
4870 hdmi_infoframe_log(loglevel, display->drm->dev, b); in pipe_config_infoframe_mismatch()
4939 struct intel_display *display = to_intel_display(crtc); in pipe_config_pll_mismatch() local
4944 intel_dpll_dump_hw_state(display, p, a); in pipe_config_pll_mismatch()
4946 intel_dpll_dump_hw_state(display, p, b); in pipe_config_pll_mismatch()
4956 struct intel_display *display = to_intel_display(crtc); in pipe_config_cx0pll_mismatch() local
4962 intel_cx0pll_dump_hw_state(display, a); in pipe_config_cx0pll_mismatch()
4964 intel_cx0pll_dump_hw_state(display, b); in pipe_config_cx0pll_mismatch()
4969 struct intel_display *display = to_intel_display(old_crtc_state); in allow_vblank_delay_fastset() local
4976 return HAS_LRR(display) && old_crtc_state->inherited && in allow_vblank_delay_fastset()
4985 struct intel_display *display = to_intel_display(current_config); in intel_pipe_config_compare() local
4992 p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL); in intel_pipe_config_compare()
4994 p = drm_err_printer(display->drm, NULL); in intel_pipe_config_compare()
5085 if (!intel_dpll_compare_hw_state(display, ¤t_config->name, \ in intel_pipe_config_compare()
5229 if (HAS_DOUBLE_BUFFERED_M_N(display)) { in intel_pipe_config_compare()
5263 if ((DISPLAY_VER(display) < 8 && !display->platform.haswell) || in intel_pipe_config_compare()
5264 display->platform.valleyview || display->platform.cherryview) in intel_pipe_config_compare()
5280 if (DISPLAY_VER(display) < 4) in intel_pipe_config_compare()
5300 if (display->platform.cherryview) in intel_pipe_config_compare()
5320 if (display->dpll.mgr) in intel_pipe_config_compare()
5324 if (display->dpll.mgr || HAS_GMCH(display)) in intel_pipe_config_compare()
5328 if (DISPLAY_VER(display) >= 14) in intel_pipe_config_compare()
5334 if (display->platform.g4x || DISPLAY_VER(display) >= 5) in intel_pipe_config_compare()
5417 if (!fastset || intel_vrr_always_use_vrr_tg(display)) { in intel_pipe_config_compare()
5453 struct intel_display *display = to_intel_display(state); in intel_modeset_pipe() local
5457 drm_dbg_kms(display->drm, "[CRTC:%d:%s] Full modeset due to %s\n", in intel_modeset_pipe()
5497 struct intel_display *display = to_intel_display(state); in intel_modeset_pipes_in_mask_early() local
5500 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, mask) { in intel_modeset_pipes_in_mask_early()
5544 struct intel_display *display = to_intel_display(state); in intel_modeset_all_pipes_late() local
5547 for_each_intel_crtc(display->drm, crtc) { in intel_modeset_all_pipes_late()
5573 int intel_modeset_commit_pipes(struct intel_display *display, in intel_modeset_commit_pipes() argument
5581 state = drm_atomic_state_alloc(display->drm); in intel_modeset_commit_pipes()
5588 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) { in intel_modeset_commit_pipes()
5687 struct intel_display *display = to_intel_display(state); in intel_modeset_checks() local
5691 if (display->platform.haswell) in intel_modeset_checks()
5708 struct intel_display *display = to_intel_display(new_crtc_state); in intel_crtc_check_fastset() local
5716 drm_dbg_kms(display->drm, "[CRTC:%d:%s] fastset requirement not met, forcing full modeset\n", in intel_crtc_check_fastset()
5740 struct intel_display *display = to_intel_display(state); in intel_atomic_check_crtcs() local
5750 drm_dbg_atomic(display->drm, in intel_atomic_check_crtcs()
5797 struct intel_display *display = to_intel_display(state); in intel_atomic_check_joiner() local
5806 if (drm_WARN_ON(display->drm, in intel_atomic_check_joiner()
5810 if (primary_crtc_state->joiner_pipes & ~joiner_pipes(display)) { in intel_atomic_check_joiner()
5811 drm_dbg_kms(display->drm, in intel_atomic_check_joiner()
5815 primary_crtc_state->joiner_pipes, joiner_pipes(display)); in intel_atomic_check_joiner()
5819 for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc, in intel_atomic_check_joiner()
5830 drm_dbg_kms(display->drm, in intel_atomic_check_joiner()
5849 drm_dbg_kms(display->drm, in intel_atomic_check_joiner()
5868 struct intel_display *display = to_intel_display(state); in kill_joiner_secondaries() local
5873 for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc, in kill_joiner_secondaries()
5907 struct intel_display *display = to_intel_display(state); in intel_async_flip_check_uapi() local
5919 drm_dbg_kms(display->drm, in intel_async_flip_check_uapi()
5926 drm_dbg_kms(display->drm, in intel_async_flip_check_uapi()
5937 drm_dbg_kms(display->drm, in intel_async_flip_check_uapi()
5956 drm_dbg_kms(display->drm, in intel_async_flip_check_uapi()
5963 drm_dbg_kms(display->drm, in intel_async_flip_check_uapi()
5975 struct intel_display *display = to_intel_display(state); in intel_async_flip_check_hw() local
5988 drm_dbg_kms(display->drm, in intel_async_flip_check_hw()
5995 drm_dbg_kms(display->drm, in intel_async_flip_check_hw()
6002 drm_dbg_kms(display->drm, in intel_async_flip_check_hw()
6018 if (drm_WARN_ON(display->drm, in intel_async_flip_check_hw()
6035 drm_dbg_kms(display->drm, in intel_async_flip_check_hw()
6052 drm_dbg_kms(display->drm, in intel_async_flip_check_hw()
6060 drm_dbg_kms(display->drm, in intel_async_flip_check_hw()
6068 drm_dbg_kms(display->drm, in intel_async_flip_check_hw()
6076 drm_dbg_kms(display->drm, in intel_async_flip_check_hw()
6084 drm_dbg_kms(display->drm, in intel_async_flip_check_hw()
6092 drm_dbg_kms(display->drm, in intel_async_flip_check_hw()
6099 drm_dbg_kms(display->drm, in intel_async_flip_check_hw()
6107 drm_dbg_kms(display->drm, in intel_async_flip_check_hw()
6114 drm_dbg_kms(display->drm, in intel_async_flip_check_hw()
6121 drm_dbg_kms(display->drm, in intel_async_flip_check_hw()
6129 drm_dbg_kms(display->drm, in intel_async_flip_check_hw()
6141 struct intel_display *display = to_intel_display(state); in intel_joiner_add_affected_crtcs() local
6172 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, affected_pipes) { in intel_joiner_add_affected_crtcs()
6178 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, modeset_pipes) { in intel_joiner_add_affected_crtcs()
6208 struct intel_display *display = to_intel_display(state); in intel_atomic_check_config() local
6233 if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state))) in intel_atomic_check_config()
6252 if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state))) in intel_atomic_check_config()
6316 struct intel_display *display = to_intel_display(dev); in intel_atomic_check() local
6323 if (!intel_display_driver_check_access(display)) in intel_atomic_check()
6364 drm_WARN_ON(display->drm, new_crtc_state->uapi.enable); in intel_atomic_check()
6435 drm_dbg_kms(display->drm, in intel_atomic_check()
6491 drm_WARN_ON(display->drm, in intel_atomic_check()
6535 struct intel_display *display = to_intel_display(crtc); in intel_crtc_arm_fifo_underrun() local
6537 if (DISPLAY_VER(display) != 2 || crtc_state->active_planes) in intel_crtc_arm_fifo_underrun()
6538 intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true); in intel_crtc_arm_fifo_underrun()
6544 intel_set_pch_fifo_underrun_reporting(display, pch_transcoder, true); in intel_crtc_arm_fifo_underrun()
6551 struct intel_display *display = to_intel_display(new_crtc_state); in intel_pipe_fastset() local
6565 if (DISPLAY_VER(display) >= 9) { in intel_pipe_fastset()
6568 } else if (HAS_PCH_SPLIT(display)) { in intel_pipe_fastset()
6583 if (DISPLAY_VER(display) >= 9 || in intel_pipe_fastset()
6584 display->platform.broadwell || display->platform.haswell) in intel_pipe_fastset()
6598 struct intel_display *display = to_intel_display(state); in commit_pipe_pre_planes() local
6605 drm_WARN_ON(display->drm, new_crtc_state->use_dsb); in commit_pipe_pre_planes()
6615 if (DISPLAY_VER(display) >= 9 || display->platform.broadwell) in commit_pipe_pre_planes()
6630 struct intel_display *display = to_intel_display(state); in commit_pipe_post_planes() local
6634 drm_WARN_ON(display->drm, new_crtc_state->use_dsb); in commit_pipe_post_planes()
6641 if (DISPLAY_VER(display) >= 9 && in commit_pipe_post_planes()
6652 struct intel_display *display = to_intel_display(state); in intel_enable_crtc() local
6660 for_each_intel_crtc_in_pipe_mask_reverse(display->drm, pipe_crtc, in intel_enable_crtc()
6671 display->funcs.display->crtc_enable(state, crtc); in intel_enable_crtc()
6680 struct intel_display *display = to_intel_display(state); in intel_pre_update_crtc() local
6689 if (HAS_DPT(display)) in intel_pre_update_crtc()
6703 if (DISPLAY_VER(display) >= 11 && in intel_pre_update_crtc()
6714 drm_WARN_ON(display->drm, !intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF)); in intel_pre_update_crtc()
6777 struct intel_display *display = to_intel_display(state); in intel_old_crtc_state_disables() local
6786 for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, in intel_old_crtc_state_disables()
6792 display->funcs.display->crtc_disable(state, crtc); in intel_old_crtc_state_disables()
6794 for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, in intel_old_crtc_state_disables()
6809 struct intel_display *display = to_intel_display(state); in intel_commit_modeset_disables() local
6876 drm_WARN_ON(display->drm, disable_pipes); in intel_commit_modeset_disables()
6903 struct intel_display *display = to_intel_display(state); in skl_commit_modeset_enables() local
7045 drm_WARN_ON(display->drm, in skl_commit_modeset_enables()
7055 drm_WARN_ON(display->drm, modeset_pipes); in skl_commit_modeset_enables()
7056 drm_WARN_ON(display->drm, update_pipes); in skl_commit_modeset_enables()
7101 struct intel_display *display = to_intel_display(state); in intel_atomic_cleanup_work() local
7109 drm_atomic_helper_cleanup_planes(display->drm, &state->base); in intel_atomic_cleanup_work()
7116 struct intel_display *display = to_intel_display(state); in intel_atomic_prepare_plane_clear_colors() local
7140 * - 8 bytes native color value used by the display in intel_atomic_prepare_plane_clear_colors()
7153 drm_WARN_ON(display->drm, ret); in intel_atomic_prepare_plane_clear_colors()
7160 struct intel_display *display = to_intel_display(state); in intel_atomic_dsb_prepare() local
7173 (DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) && in intel_atomic_dsb_prepare()
7183 struct intel_display *display = to_intel_display(state); in intel_atomic_dsb_finish() local
7230 if (DISPLAY_VER(display) >= 9) in intel_atomic_dsb_finish()
7253 struct intel_display *display = to_intel_display(state); in intel_atomic_commit_tail() local
7254 struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm); in intel_atomic_commit_tail()
7266 intel_td_flush(display); in intel_atomic_commit_tail()
7307 wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF); in intel_atomic_commit_tail()
7333 drm_atomic_helper_update_legacy_modeset_state(display->drm, &state->base); in intel_atomic_commit_tail()
7348 spin_lock_irq(&display->drm->event_lock); in intel_atomic_commit_tail()
7351 spin_unlock_irq(&display->drm->event_lock); in intel_atomic_commit_tail()
7367 display->funcs.display->commit_modeset_enables(state); in intel_atomic_commit_tail()
7382 drm_atomic_helper_wait_for_flip_done(display->drm, &state->base); in intel_atomic_commit_tail()
7411 if (DISPLAY_VER(display) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) in intel_atomic_commit_tail()
7412 intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true); in intel_atomic_commit_tail()
7440 intel_check_cpu_fifo_underruns(display); in intel_atomic_commit_tail()
7441 intel_check_pch_fifo_underruns(display); in intel_atomic_commit_tail()
7467 intel_display_power_put_async_delay(display, POWER_DOMAIN_DC_OFF, wakeref, 17); in intel_atomic_commit_tail()
7468 intel_display_rpm_put(display, state->wakeref); in intel_atomic_commit_tail()
7479 queue_work(display->wq.cleanup, &state->cleanup_work); in intel_atomic_commit_tail()
7538 struct intel_display *display = to_intel_display(dev); in intel_atomic_commit() local
7542 state->wakeref = intel_display_rpm_get(display); in intel_atomic_commit()
7561 if (DISPLAY_VER(display) < 9 && state->base.legacy_cursor_update) { in intel_atomic_commit()
7574 drm_dbg_atomic(display->drm, in intel_atomic_commit()
7576 intel_display_rpm_put(display, state->wakeref); in intel_atomic_commit()
7586 intel_display_rpm_put(display, state->wakeref); in intel_atomic_commit()
7594 queue_work(display->wq.modeset, &state->base.commit_work); in intel_atomic_commit()
7596 queue_work(display->wq.flip, &state->base.commit_work); in intel_atomic_commit()
7599 flush_workqueue(display->wq.modeset); in intel_atomic_commit()
7608 struct intel_display *display = to_intel_display(encoder); in intel_encoder_possible_clones() local
7612 for_each_intel_encoder(display->drm, source_encoder) { in intel_encoder_possible_clones()
7622 struct intel_display *display = to_intel_display(encoder); in intel_encoder_possible_crtcs() local
7626 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, encoder->pipe_mask) in intel_encoder_possible_crtcs()
7632 static bool ilk_has_edp_a(struct intel_display *display) in ilk_has_edp_a() argument
7634 if (!display->platform.mobile) in ilk_has_edp_a()
7637 if ((intel_de_read(display, DP_A) & DP_DETECTED) == 0) in ilk_has_edp_a()
7640 if (display->platform.ironlake && (intel_de_read(display, FUSE_STRAP) & ILK_eDP_A_DISABLE)) in ilk_has_edp_a()
7646 static bool intel_ddi_crt_present(struct intel_display *display) in intel_ddi_crt_present() argument
7648 if (DISPLAY_VER(display) >= 9) in intel_ddi_crt_present()
7651 if (display->platform.haswell_ult || display->platform.broadwell_ult) in intel_ddi_crt_present()
7654 if (HAS_PCH_LPT_H(display) && in intel_ddi_crt_present()
7655 intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) in intel_ddi_crt_present()
7659 if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) in intel_ddi_crt_present()
7662 if (!display->vbt.int_crt_support) in intel_ddi_crt_present()
7668 bool assert_port_valid(struct intel_display *display, enum port port) in assert_port_valid() argument
7670 return !drm_WARN(display->drm, !(DISPLAY_RUNTIME_INFO(display)->port_mask & BIT(port)), in assert_port_valid()
7674 void intel_setup_outputs(struct intel_display *display) in intel_setup_outputs() argument
7679 intel_pps_unlock_regs_wa(display); in intel_setup_outputs()
7681 if (!HAS_DISPLAY(display)) in intel_setup_outputs()
7684 if (HAS_DDI(display)) { in intel_setup_outputs()
7685 if (intel_ddi_crt_present(display)) in intel_setup_outputs()
7686 intel_crt_init(display); in intel_setup_outputs()
7688 intel_bios_for_each_encoder(display, intel_ddi_init); in intel_setup_outputs()
7690 if (display->platform.geminilake || display->platform.broxton) in intel_setup_outputs()
7691 vlv_dsi_init(display); in intel_setup_outputs()
7692 } else if (HAS_PCH_SPLIT(display)) { in intel_setup_outputs()
7700 intel_lvds_init(display); in intel_setup_outputs()
7701 intel_crt_init(display); in intel_setup_outputs()
7703 dpd_is_edp = intel_dp_is_port_edp(display, PORT_D); in intel_setup_outputs()
7705 if (ilk_has_edp_a(display)) in intel_setup_outputs()
7706 g4x_dp_init(display, DP_A, PORT_A); in intel_setup_outputs()
7708 if (intel_de_read(display, PCH_HDMIB) & SDVO_DETECTED) { in intel_setup_outputs()
7710 found = intel_sdvo_init(display, PCH_SDVOB, PORT_B); in intel_setup_outputs()
7712 g4x_hdmi_init(display, PCH_HDMIB, PORT_B); in intel_setup_outputs()
7713 if (!found && (intel_de_read(display, PCH_DP_B) & DP_DETECTED)) in intel_setup_outputs()
7714 g4x_dp_init(display, PCH_DP_B, PORT_B); in intel_setup_outputs()
7717 if (intel_de_read(display, PCH_HDMIC) & SDVO_DETECTED) in intel_setup_outputs()
7718 g4x_hdmi_init(display, PCH_HDMIC, PORT_C); in intel_setup_outputs()
7720 if (!dpd_is_edp && intel_de_read(display, PCH_HDMID) & SDVO_DETECTED) in intel_setup_outputs()
7721 g4x_hdmi_init(display, PCH_HDMID, PORT_D); in intel_setup_outputs()
7723 if (intel_de_read(display, PCH_DP_C) & DP_DETECTED) in intel_setup_outputs()
7724 g4x_dp_init(display, PCH_DP_C, PORT_C); in intel_setup_outputs()
7726 if (intel_de_read(display, PCH_DP_D) & DP_DETECTED) in intel_setup_outputs()
7727 g4x_dp_init(display, PCH_DP_D, PORT_D); in intel_setup_outputs()
7728 } else if (display->platform.valleyview || display->platform.cherryview) { in intel_setup_outputs()
7731 if (display->platform.valleyview && display->vbt.int_crt_support) in intel_setup_outputs()
7732 intel_crt_init(display); in intel_setup_outputs()
7749 has_edp = intel_dp_is_port_edp(display, PORT_B); in intel_setup_outputs()
7750 has_port = intel_bios_is_port_present(display, PORT_B); in intel_setup_outputs()
7751 if (intel_de_read(display, VLV_DP_B) & DP_DETECTED || has_port) in intel_setup_outputs()
7752 has_edp &= g4x_dp_init(display, VLV_DP_B, PORT_B); in intel_setup_outputs()
7753 if ((intel_de_read(display, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) in intel_setup_outputs()
7754 g4x_hdmi_init(display, VLV_HDMIB, PORT_B); in intel_setup_outputs()
7756 has_edp = intel_dp_is_port_edp(display, PORT_C); in intel_setup_outputs()
7757 has_port = intel_bios_is_port_present(display, PORT_C); in intel_setup_outputs()
7758 if (intel_de_read(display, VLV_DP_C) & DP_DETECTED || has_port) in intel_setup_outputs()
7759 has_edp &= g4x_dp_init(display, VLV_DP_C, PORT_C); in intel_setup_outputs()
7760 if ((intel_de_read(display, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) in intel_setup_outputs()
7761 g4x_hdmi_init(display, VLV_HDMIC, PORT_C); in intel_setup_outputs()
7763 if (display->platform.cherryview) { in intel_setup_outputs()
7768 has_port = intel_bios_is_port_present(display, PORT_D); in intel_setup_outputs()
7769 if (intel_de_read(display, CHV_DP_D) & DP_DETECTED || has_port) in intel_setup_outputs()
7770 g4x_dp_init(display, CHV_DP_D, PORT_D); in intel_setup_outputs()
7771 if (intel_de_read(display, CHV_HDMID) & SDVO_DETECTED || has_port) in intel_setup_outputs()
7772 g4x_hdmi_init(display, CHV_HDMID, PORT_D); in intel_setup_outputs()
7775 vlv_dsi_init(display); in intel_setup_outputs()
7776 } else if (display->platform.pineview) { in intel_setup_outputs()
7777 intel_lvds_init(display); in intel_setup_outputs()
7778 intel_crt_init(display); in intel_setup_outputs()
7779 } else if (IS_DISPLAY_VER(display, 3, 4)) { in intel_setup_outputs()
7782 if (display->platform.mobile) in intel_setup_outputs()
7783 intel_lvds_init(display); in intel_setup_outputs()
7785 intel_crt_init(display); in intel_setup_outputs()
7787 if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) { in intel_setup_outputs()
7788 drm_dbg_kms(display->drm, "probing SDVOB\n"); in intel_setup_outputs()
7789 found = intel_sdvo_init(display, GEN3_SDVOB, PORT_B); in intel_setup_outputs()
7790 if (!found && display->platform.g4x) { in intel_setup_outputs()
7791 drm_dbg_kms(display->drm, in intel_setup_outputs()
7793 g4x_hdmi_init(display, GEN4_HDMIB, PORT_B); in intel_setup_outputs()
7796 if (!found && display->platform.g4x) in intel_setup_outputs()
7797 g4x_dp_init(display, DP_B, PORT_B); in intel_setup_outputs()
7802 if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) { in intel_setup_outputs()
7803 drm_dbg_kms(display->drm, "probing SDVOC\n"); in intel_setup_outputs()
7804 found = intel_sdvo_init(display, GEN3_SDVOC, PORT_C); in intel_setup_outputs()
7807 if (!found && (intel_de_read(display, GEN3_SDVOC) & SDVO_DETECTED)) { in intel_setup_outputs()
7809 if (display->platform.g4x) { in intel_setup_outputs()
7810 drm_dbg_kms(display->drm, in intel_setup_outputs()
7812 g4x_hdmi_init(display, GEN4_HDMIC, PORT_C); in intel_setup_outputs()
7814 if (display->platform.g4x) in intel_setup_outputs()
7815 g4x_dp_init(display, DP_C, PORT_C); in intel_setup_outputs()
7818 if (display->platform.g4x && (intel_de_read(display, DP_D) & DP_DETECTED)) in intel_setup_outputs()
7819 g4x_dp_init(display, DP_D, PORT_D); in intel_setup_outputs()
7821 if (SUPPORTS_TV(display)) in intel_setup_outputs()
7822 intel_tv_init(display); in intel_setup_outputs()
7823 } else if (DISPLAY_VER(display) == 2) { in intel_setup_outputs()
7824 if (display->platform.i85x) in intel_setup_outputs()
7825 intel_lvds_init(display); in intel_setup_outputs()
7827 intel_crt_init(display); in intel_setup_outputs()
7828 intel_dvo_init(display); in intel_setup_outputs()
7831 for_each_intel_encoder(display->drm, encoder) { in intel_setup_outputs()
7838 intel_init_pch_refclk(display); in intel_setup_outputs()
7840 drm_helper_move_panel_connectors_to_head(display->drm); in intel_setup_outputs()
7843 static int max_dotclock(struct intel_display *display) in max_dotclock() argument
7845 int max_dotclock = display->cdclk.max_dotclk_freq; in max_dotclock()
7847 if (HAS_ULTRAJOINER(display)) in max_dotclock()
7849 else if (HAS_UNCOMPRESSED_JOINER(display) || HAS_BIGJOINER(display)) in max_dotclock()
7858 struct intel_display *display = to_intel_display(dev); in intel_mode_valid() local
7895 if (mode->clock > max_dotclock(display)) in intel_mode_valid()
7899 if (DISPLAY_VER(display) >= 11) { in intel_mode_valid()
7904 } else if (DISPLAY_VER(display) >= 9 || in intel_mode_valid()
7905 display->platform.broadwell || display->platform.haswell) { in intel_mode_valid()
7910 } else if (DISPLAY_VER(display) >= 3) { in intel_mode_valid()
7937 enum drm_mode_status intel_cpu_transcoder_mode_valid(struct intel_display *display, in intel_cpu_transcoder_mode_valid() argument
7944 if (DISPLAY_VER(display) >= 5) { in intel_cpu_transcoder_mode_valid()
7963 if ((DISPLAY_VER(display) >= 5 || display->platform.g4x) && in intel_cpu_transcoder_mode_valid()
7971 intel_mode_valid_max_plane_size(struct intel_display *display, in intel_mode_valid_max_plane_size() argument
7981 if (DISPLAY_VER(display) < 9) in intel_mode_valid_max_plane_size()
7989 if (DISPLAY_VER(display) >= 30) { in intel_mode_valid_max_plane_size()
7992 } else if (DISPLAY_VER(display) >= 11) { in intel_mode_valid_max_plane_size()
8055 * intel_init_display_hooks - initialize the display modesetting hooks
8056 * @display: display device private
8058 void intel_init_display_hooks(struct intel_display *display) in intel_init_display_hooks() argument
8060 if (DISPLAY_VER(display) >= 9) { in intel_init_display_hooks()
8061 display->funcs.display = &skl_display_funcs; in intel_init_display_hooks()
8062 } else if (HAS_DDI(display)) { in intel_init_display_hooks()
8063 display->funcs.display = &ddi_display_funcs; in intel_init_display_hooks()
8064 } else if (HAS_PCH_SPLIT(display)) { in intel_init_display_hooks()
8065 display->funcs.display = &pch_split_display_funcs; in intel_init_display_hooks()
8066 } else if (display->platform.cherryview || in intel_init_display_hooks()
8067 display->platform.valleyview) { in intel_init_display_hooks()
8068 display->funcs.display = &vlv_display_funcs; in intel_init_display_hooks()
8070 display->funcs.display = &i9xx_display_funcs; in intel_init_display_hooks()
8074 int intel_initial_commit(struct intel_display *display) in intel_initial_commit() argument
8081 state = drm_atomic_state_alloc(display->drm); in intel_initial_commit()
8091 for_each_intel_crtc(display->drm, crtc) { in intel_initial_commit()
8118 for_each_intel_encoder_mask(display->drm, encoder, in intel_initial_commit()
8148 void i830_enable_pipe(struct intel_display *display, enum pipe pipe) in i830_enable_pipe() argument
8150 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); in i830_enable_pipe()
8163 drm_WARN_ON(display->drm, in i830_enable_pipe()
8166 drm_dbg_kms(display->drm, in i830_enable_pipe()
8178 intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder), in i830_enable_pipe()
8180 intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder), in i830_enable_pipe()
8182 intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder), in i830_enable_pipe()
8184 intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), in i830_enable_pipe()
8186 intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), in i830_enable_pipe()
8188 intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder), in i830_enable_pipe()
8190 intel_de_write(display, PIPESRC(display, pipe), in i830_enable_pipe()
8193 intel_de_write(display, FP0(pipe), fp); in i830_enable_pipe()
8194 intel_de_write(display, FP1(pipe), fp); in i830_enable_pipe()
8201 intel_de_write(display, DPLL(display, pipe), in i830_enable_pipe()
8203 intel_de_write(display, DPLL(display, pipe), dpll); in i830_enable_pipe()
8206 intel_de_posting_read(display, DPLL(display, pipe)); in i830_enable_pipe()
8214 intel_de_write(display, DPLL(display, pipe), dpll); in i830_enable_pipe()
8218 intel_de_write(display, DPLL(display, pipe), dpll); in i830_enable_pipe()
8219 intel_de_posting_read(display, DPLL(display, pipe)); in i830_enable_pipe()
8223 intel_de_write(display, TRANSCONF(display, pipe), TRANSCONF_ENABLE); in i830_enable_pipe()
8224 intel_de_posting_read(display, TRANSCONF(display, pipe)); in i830_enable_pipe()
8229 void i830_disable_pipe(struct intel_display *display, enum pipe pipe) in i830_disable_pipe() argument
8231 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); in i830_disable_pipe()
8233 drm_dbg_kms(display->drm, "disabling pipe %c due to force quirk\n", in i830_disable_pipe()
8236 drm_WARN_ON(display->drm, in i830_disable_pipe()
8237 intel_de_read(display, DSPCNTR(display, PLANE_A)) & DISP_ENABLE); in i830_disable_pipe()
8238 drm_WARN_ON(display->drm, in i830_disable_pipe()
8239 intel_de_read(display, DSPCNTR(display, PLANE_B)) & DISP_ENABLE); in i830_disable_pipe()
8240 drm_WARN_ON(display->drm, in i830_disable_pipe()
8241 intel_de_read(display, DSPCNTR(display, PLANE_C)) & DISP_ENABLE); in i830_disable_pipe()
8242 drm_WARN_ON(display->drm, in i830_disable_pipe()
8243 intel_de_read(display, CURCNTR(display, PIPE_A)) & MCURSOR_MODE_MASK); in i830_disable_pipe()
8244 drm_WARN_ON(display->drm, in i830_disable_pipe()
8245 intel_de_read(display, CURCNTR(display, PIPE_B)) & MCURSOR_MODE_MASK); in i830_disable_pipe()
8247 intel_de_write(display, TRANSCONF(display, pipe), 0); in i830_disable_pipe()
8248 intel_de_posting_read(display, TRANSCONF(display, pipe)); in i830_disable_pipe()
8252 intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS); in i830_disable_pipe()
8253 intel_de_posting_read(display, DPLL(display, pipe)); in i830_disable_pipe()
8256 bool intel_scanout_needs_vtd_wa(struct intel_display *display) in intel_scanout_needs_vtd_wa() argument
8258 struct drm_i915_private *i915 = to_i915(display->drm); in intel_scanout_needs_vtd_wa()
8260 return IS_DISPLAY_VER(display, 6, 11) && i915_vtd_active(i915); in intel_scanout_needs_vtd_wa()