1124 	int n_entries, ln;  in icl_ddi_combo_vswing_program()  local
1150 	for (ln = 0; ln < 4; ln++) {  in icl_ddi_combo_vswing_program()
1151 		int level = intel_ddi_level(encoder, crtc_state, ln);  in icl_ddi_combo_vswing_program()
1153 		intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy),  in icl_ddi_combo_vswing_program()
1162 	for (ln = 0; ln < 4; ln++) {  in icl_ddi_combo_vswing_program()
1163 		int level = intel_ddi_level(encoder, crtc_state, ln);  in icl_ddi_combo_vswing_program()
1165 		intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),  in icl_ddi_combo_vswing_program()
1173 	for (ln = 0; ln < 4; ln++) {  in icl_ddi_combo_vswing_program()
1174 		int level = intel_ddi_level(encoder, crtc_state, ln);  in icl_ddi_combo_vswing_program()
1176 		intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy),  in icl_ddi_combo_vswing_program()
1188 	int ln;  in icl_combo_phy_set_signal_levels()  local
1209 	for (ln = 0; ln < 4; ln++) {  in icl_combo_phy_set_signal_levels()
1210 		intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),  in icl_combo_phy_set_signal_levels()
1212 			     icl_combo_phy_loadgen_select(crtc_state, ln));  in icl_combo_phy_set_signal_levels()
1239 	int n_entries, ln;  in icl_mg_phy_set_signal_levels()  local
1248 	for (ln = 0; ln < 2; ln++) {  in icl_mg_phy_set_signal_levels()
1249 		intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port),  in icl_mg_phy_set_signal_levels()
1251 		intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port),  in icl_mg_phy_set_signal_levels()
1256 	for (ln = 0; ln < 2; ln++) {  in icl_mg_phy_set_signal_levels()
1259 		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);  in icl_mg_phy_set_signal_levels()
1261 		intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port),  in icl_mg_phy_set_signal_levels()
1265 		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);  in icl_mg_phy_set_signal_levels()
1267 		intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port),  in icl_mg_phy_set_signal_levels()
1273 	for (ln = 0; ln < 2; ln++) {  in icl_mg_phy_set_signal_levels()
1276 		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);  in icl_mg_phy_set_signal_levels()
1278 		intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port),  in icl_mg_phy_set_signal_levels()
1285 		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);  in icl_mg_phy_set_signal_levels()
1287 		intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port),  in icl_mg_phy_set_signal_levels()
1302 	for (ln = 0; ln < 2; ln++) {  in icl_mg_phy_set_signal_levels()
1303 		intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port),  in icl_mg_phy_set_signal_levels()
1309 	for (ln = 0; ln < 2; ln++) {  in icl_mg_phy_set_signal_levels()
1310 		intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port),  in icl_mg_phy_set_signal_levels()
1317 		intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port),  in icl_mg_phy_set_signal_levels()
1326 	for (ln = 0; ln < 2; ln++) {  in icl_mg_phy_set_signal_levels()
1327 		intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),  in icl_mg_phy_set_signal_levels()
1329 		intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),  in icl_mg_phy_set_signal_levels()
1340 	int n_entries, ln;  in tgl_dkl_phy_set_signal_levels()  local
1349 	for (ln = 0; ln < 2; ln++) {  in tgl_dkl_phy_set_signal_levels()
1352 		intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);  in tgl_dkl_phy_set_signal_levels()
1354 		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);  in tgl_dkl_phy_set_signal_levels()
1356 		intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln),  in tgl_dkl_phy_set_signal_levels()
1364 		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);  in tgl_dkl_phy_set_signal_levels()
1366 		intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln),  in tgl_dkl_phy_set_signal_levels()
1374 		intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),  in tgl_dkl_phy_set_signal_levels()
1381 				if (ln == 0) {  in tgl_dkl_phy_set_signal_levels()
1393 			intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),  in tgl_dkl_phy_set_signal_levels()
3593 	int ln;  in adlp_tbt_to_dp_alt_switch_wa()  local
3595 	for (ln = 0; ln < 2; ln++)  in adlp_tbt_to_dp_alt_switch_wa()
3596 		intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0);  in adlp_tbt_to_dp_alt_switch_wa()