100 	int level;  in intel_ddi_hdmi_level()  local
102 	level = intel_bios_hdmi_level_shift(encoder->devdata);  in intel_ddi_hdmi_level()
103 	if (level < 0)  in intel_ddi_hdmi_level()
104 		level = trans->hdmi_default_entry;  in intel_ddi_hdmi_level()
106 	return level;  in intel_ddi_hdmi_level()
120  * Starting with Haswell, DDI port buffers must be programmed with correct
127 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in hsw_prepare_dp_ddi_buffers()
130 	enum port port = encoder->port;  in hsw_prepare_dp_ddi_buffers()  local
133 	trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);  in hsw_prepare_dp_ddi_buffers()
134 	if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))  in hsw_prepare_dp_ddi_buffers()
139 	    intel_bios_dp_boost_level(encoder->devdata))  in hsw_prepare_dp_ddi_buffers()
143 		intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i),  in hsw_prepare_dp_ddi_buffers()
144 			       trans->entries[i].hsw.trans1 | iboost_bit);  in hsw_prepare_dp_ddi_buffers()
145 		intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i),  in hsw_prepare_dp_ddi_buffers()
146 			       trans->entries[i].hsw.trans2);  in hsw_prepare_dp_ddi_buffers()
151  * Starting with Haswell, DDI port buffers must be programmed with correct
158 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in hsw_prepare_hdmi_ddi_buffers()
159 	int level = intel_ddi_level(encoder, crtc_state, 0);  in hsw_prepare_hdmi_ddi_buffers()  local
162 	enum port port = encoder->port;  in hsw_prepare_hdmi_ddi_buffers()  local
165 	trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);  in hsw_prepare_hdmi_ddi_buffers()
166 	if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))  in hsw_prepare_hdmi_ddi_buffers()
171 	    intel_bios_hdmi_boost_level(encoder->devdata))  in hsw_prepare_hdmi_ddi_buffers()
175 	intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9),  in hsw_prepare_hdmi_ddi_buffers()
176 		       trans->entries[level].hsw.trans1 | iboost_bit);  in hsw_prepare_hdmi_ddi_buffers()
177 	intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9),  in hsw_prepare_hdmi_ddi_buffers()
178 		       trans->entries[level].hsw.trans2);  in hsw_prepare_hdmi_ddi_buffers()
181 static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port)  in intel_ddi_buf_status_reg()  argument
183 	struct drm_i915_private *i915 = to_i915(display->drm);  in intel_ddi_buf_status_reg()
186 		return XELPDP_PORT_BUF_CTL1(i915, port);  in intel_ddi_buf_status_reg()
188 		return DDI_BUF_CTL(port);  in intel_ddi_buf_status_reg()
191 void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port)  in intel_wait_ddi_buf_idle()  argument
197 	 * HSW-ADL: 8 us  in intel_wait_ddi_buf_idle()
201 	if (display->platform.broxton) {  in intel_wait_ddi_buf_idle()
207 	if (intel_de_wait_for_set(display, intel_ddi_buf_status_reg(display, port),  in intel_wait_ddi_buf_idle()
209 		drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n",  in intel_wait_ddi_buf_idle()
210 			port_name(port));  in intel_wait_ddi_buf_idle()
216 	enum port port = encoder->port;  in intel_wait_ddi_buf_active()  local
222 	 * TGL-ADL combo PHY: 1000 us  in intel_wait_ddi_buf_active()
223 	 * TGL-ADL TypeC PHY: 3000 us  in intel_wait_ddi_buf_active()
224 	 * HSW-ICL          : fixed 518 us  in intel_wait_ddi_buf_active()
232 	if (intel_de_wait_for_clear(display, intel_ddi_buf_status_reg(display, port),  in intel_wait_ddi_buf_active()
234 		drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n",  in intel_wait_ddi_buf_active()
235 			port_name(port));  in intel_wait_ddi_buf_active()
240 	switch (pll->info->id) {  in hsw_pll_to_ddi_pll_sel()
254 		MISSING_CASE(pll->info->id);  in hsw_pll_to_ddi_pll_sel()
262 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;  in icl_pll_to_ddi_clk_sel()
263 	int clock = crtc_state->port_clock;  in icl_pll_to_ddi_clk_sel()
264 	const enum intel_dpll_id id = pll->info->id;  in icl_pll_to_ddi_clk_sel()
327 	 * assertion/desassertion of the port lane enables. The target delay  in dp_phy_lane_stagger_delay()
338 	 * port_clock (10 kHz) -> bits    / 100 us  in dp_phy_lane_stagger_delay()
339 	 * / symbol_size       -> symbols / 100 us  in dp_phy_lane_stagger_delay()
340 	 * / 1000              -> symbols / 100 ns  in dp_phy_lane_stagger_delay()
349 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_ddi_init_dp_buf_reg()
354 	intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) |  in intel_ddi_init_dp_buf_reg()
357 	if (dig_port->lane_reversal)  in intel_ddi_init_dp_buf_reg()
358 		intel_dp->DP |= DDI_BUF_PORT_REVERSAL;  in intel_ddi_init_dp_buf_reg()
359 	if (dig_port->ddi_a_4_lanes)  in intel_ddi_init_dp_buf_reg()
360 		intel_dp->DP |= DDI_A_4_LANES;  in intel_ddi_init_dp_buf_reg()
364 			intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;  in intel_ddi_init_dp_buf_reg()
366 			intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;  in intel_ddi_init_dp_buf_reg()
370 		intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);  in intel_ddi_init_dp_buf_reg()
372 			intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;  in intel_ddi_init_dp_buf_reg()
376 		int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock);  in intel_ddi_init_dp_buf_reg()
378 		intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay);  in intel_ddi_init_dp_buf_reg()
383 				 enum port port)  in icl_calc_tbt_pll_link()  argument
385 	u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;  in icl_calc_tbt_pll_link()
407 	if (pipe_config->has_pch_encoder)  in ddi_dotclock_get()
410 	pipe_config->hw.adjusted_mode.crtc_clock =  in ddi_dotclock_get()
417 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_ddi_set_dp_msa()
418 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_ddi_set_dp_msa()
419 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_ddi_set_dp_msa()
425 	drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder));  in intel_ddi_set_dp_msa()
429 	switch (crtc_state->pipe_bpp) {  in intel_ddi_set_dp_msa()
443 		MISSING_CASE(crtc_state->pipe_bpp);  in intel_ddi_set_dp_msa()
448 	drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&  in intel_ddi_set_dp_msa()
449 		    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);  in intel_ddi_set_dp_msa()
451 	if (crtc_state->limited_color_range)  in intel_ddi_set_dp_msa()
459 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)  in intel_ddi_set_dp_msa()
488 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_ddi_config_transcoder_dp2()
510 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_ddi_transcoder_func_reg_val_get()
511 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_ddi_transcoder_func_reg_val_get()
512 	enum pipe pipe = crtc->pipe;  in intel_ddi_transcoder_func_reg_val_get()
513 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_ddi_transcoder_func_reg_val_get()
514 	enum port port = encoder->port;  in intel_ddi_transcoder_func_reg_val_get()  local
520 		temp |= TGL_TRANS_DDI_SELECT_PORT(port);  in intel_ddi_transcoder_func_reg_val_get()
522 		temp |= TRANS_DDI_SELECT_PORT(port);  in intel_ddi_transcoder_func_reg_val_get()
524 	switch (crtc_state->pipe_bpp) {  in intel_ddi_transcoder_func_reg_val_get()
526 		MISSING_CASE(crtc_state->pipe_bpp);  in intel_ddi_transcoder_func_reg_val_get()
542 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)  in intel_ddi_transcoder_func_reg_val_get()
544 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)  in intel_ddi_transcoder_func_reg_val_get()
553 			/* On Haswell, can only use the always-on power well for  in intel_ddi_transcoder_func_reg_val_get()
557 			if (crtc_state->pch_pfit.force_thru)  in intel_ddi_transcoder_func_reg_val_get()
572 		if (crtc_state->has_hdmi_sink)  in intel_ddi_transcoder_func_reg_val_get()
577 		if (crtc_state->hdmi_scrambling)  in intel_ddi_transcoder_func_reg_val_get()
579 		if (crtc_state->hdmi_high_tmds_clock_ratio)  in intel_ddi_transcoder_func_reg_val_get()
582 			temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count);  in intel_ddi_transcoder_func_reg_val_get()
585 		temp |= (crtc_state->fdi_lanes - 1) << 1;  in intel_ddi_transcoder_func_reg_val_get()
592 		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);  in intel_ddi_transcoder_func_reg_val_get()
597 			master = crtc_state->mst_master_transcoder;  in intel_ddi_transcoder_func_reg_val_get()
598 			drm_WARN_ON(&dev_priv->drm,  in intel_ddi_transcoder_func_reg_val_get()
604 		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);  in intel_ddi_transcoder_func_reg_val_get()
608 	    crtc_state->master_transcoder != INVALID_TRANSCODER) {  in intel_ddi_transcoder_func_reg_val_get()
610 			bdw_trans_port_sync_master_select(crtc_state->master_transcoder);  in intel_ddi_transcoder_func_reg_val_get()
622 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_ddi_enable_transcoder_func()
623 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_ddi_enable_transcoder_func()
624 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_ddi_enable_transcoder_func()
627 		enum transcoder master_transcoder = crtc_state->master_transcoder;  in intel_ddi_enable_transcoder_func()
657 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_ddi_config_transcoder_func()
658 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_ddi_config_transcoder_func()
659 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_ddi_config_transcoder_func()
671  * Disable the DDI function and port syncing.
672  * For SST, pre-TGL MST, TGL+ MST-slave transcoders: deselect the DDI port,
673  * SST/MST mode and disable the DP2 configuration. For TGL+ MST-master
679 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_ddi_disable_transcoder_func()
680 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_ddi_disable_transcoder_func()
681 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_ddi_disable_transcoder_func()
692 	drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING);  in intel_ddi_disable_transcoder_func()
717 		drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n");  in intel_ddi_disable_transcoder_func()
728 	struct drm_device *dev = intel_encoder->base.dev;  in intel_ddi_toggle_hdcp_bits()
734 						     intel_encoder->power_domain);  in intel_ddi_toggle_hdcp_bits()
736 		return -ENXIO;  in intel_ddi_toggle_hdcp_bits()
740 	intel_display_power_put(display, intel_encoder->power_domain, wakeref);  in intel_ddi_toggle_hdcp_bits()
747 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in intel_ddi_connector_get_hw_state()
749 	int type = intel_connector->base.connector_type;  in intel_ddi_connector_get_hw_state()
750 	enum port port = encoder->port;  in intel_ddi_connector_get_hw_state()  local
758 						     encoder->power_domain);  in intel_ddi_connector_get_hw_state()
763 	if (!encoder->get_hw_state(encoder, &pipe)) {  in intel_ddi_connector_get_hw_state()
768 	if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)  in intel_ddi_connector_get_hw_state()
786 		 * encoder->get_hw_state() should have bailed out on MST. This  in intel_ddi_connector_get_hw_state()
787 		 * must be SST and non-eDP.  in intel_ddi_connector_get_hw_state()
790 	} else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) {  in intel_ddi_connector_get_hw_state()
791 		/* encoder->get_hw_state() should have bailed out on MST. */  in intel_ddi_connector_get_hw_state()
798 	intel_display_power_put(display, encoder->power_domain, wakeref);  in intel_ddi_connector_get_hw_state()
807 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in intel_ddi_get_encoder_pipes()
808 	enum port port = encoder->port;  in intel_ddi_get_encoder_pipes()  local
818 						     encoder->power_domain);  in intel_ddi_get_encoder_pipes()
822 	tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));  in intel_ddi_get_encoder_pipes()
826 	if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) {  in intel_ddi_get_encoder_pipes()
861 			ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);  in intel_ddi_get_encoder_pipes()
864 			ddi_select = TRANS_DDI_SELECT_PORT(port);  in intel_ddi_get_encoder_pipes()
886 		drm_dbg_kms(&dev_priv->drm,  in intel_ddi_get_encoder_pipes()
888 			    encoder->base.base.id, encoder->base.name);  in intel_ddi_get_encoder_pipes()
909 		drm_dbg_kms(&dev_priv->drm,  in intel_ddi_get_encoder_pipes()
911 			    encoder->base.base.id, encoder->base.name,  in intel_ddi_get_encoder_pipes()
913 		*pipe_mask = BIT(ffs(*pipe_mask) - 1);  in intel_ddi_get_encoder_pipes()
917 		drm_dbg_kms(&dev_priv->drm,  in intel_ddi_get_encoder_pipes()
918 …"Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b …  in intel_ddi_get_encoder_pipes()
919 			    encoder->base.base.id, encoder->base.name,  in intel_ddi_get_encoder_pipes()
926 		tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port));  in intel_ddi_get_encoder_pipes()
930 			drm_err(&dev_priv->drm,  in intel_ddi_get_encoder_pipes()
932 				encoder->base.base.id, encoder->base.name, tmp);  in intel_ddi_get_encoder_pipes()
935 	intel_display_power_put(display, encoder->power_domain, wakeref);  in intel_ddi_get_encoder_pipes()
949 	*pipe = ffs(pipe_mask) - 1;  in intel_ddi_get_hw_state()
964 	 * disabled. Accordingly use the AUX_IO_<port> power domain here which  in intel_ddi_main_link_aux_domain()
969 	 * well, so we can acquire a wider AUX_<port> power domain reference  in intel_ddi_main_link_aux_domain()
970 	 * instead of a specific AUX_IO_<port> reference without powering up any  in intel_ddi_main_link_aux_domain()
973 	if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state))  in intel_ddi_main_link_aux_domain()
974 		return intel_display_power_aux_io_domain(display, dig_port->aux_ch);  in intel_ddi_main_link_aux_domain()
977 		  intel_encoder_is_tc(&dig_port->base)))  in intel_ddi_main_link_aux_domain()
991 	drm_WARN_ON(display->drm, dig_port->aux_wakeref);  in main_link_aux_power_domain_get()
996 	dig_port->aux_wakeref = intel_display_power_get(display, domain);  in main_link_aux_power_domain_get()
1008 	wf = fetch_and_zero(&dig_port->aux_wakeref);  in main_link_aux_power_domain_put()
1023 	 * happen since fake-MST encoders don't set their get_power_domains()  in intel_ddi_get_power_domains()
1026 	if (drm_WARN_ON(display->drm,  in intel_ddi_get_power_domains()
1033 		drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref);  in intel_ddi_get_power_domains()
1034 		dig_port->ddi_io_wakeref = intel_display_power_get(display,  in intel_ddi_get_power_domains()
1035 								   dig_port->ddi_io_power_domain);  in intel_ddi_get_power_domains()
1044 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_ddi_enable_transcoder_clock()
1045 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_ddi_enable_transcoder_clock()
1046 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_ddi_enable_transcoder_clock()
1056 		val = TGL_TRANS_CLK_SEL_PORT(encoder->port);  in intel_ddi_enable_transcoder_clock()
1058 		val = TRANS_CLK_SEL_PORT(encoder->port);  in intel_ddi_enable_transcoder_clock()
1065 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in intel_ddi_disable_transcoder_clock()
1066 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_ddi_disable_transcoder_clock()
1081 				enum port port, u8 iboost)  in _skl_ddi_set_iboost()  argument
1086 	tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));  in _skl_ddi_set_iboost()
1088 		tmp |= iboost << BALANCE_LEG_SHIFT(port);  in _skl_ddi_set_iboost()
1090 		tmp |= BALANCE_LEG_DISABLE(port);  in _skl_ddi_set_iboost()
1096 			       int level)  in skl_ddi_set_iboost()  argument
1099 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in skl_ddi_set_iboost()
1103 		iboost = intel_bios_hdmi_boost_level(encoder->devdata);  in skl_ddi_set_iboost()
1105 		iboost = intel_bios_dp_boost_level(encoder->devdata);  in skl_ddi_set_iboost()
1111 		trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);  in skl_ddi_set_iboost()
1112 		if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))  in skl_ddi_set_iboost()
1115 		iboost = trans->entries[level].hsw.i_boost;  in skl_ddi_set_iboost()
1120 		drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost);  in skl_ddi_set_iboost()
1124 	_skl_ddi_set_iboost(dev_priv, encoder->port, iboost);  in skl_ddi_set_iboost()
1126 	if (encoder->port == PORT_A && dig_port->max_lanes == 4)  in skl_ddi_set_iboost()
1133 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_ddi_dp_voltage_max()
1134 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_ddi_dp_voltage_max()
1137 	encoder->get_buf_trans(encoder, crtc_state, &n_entries);  in intel_ddi_dp_voltage_max()
1139 	if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))  in intel_ddi_dp_voltage_max()
1141 	if (drm_WARN_ON(&dev_priv->drm,  in intel_ddi_dp_voltage_max()
1145 	return index_to_dp_signal_levels[n_entries - 1] &  in intel_ddi_dp_voltage_max()
1150  * We assume that the full set of pre-emphasis values can be
1162 	if (crtc_state->port_clock > 600000)  in icl_combo_phy_loadgen_select()
1165 	if (crtc_state->lane_count == 4)  in icl_combo_phy_loadgen_select()
1174 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in icl_ddi_combo_vswing_program()
1180 	trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);  in icl_ddi_combo_vswing_program()
1181 	if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))  in icl_ddi_combo_vswing_program()
1188 		intel_dp->hobl_active = is_hobl_buf_trans(trans);  in icl_ddi_combo_vswing_program()
1190 			     intel_dp->hobl_active ? val : 0);  in icl_ddi_combo_vswing_program()
1205 		int level = intel_ddi_level(encoder, crtc_state, ln);  in icl_ddi_combo_vswing_program()  local
1209 			     SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) |  in icl_ddi_combo_vswing_program()
1210 			     SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) |  in icl_ddi_combo_vswing_program()
1217 		int level = intel_ddi_level(encoder, crtc_state, ln);  in icl_ddi_combo_vswing_program()  local
1221 			     POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) |  in icl_ddi_combo_vswing_program()
1222 			     POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) |  in icl_ddi_combo_vswing_program()
1223 			     CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff));  in icl_ddi_combo_vswing_program()
1228 		int level = intel_ddi_level(encoder, crtc_state, ln);  in icl_ddi_combo_vswing_program()  local
1232 			     N_SCALAR(trans->entries[level].icl.dw7_n_scalar));  in icl_ddi_combo_vswing_program()
1239 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in icl_combo_phy_set_signal_levels()
1245 	 * 1. If port type is eDP or DP,  in icl_combo_phy_set_signal_levels()
1278 	/* 5. Program swing and de-emphasis */  in icl_combo_phy_set_signal_levels()
1290 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in icl_mg_phy_set_signal_levels()
1298 	trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);  in icl_mg_phy_set_signal_levels()
1299 	if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))  in icl_mg_phy_set_signal_levels()
1311 		int level;  in icl_mg_phy_set_signal_levels()  local
1313 		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);  in icl_mg_phy_set_signal_levels()
1317 			     CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));  in icl_mg_phy_set_signal_levels()
1319 		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);  in icl_mg_phy_set_signal_levels()
1323 			     CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));  in icl_mg_phy_set_signal_levels()
1328 		int level;  in icl_mg_phy_set_signal_levels()  local
1330 		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);  in icl_mg_phy_set_signal_levels()
1335 			     CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |  in icl_mg_phy_set_signal_levels()
1336 			     CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |  in icl_mg_phy_set_signal_levels()
1339 		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);  in icl_mg_phy_set_signal_levels()
1344 			     CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |  in icl_mg_phy_set_signal_levels()
1345 			     CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |  in icl_mg_phy_set_signal_levels()
1352 	 * Program MG_CLKHUB<LN, port being used> with value from frequency table  in icl_mg_phy_set_signal_levels()
1359 			     crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0);  in icl_mg_phy_set_signal_levels()
1362 	/* Program the MG_TX_DCC<LN, port being used> based on the link frequency */  in icl_mg_phy_set_signal_levels()
1367 			     crtc_state->port_clock > 500000 ?  in icl_mg_phy_set_signal_levels()
1374 			     crtc_state->port_clock > 500000 ?  in icl_mg_phy_set_signal_levels()
1399 	trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);  in tgl_dkl_phy_set_signal_levels()
1400 	if (drm_WARN_ON_ONCE(display->drm, !trans))  in tgl_dkl_phy_set_signal_levels()
1404 		int level;  in tgl_dkl_phy_set_signal_levels()  local
1408 		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);  in tgl_dkl_phy_set_signal_levels()
1414 				  DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |  in tgl_dkl_phy_set_signal_levels()
1415 				  DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |  in tgl_dkl_phy_set_signal_levels()
1416 				  DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));  in tgl_dkl_phy_set_signal_levels()
1418 		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);  in tgl_dkl_phy_set_signal_levels()
1424 				  DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |  in tgl_dkl_phy_set_signal_levels()
1425 				  DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |  in tgl_dkl_phy_set_signal_levels()
1426 				  DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));  in tgl_dkl_phy_set_signal_levels()
1431 		if (display->platform.alderlake_p) {  in tgl_dkl_phy_set_signal_levels()
1466 	drm_WARN(display->drm, 1,  in translate_signal_level()
1467 		 "Unsupported voltage swing/pre-emphasis level: 0x%x\n",  in translate_signal_level()
1477 	u8 train_set = intel_dp->train_set[lane];  in intel_ddi_dp_level()
1493 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_ddi_level()
1495 	int level, n_entries;  in intel_ddi_level()  local
1497 	trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);  in intel_ddi_level()
1498 	if (drm_WARN_ON_ONCE(&i915->drm, !trans))  in intel_ddi_level()
1502 		level = intel_ddi_hdmi_level(encoder, trans);  in intel_ddi_level()
1504 		level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state,  in intel_ddi_level()
1507 	if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries))  in intel_ddi_level()
1508 		level = n_entries - 1;  in intel_ddi_level()
1510 	return level;  in intel_ddi_level()
1517 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in hsw_set_signal_levels()
1519 	int level = intel_ddi_level(encoder, crtc_state, 0);  in hsw_set_signal_levels()  local
1520 	enum port port = encoder->port;  in hsw_set_signal_levels()  local
1524 		skl_ddi_set_iboost(encoder, crtc_state, level);  in hsw_set_signal_levels()
1530 	signal_levels = DDI_BUF_TRANS_SELECT(level);  in hsw_set_signal_levels()
1532 	drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",  in hsw_set_signal_levels()
1535 	intel_dp->DP &= ~DDI_BUF_EMP_MASK;  in hsw_set_signal_levels()
1536 	intel_dp->DP |= signal_levels;  in hsw_set_signal_levels()
1538 	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);  in hsw_set_signal_levels()
1539 	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));  in hsw_set_signal_levels()
1545 	mutex_lock(&i915->display.dpll.lock);  in _icl_ddi_enable_clock()
1555 	mutex_unlock(&i915->display.dpll.lock);  in _icl_ddi_enable_clock()
1561 	mutex_lock(&i915->display.dpll.lock);  in _icl_ddi_disable_clock()
1565 	mutex_unlock(&i915->display.dpll.lock);  in _icl_ddi_disable_clock()
1588 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in adls_ddi_enable_clock()
1589 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;  in adls_ddi_enable_clock()
1592 	if (drm_WARN_ON(&i915->drm, !pll))  in adls_ddi_enable_clock()
1597 			      pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),  in adls_ddi_enable_clock()
1603 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in adls_ddi_disable_clock()
1612 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in adls_ddi_is_clock_enabled()
1632 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in rkl_ddi_enable_clock()
1633 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;  in rkl_ddi_enable_clock()
1636 	if (drm_WARN_ON(&i915->drm, !pll))  in rkl_ddi_enable_clock()
1641 			      RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),  in rkl_ddi_enable_clock()
1647 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in rkl_ddi_disable_clock()
1656 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in rkl_ddi_is_clock_enabled()
1676 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in dg1_ddi_enable_clock()
1677 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;  in dg1_ddi_enable_clock()
1680 	if (drm_WARN_ON(&i915->drm, !pll))  in dg1_ddi_enable_clock()
1687 	if (drm_WARN_ON(&i915->drm,  in dg1_ddi_enable_clock()
1688 			(pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||  in dg1_ddi_enable_clock()
1689 			(pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))  in dg1_ddi_enable_clock()
1694 			      DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),  in dg1_ddi_enable_clock()
1700 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in dg1_ddi_disable_clock()
1709 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in dg1_ddi_is_clock_enabled()
1742 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in icl_ddi_combo_enable_clock()
1743 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;  in icl_ddi_combo_enable_clock()
1746 	if (drm_WARN_ON(&i915->drm, !pll))  in icl_ddi_combo_enable_clock()
1751 			      ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),  in icl_ddi_combo_enable_clock()
1757 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in icl_ddi_combo_disable_clock()
1766 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in icl_ddi_combo_is_clock_enabled()
1786 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in jsl_ddi_tc_enable_clock()
1787 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;  in jsl_ddi_tc_enable_clock()
1788 	enum port port = encoder->port;  in jsl_ddi_tc_enable_clock()  local
1790 	if (drm_WARN_ON(&i915->drm, !pll))  in jsl_ddi_tc_enable_clock()
1794 	 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port.  in jsl_ddi_tc_enable_clock()
1797 	intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG);  in jsl_ddi_tc_enable_clock()
1804 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in jsl_ddi_tc_disable_clock()
1805 	enum port port = encoder->port;  in jsl_ddi_tc_disable_clock()  local
1809 	intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);  in jsl_ddi_tc_disable_clock()
1814 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in jsl_ddi_tc_is_clock_enabled()
1815 	enum port port = encoder->port;  in jsl_ddi_tc_is_clock_enabled()  local
1818 	tmp = intel_de_read(i915, DDI_CLK_SEL(port));  in jsl_ddi_tc_is_clock_enabled()
1829 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in icl_ddi_tc_enable_clock()
1830 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;  in icl_ddi_tc_enable_clock()
1832 	enum port port = encoder->port;  in icl_ddi_tc_enable_clock()  local
1834 	if (drm_WARN_ON(&i915->drm, !pll))  in icl_ddi_tc_enable_clock()
1837 	intel_de_write(i915, DDI_CLK_SEL(port),  in icl_ddi_tc_enable_clock()
1840 	mutex_lock(&i915->display.dpll.lock);  in icl_ddi_tc_enable_clock()
1845 	mutex_unlock(&i915->display.dpll.lock);  in icl_ddi_tc_enable_clock()
1850 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in icl_ddi_tc_disable_clock()
1852 	enum port port = encoder->port;  in icl_ddi_tc_disable_clock()  local
1854 	mutex_lock(&i915->display.dpll.lock);  in icl_ddi_tc_disable_clock()
1859 	mutex_unlock(&i915->display.dpll.lock);  in icl_ddi_tc_disable_clock()
1861 	intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);  in icl_ddi_tc_disable_clock()
1866 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in icl_ddi_tc_is_clock_enabled()
1868 	enum port port = encoder->port;  in icl_ddi_tc_is_clock_enabled()  local
1871 	tmp = intel_de_read(i915, DDI_CLK_SEL(port));  in icl_ddi_tc_is_clock_enabled()
1885 	enum port port = encoder->port;  in icl_ddi_tc_get_pll()  local
1889 	tmp = intel_de_read(display, DDI_CLK_SEL(port));  in icl_ddi_tc_get_pll()
1913 	struct intel_display *display = to_intel_display(encoder->base.dev);  in bxt_ddi_get_pll()
1916 	switch (encoder->port) {  in bxt_ddi_get_pll()
1927 		MISSING_CASE(encoder->port);  in bxt_ddi_get_pll()
1937 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in skl_ddi_enable_clock()
1938 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;  in skl_ddi_enable_clock()
1939 	enum port port = encoder->port;  in skl_ddi_enable_clock()  local
1941 	if (drm_WARN_ON(&i915->drm, !pll))  in skl_ddi_enable_clock()
1944 	mutex_lock(&i915->display.dpll.lock);  in skl_ddi_enable_clock()
1947 		     DPLL_CTRL2_DDI_CLK_OFF(port) |  in skl_ddi_enable_clock()
1948 		     DPLL_CTRL2_DDI_CLK_SEL_MASK(port),  in skl_ddi_enable_clock()
1949 		     DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |  in skl_ddi_enable_clock()
1950 		     DPLL_CTRL2_DDI_SEL_OVERRIDE(port));  in skl_ddi_enable_clock()
1952 	mutex_unlock(&i915->display.dpll.lock);  in skl_ddi_enable_clock()
1957 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in skl_ddi_disable_clock()
1958 	enum port port = encoder->port;  in skl_ddi_disable_clock()  local
1960 	mutex_lock(&i915->display.dpll.lock);  in skl_ddi_disable_clock()
1963 		     0, DPLL_CTRL2_DDI_CLK_OFF(port));  in skl_ddi_disable_clock()
1965 	mutex_unlock(&i915->display.dpll.lock);  in skl_ddi_disable_clock()
1970 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in skl_ddi_is_clock_enabled()
1971 	enum port port = encoder->port;  in skl_ddi_is_clock_enabled()  local
1977 	return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));  in skl_ddi_is_clock_enabled()
1983 	enum port port = encoder->port;  in skl_ddi_get_pll()  local
1993 	if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0)  in skl_ddi_get_pll()
1996 	id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>  in skl_ddi_get_pll()
1997 		DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);  in skl_ddi_get_pll()
2005 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in hsw_ddi_enable_clock()
2006 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;  in hsw_ddi_enable_clock()
2007 	enum port port = encoder->port;  in hsw_ddi_enable_clock()  local
2009 	if (drm_WARN_ON(&i915->drm, !pll))  in hsw_ddi_enable_clock()
2012 	intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));  in hsw_ddi_enable_clock()
2017 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in hsw_ddi_disable_clock()
2018 	enum port port = encoder->port;  in hsw_ddi_disable_clock()  local
2020 	intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);  in hsw_ddi_disable_clock()
2025 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in hsw_ddi_is_clock_enabled()
2026 	enum port port = encoder->port;  in hsw_ddi_is_clock_enabled()  local
2028 	return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;  in hsw_ddi_is_clock_enabled()
2034 	enum port port = encoder->port;  in hsw_ddi_get_pll()  local
2038 	tmp = intel_de_read(display, PORT_CLK_SEL(port));  in hsw_ddi_get_pll()
2072 	if (encoder->enable_clock)  in intel_ddi_enable_clock()
2073 		encoder->enable_clock(encoder, crtc_state);  in intel_ddi_enable_clock()
2078 	if (encoder->disable_clock)  in intel_ddi_disable_clock()
2079 		encoder->disable_clock(encoder);  in intel_ddi_disable_clock()
2084 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_ddi_sanitize_encoder_pll_mapping()
2092 	if (encoder->type == INTEL_OUTPUT_DP_MST)  in intel_ddi_sanitize_encoder_pll_mapping()
2095 	if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {  in intel_ddi_sanitize_encoder_pll_mapping()
2104 		if (drm_WARN_ON(&i915->drm, is_mst))  in intel_ddi_sanitize_encoder_pll_mapping()
2108 	port_mask = BIT(encoder->port);  in intel_ddi_sanitize_encoder_pll_mapping()
2109 	ddi_clk_needed = encoder->base.crtc;  in intel_ddi_sanitize_encoder_pll_mapping()
2111 	if (encoder->type == INTEL_OUTPUT_DSI) {  in intel_ddi_sanitize_encoder_pll_mapping()
2119 		for_each_intel_encoder(&i915->drm, other_encoder) {  in intel_ddi_sanitize_encoder_pll_mapping()
2123 			if (drm_WARN_ON(&i915->drm,  in intel_ddi_sanitize_encoder_pll_mapping()
2124 					port_mask & BIT(other_encoder->port)))  in intel_ddi_sanitize_encoder_pll_mapping()
2134 	if (ddi_clk_needed || !encoder->is_clock_enabled ||  in intel_ddi_sanitize_encoder_pll_mapping()
2135 	    !encoder->is_clock_enabled(encoder))  in intel_ddi_sanitize_encoder_pll_mapping()
2138 	drm_dbg_kms(&i915->drm,  in intel_ddi_sanitize_encoder_pll_mapping()
2140 		    encoder->base.base.id, encoder->base.name);  in intel_ddi_sanitize_encoder_pll_mapping()
2142 	encoder->disable_clock(encoder);  in intel_ddi_sanitize_encoder_pll_mapping()
2160 	enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);  in icl_program_mg_dp_mode()
2167 	if (!intel_encoder_is_tc(&dig_port->base) ||  in icl_program_mg_dp_mode()
2184 	width = crtc_state->lane_count;  in icl_program_mg_dp_mode()
2188 		drm_WARN_ON(display->drm,  in icl_program_mg_dp_mode()
2250 		return crtc_state->mst_master_transcoder;  in tgl_dp_tp_transcoder()
2252 		return crtc_state->cpu_transcoder;  in tgl_dp_tp_transcoder()
2258 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in dp_tp_ctl_reg()
2264 		return DP_TP_CTL(encoder->port);  in dp_tp_ctl_reg()
2270 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in dp_tp_status_reg()
2276 		return DP_TP_STATUS(encoder->port);  in dp_tp_status_reg()
2295 		drm_err(display->drm, "Timed out waiting for ACT sent\n");  in intel_ddi_wait_for_act_sent()
2304 	if (!crtc_state->vrr.enable)  in intel_dp_sink_set_msa_timing_par_ignore_state()
2307 	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,  in intel_dp_sink_set_msa_timing_par_ignore_state()
2309 		drm_dbg_kms(display->drm,  in intel_dp_sink_set_msa_timing_par_ignore_state()
2320 	if (!crtc_state->fec_enable)  in intel_dp_sink_set_fec_ready()
2323 	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION,  in intel_dp_sink_set_fec_ready()
2325 		drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n",  in intel_dp_sink_set_fec_ready()
2329 	    drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS,  in intel_dp_sink_set_fec_ready()
2331 		drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n");  in intel_dp_sink_set_fec_ready()
2348 	struct intel_display *display = to_intel_display(aux->drm_dev);  in wait_for_fec_detected()
2358 		drm_dbg_kms(display->drm,  in wait_for_fec_detected()
2375 	if (!crtc_state->fec_enable)  in intel_ddi_wait_for_fec_status()
2386 		drm_err(display->drm,  in intel_ddi_wait_for_fec_status()
2396 		ret = wait_for_fec_detected(&intel_dp->aux, enabled);  in intel_ddi_wait_for_fec_status()
2411 	if (!crtc_state->fec_enable)  in intel_ddi_enable_fec()
2425 		drm_dbg_kms(display->drm, "Retry FEC enabling\n");  in intel_ddi_enable_fec()
2442 	drm_err(display->drm, "Failed to enable FEC after retries\n");  in intel_ddi_enable_fec()
2448 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_ddi_disable_fec()
2450 	if (!crtc_state->fec_enable)  in intel_ddi_disable_fec()
2468 					       crtc_state->lane_count,  in intel_ddi_power_up_lanes()
2469 					       dig_port->lane_reversal);  in intel_ddi_power_up_lanes()
2490 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);  in intel_ddi_mso_get_config()
2491 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in intel_ddi_mso_get_config()
2492 	enum pipe pipe = crtc->pipe;  in intel_ddi_mso_get_config()
2500 	pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;  in intel_ddi_mso_get_config()
2501 	if (!pipe_config->splitter.enable)  in intel_ddi_mso_get_config()
2504 	if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) {  in intel_ddi_mso_get_config()
2505 		pipe_config->splitter.enable = false;  in intel_ddi_mso_get_config()
2511 		drm_WARN(&i915->drm, true,  in intel_ddi_mso_get_config()
2515 		pipe_config->splitter.link_count = 2;  in intel_ddi_mso_get_config()
2518 		pipe_config->splitter.link_count = 4;  in intel_ddi_mso_get_config()
2522 	pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1);  in intel_ddi_mso_get_config()
2527 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_ddi_mso_configure()
2528 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in intel_ddi_mso_configure()
2529 	enum pipe pipe = crtc->pipe;  in intel_ddi_mso_configure()
2535 	if (crtc_state->splitter.enable) {  in intel_ddi_mso_configure()
2537 		dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap);  in intel_ddi_mso_configure()
2538 		if (crtc_state->splitter.link_count == 2)  in intel_ddi_mso_configure()
2552 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in mtl_ddi_enable_d2d()
2553 	enum port port = encoder->port;  in mtl_ddi_enable_d2d()  local
2561 		reg = DDI_BUF_CTL(port);  in mtl_ddi_enable_d2d()
2565 		reg = XELPDP_PORT_BUF_CTL1(dev_priv, port);  in mtl_ddi_enable_d2d()
2572 		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n",  in mtl_ddi_enable_d2d()
2573 			port_name(port));  in mtl_ddi_enable_d2d()
2582 	enum port port = encoder->port;  in mtl_port_buf_ctl_program()  local
2585 	val |= XELPDP_PORT_WIDTH(crtc_state->lane_count);  in mtl_port_buf_ctl_program()
2592 	if (dig_port->lane_reversal)  in mtl_port_buf_ctl_program()
2595 	intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port),  in mtl_port_buf_ctl_program()
2602 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in mtl_port_buf_ctl_io_selection()
2608 	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port),  in mtl_port_buf_ctl_io_selection()
2623 				 crtc_state->port_clock,  in mtl_ddi_pre_enable_dp()
2624 				 crtc_state->lane_count);  in mtl_ddi_pre_enable_dp()
2647 	/* 5. Enable the port PLL */  in mtl_ddi_pre_enable_dp()
2651 	 * 6.a Configure Transcoder Clock Select to direct the Port clock to the  in mtl_ddi_pre_enable_dp()
2657 	 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings.  in mtl_ddi_pre_enable_dp()
2672 	drm_dp_lttpr_wake_timeout_setup(&intel_dp->aux, transparent_mode);  in mtl_ddi_pre_enable_dp()
2677 						   to_intel_connector(conn_state->connector),  in mtl_ddi_pre_enable_dp()
2692 	 * Train Display Port" step.  Note that steps that are specific to  in mtl_ddi_pre_enable_dp()
2696 	 * stream or multi-stream master transcoder" can just be performed  in mtl_ddi_pre_enable_dp()
2705 	 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle  in mtl_ddi_pre_enable_dp()
2721 		ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);  in mtl_ddi_pre_enable_dp()
2737 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in tgl_ddi_pre_enable_dp()
2743 				 crtc_state->port_clock,  in tgl_ddi_pre_enable_dp()
2744 				 crtc_state->lane_count);  in tgl_ddi_pre_enable_dp()
2763 	 * 3. For non-TBT Type-C ports, set FIA lane count  in tgl_ddi_pre_enable_dp()
2767 	 * hsw_crtc_enable()->intel_encoders_pre_pll_enable().  in tgl_ddi_pre_enable_dp()
2771 	 * 4. Enable the port PLL.  in tgl_ddi_pre_enable_dp()
2774 	 * hsw_crtc_enable()->intel_enable_shared_dpll().  We need only  in tgl_ddi_pre_enable_dp()
2775 	 * configure the PLL to port mapping here.  in tgl_ddi_pre_enable_dp()
2781 		drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);  in tgl_ddi_pre_enable_dp()
2782 		dig_port->ddi_io_wakeref = intel_display_power_get(display,  in tgl_ddi_pre_enable_dp()
2783 								   dig_port->ddi_io_power_domain);  in tgl_ddi_pre_enable_dp()
2791 	 * Train Display Port" step.  Note that steps that are specific to  in tgl_ddi_pre_enable_dp()
2795 	 * stream or multi-stream master transcoder" can just be performed  in tgl_ddi_pre_enable_dp()
2800 	 * 7.a Configure Transcoder Clock Select to direct the Port clock to the  in tgl_ddi_pre_enable_dp()
2820 	encoder->set_signal_levels(encoder, crtc_state);  in tgl_ddi_pre_enable_dp()
2839 						   to_intel_connector(conn_state->connector),  in tgl_ddi_pre_enable_dp()
2854 	 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle  in tgl_ddi_pre_enable_dp()
2869 		ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);  in tgl_ddi_pre_enable_dp()
2885 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in hsw_ddi_pre_enable_dp()
2886 	enum port port = encoder->port;  in hsw_ddi_pre_enable_dp()  local
2891 		drm_WARN_ON(&dev_priv->drm,  in hsw_ddi_pre_enable_dp()
2892 			    is_mst && (port == PORT_A || port == PORT_E));  in hsw_ddi_pre_enable_dp()
2894 		drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);  in hsw_ddi_pre_enable_dp()
2897 				 crtc_state->port_clock,  in hsw_ddi_pre_enable_dp()
2898 				 crtc_state->lane_count);  in hsw_ddi_pre_enable_dp()
2911 		drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);  in hsw_ddi_pre_enable_dp()
2912 		dig_port->ddi_io_wakeref = intel_display_power_get(display,  in hsw_ddi_pre_enable_dp()
2913 								   dig_port->ddi_io_power_domain);  in hsw_ddi_pre_enable_dp()
2921 	encoder->set_signal_levels(encoder, crtc_state);  in hsw_ddi_pre_enable_dp()
2930 						   to_intel_connector(conn_state->connector),  in hsw_ddi_pre_enable_dp()
2934 	if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) &&  in hsw_ddi_pre_enable_dp()
2981 	struct intel_hdmi *intel_hdmi = &dig_port->hdmi;  in intel_ddi_pre_enable_hdmi()
2982 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_ddi_pre_enable_hdmi()
2987 	drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);  in intel_ddi_pre_enable_hdmi()
2988 	dig_port->ddi_io_wakeref = intel_display_power_get(display,  in intel_ddi_pre_enable_hdmi()
2989 							   dig_port->ddi_io_power_domain);  in intel_ddi_pre_enable_hdmi()
2995 	dig_port->set_infoframes(encoder,  in intel_ddi_pre_enable_hdmi()
2996 				 crtc_state->has_infoframe,  in intel_ddi_pre_enable_hdmi()
3001  * Note: Also called from the ->pre_enable of the first active MST stream
3006  * - conn_state will be NULL
3008  * - encoder will be the primary encoder (i.e. mst->primary)
3010  * - the main connector associated with this port won't be active or linked to a
3013  * - crtc_state will be the state of the first stream to be activated on this
3014  *   port, and it may not be the same stream that will be deactivated last, but
3024 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_ddi_pre_enable()
3025 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_ddi_pre_enable()
3026 	enum pipe pipe = crtc->pipe;  in intel_ddi_pre_enable()
3028 	drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);  in intel_ddi_pre_enable()
3043 		if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp))  in intel_ddi_pre_enable()
3044 			dig_port->set_infoframes(encoder,  in intel_ddi_pre_enable()
3045 						 crtc_state->has_infoframe,  in intel_ddi_pre_enable()
3053 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in mtl_ddi_disable_d2d()
3054 	enum port port = encoder->port;  in mtl_ddi_disable_d2d()  local
3062 		reg = DDI_BUF_CTL(port);  in mtl_ddi_disable_d2d()
3066 		reg = XELPDP_PORT_BUF_CTL1(dev_priv, port);  in mtl_ddi_disable_d2d()
3073 		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n",  in mtl_ddi_disable_d2d()
3074 			port_name(port));  in mtl_ddi_disable_d2d()
3080 	enum port port = encoder->port;  in intel_ddi_buf_enable()  local
3082 	intel_de_write(display, DDI_BUF_CTL(port), buf_ctl | DDI_BUF_CTL_ENABLE);  in intel_ddi_buf_enable()
3083 	intel_de_posting_read(display, DDI_BUF_CTL(port));  in intel_ddi_buf_enable()
3092 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_ddi_buf_disable()
3093 	enum port port = encoder->port;  in intel_ddi_buf_disable()  local
3095 	intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);  in intel_ddi_buf_disable()
3098 		intel_wait_ddi_buf_idle(display, port);  in intel_ddi_buf_disable()
3110 		intel_wait_ddi_buf_idle(display, port);  in intel_ddi_buf_disable()
3121 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_ddi_post_disable_dp()
3123 	struct intel_dp *intel_dp = &dig_port->dp;  in intel_ddi_post_disable_dp()
3133 	 * Power down sink before disabling the port, otherwise we end  in intel_ddi_post_disable_dp()
3140 			enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;  in intel_ddi_post_disable_dp()
3159 	 * From TGL spec: "If single stream or multi-stream master transcoder:  in intel_ddi_post_disable_dp()
3169 	wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref);  in intel_ddi_post_disable_dp()
3173 					dig_port->ddi_io_power_domain,  in intel_ddi_post_disable_dp()
3178 	/* De-select Thunderbolt */  in intel_ddi_post_disable_dp()
3180 		intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, encoder->port),  in intel_ddi_post_disable_dp()
3190 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_ddi_post_disable_hdmi()
3192 	struct intel_hdmi *intel_hdmi = &dig_port->hdmi;  in intel_ddi_post_disable_hdmi()
3195 	dig_port->set_infoframes(encoder, false,  in intel_ddi_post_disable_hdmi()
3206 	wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref);  in intel_ddi_post_disable_hdmi()
3209 					dig_port->ddi_io_power_domain,  in intel_ddi_post_disable_hdmi()
3223 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_ddi_post_disable_hdmi_or_sst()
3241 		drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, 0);  in intel_ddi_post_disable_hdmi_or_sst()
3245 		intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder),  in intel_ddi_post_disable_hdmi_or_sst()
3249 		drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0);  in intel_ddi_post_disable_hdmi_or_sst()
3268  * Note: Also called from the ->post_disable of the last active MST stream
3283 	 * - old_conn_state will be NULL  in intel_ddi_post_disable()
3284 	 * - encoder will be the main encoder (ie. mst->primary)  in intel_ddi_post_disable()
3285 	 * - the main connector associated with this port  in intel_ddi_post_disable()
3287 	 * - old_crtc_state will be the state of the last stream to  in intel_ddi_post_disable()
3288 	 *   be deactivated on this port, and it may not be the same  in intel_ddi_post_disable()
3303  * Note: Also called from the ->post_pll_disable of the last active MST stream
3328 	if (!crtc_state->sync_mode_slaves_mask)  in trans_port_sync_stop_link_train()
3331 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in trans_port_sync_stop_link_train()
3333 			to_intel_encoder(conn_state->best_encoder);  in trans_port_sync_stop_link_train()
3334 		struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);  in trans_port_sync_stop_link_train()
3343 		if (slave_crtc_state->master_transcoder !=  in trans_port_sync_stop_link_train()
3344 		    crtc_state->cpu_transcoder)  in trans_port_sync_stop_link_train()
3362 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_ddi_enable_dp()
3365 	enum port port = encoder->port;  in intel_ddi_enable_dp()  local
3367 	if (port == PORT_A && DISPLAY_VER(dev_priv) < 9)  in intel_ddi_enable_dp()
3373 	if (!intel_lspcon_active(dig_port) || intel_dp_has_hdmi_sink(&dig_port->dp))  in intel_ddi_enable_dp()
3380 gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port)  in gen9_chicken_trans_reg_by_port()  argument
3390 	drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9);  in gen9_chicken_trans_reg_by_port()
3392 	if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E))  in gen9_chicken_trans_reg_by_port()
3393 		port = PORT_A;  in gen9_chicken_trans_reg_by_port()
3395 	return CHICKEN_TRANS(display, trans[port]);  in gen9_chicken_trans_reg_by_port()
3404 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_ddi_enable_hdmi()
3406 	struct drm_connector *connector = conn_state->connector;  in intel_ddi_enable_hdmi()
3407 	enum port port = encoder->port;  in intel_ddi_enable_hdmi()  local
3411 					       crtc_state->hdmi_high_tmds_clock_ratio,  in intel_ddi_enable_hdmi()
3412 					       crtc_state->hdmi_scrambling))  in intel_ddi_enable_hdmi()
3413 		drm_dbg_kms(&dev_priv->drm,  in intel_ddi_enable_hdmi()
3415 			    connector->base.id, connector->name);  in intel_ddi_enable_hdmi()
3423 	encoder->set_signal_levels(encoder, crtc_state);  in intel_ddi_enable_hdmi()
3430 		 * the bits affect a specific DDI port rather than  in intel_ddi_enable_hdmi()
3433 		i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port);  in intel_ddi_enable_hdmi()
3438 		if (port == PORT_E)  in intel_ddi_enable_hdmi()
3450 		if (port == PORT_E)  in intel_ddi_enable_hdmi()
3462 	/* In HDMI/DVI mode, the port width, and swing/emphasis values  in intel_ddi_enable_hdmi()
3464 	 * enabling the port.  in intel_ddi_enable_hdmi()
3473 	if (dig_port->lane_reversal)  in intel_ddi_enable_hdmi()
3475 	if (dig_port->ddi_a_4_lanes)  in intel_ddi_enable_hdmi()
3481 		port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count);  in intel_ddi_enable_hdmi()
3483 		if (dig_port->lane_reversal)  in intel_ddi_enable_hdmi()
3486 		intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port),  in intel_ddi_enable_hdmi()
3489 		buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count);  in intel_ddi_enable_hdmi()
3494 		drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));  in intel_ddi_enable_hdmi()
3508 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_ddi_enable()
3514 		const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_ddi_enable()
3515 		u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);  in intel_ddi_enable()
3538 		drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0);  in intel_ddi_enable()
3568 		to_intel_connector(old_conn_state->connector);  in intel_ddi_disable_dp()
3570 	intel_dp->link_trained = false;  in intel_ddi_disable_dp()
3587 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_ddi_disable_hdmi()
3588 	struct drm_connector *connector = old_conn_state->connector;  in intel_ddi_disable_hdmi()
3592 		drm_dbg_kms(&i915->drm,  in intel_ddi_disable_hdmi()
3594 			    connector->base.id, connector->name);  in intel_ddi_disable_hdmi()
3604 	intel_hdcp_disable(to_intel_connector(old_conn_state->connector));  in intel_ddi_disable()
3656 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_ddi_update_active_dpll()
3665 	for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc,  in intel_ddi_update_active_dpll()
3671  * Note: Also called from the ->pre_pll_enable of the first active MST stream
3681 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_ddi_pre_pll_enable()
3686 		struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_ddi_pre_pll_enable()
3688 		intel_tc_port_get_link(dig_port, crtc_state->lane_count);  in intel_ddi_pre_pll_enable()
3697 		 * Type-C ports.  Skip this step for TBT.  in intel_ddi_pre_pll_enable()
3699 		intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);  in intel_ddi_pre_pll_enable()
3702 						 crtc_state->lane_lat_optim_mask);  in intel_ddi_pre_pll_enable()
3721 	struct intel_encoder *encoder = &dig_port->base;  in mtl_ddi_prepare_link_retrain()
3726 	 * necessary disable and enable port  in mtl_ddi_prepare_link_retrain()
3730 	drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE);  in mtl_ddi_prepare_link_retrain()
3739 		if (crtc_state->enhanced_framing)  in mtl_ddi_prepare_link_retrain()
3749 	encoder->set_signal_levels(encoder, crtc_state);  in mtl_ddi_prepare_link_retrain()
3754 	/* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */  in mtl_ddi_prepare_link_retrain()
3756 		intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;  in mtl_ddi_prepare_link_retrain()
3758 	intel_ddi_buf_enable(encoder, intel_dp->DP);  in mtl_ddi_prepare_link_retrain()
3759 	intel_dp->DP |= DDI_BUF_CTL_ENABLE;  in mtl_ddi_prepare_link_retrain()
3767 	struct intel_encoder *encoder = &dig_port->base;  in intel_ddi_prepare_link_retrain()
3768 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_ddi_prepare_link_retrain()
3773 	drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE);  in intel_ddi_prepare_link_retrain()
3781 		if (crtc_state->enhanced_framing)  in intel_ddi_prepare_link_retrain()
3791 	intel_ddi_buf_enable(encoder, intel_dp->DP);  in intel_ddi_prepare_link_retrain()
3792 	intel_dp->DP |= DDI_BUF_CTL_ENABLE;  in intel_ddi_prepare_link_retrain()
3799 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_ddi_set_link_train()
3800 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_ddi_set_link_train()
3830 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_ddi_set_idle_link_train()
3831 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_ddi_set_idle_link_train()
3832 	enum port port = encoder->port;  in intel_ddi_set_idle_link_train()  local
3840 	 * issue where we enable the pipe while not in idle link-training mode.  in intel_ddi_set_idle_link_train()
3844 	if (port == PORT_A && DISPLAY_VER(dev_priv) < 12)  in intel_ddi_set_idle_link_train()
3850 		drm_err(&dev_priv->drm,  in intel_ddi_set_idle_link_train()
3857 	struct intel_display *display = &dev_priv->display;  in intel_ddi_is_audio_enabled()
3871 	if (crtc_state->port_clock > 594000)  in tgl_ddi_min_voltage_level()
3879 	if (crtc_state->port_clock > 594000)  in jsl_ddi_min_voltage_level()
3887 	if (crtc_state->port_clock > 594000)  in icl_ddi_min_voltage_level()
3895 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in intel_ddi_compute_min_voltage_level()
3898 		crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state);  in intel_ddi_compute_min_voltage_level()
3900 		crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state);  in intel_ddi_compute_min_voltage_level()
3902 		crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state);  in intel_ddi_compute_min_voltage_level()
3904 		crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state);  in intel_ddi_compute_min_voltage_level()
3933 		return master_select - 1;  in bdw_transcoder_master_readout()
3939 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in bdw_get_trans_port_sync_config()
3944 	crtc_state->master_transcoder =  in bdw_get_trans_port_sync_config()
3945 		bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder);  in bdw_get_trans_port_sync_config()
3959 		    crtc_state->cpu_transcoder)  in bdw_get_trans_port_sync_config()
3960 			crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);  in bdw_get_trans_port_sync_config()
3965 	drm_WARN_ON(&dev_priv->drm,  in bdw_get_trans_port_sync_config()
3966 		    crtc_state->master_transcoder != INVALID_TRANSCODER &&  in bdw_get_trans_port_sync_config()
3967 		    crtc_state->sync_mode_slaves_mask);  in bdw_get_trans_port_sync_config()
3976 	crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI);  in intel_ddi_read_func_ctl_dvi()
3978 		crtc_state->lane_count =  in intel_ddi_read_func_ctl_dvi()
3981 		crtc_state->lane_count = 4;  in intel_ddi_read_func_ctl_dvi()
3988 	crtc_state->has_hdmi_sink = true;  in intel_ddi_read_func_ctl_hdmi()
3990 	crtc_state->infoframes.enable |=  in intel_ddi_read_func_ctl_hdmi()
3993 	if (crtc_state->infoframes.enable)  in intel_ddi_read_func_ctl_hdmi()
3994 		crtc_state->has_infoframe = true;  in intel_ddi_read_func_ctl_hdmi()
3997 		crtc_state->hdmi_scrambling = true;  in intel_ddi_read_func_ctl_hdmi()
3999 		crtc_state->hdmi_high_tmds_clock_ratio = true;  in intel_ddi_read_func_ctl_hdmi()
4010 	crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG);  in intel_ddi_read_func_ctl_fdi()
4011 	crtc_state->enhanced_framing =  in intel_ddi_read_func_ctl_fdi()
4021 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_ddi_read_func_ctl_dp_sst()
4023 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_ddi_read_func_ctl_dp_sst()
4025 	if (encoder->type == INTEL_OUTPUT_EDP)  in intel_ddi_read_func_ctl_dp_sst()
4026 		crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP);  in intel_ddi_read_func_ctl_dp_sst()
4028 		crtc_state->output_types |= BIT(INTEL_OUTPUT_DP);  in intel_ddi_read_func_ctl_dp_sst()
4029 	crtc_state->lane_count =  in intel_ddi_read_func_ctl_dp_sst()
4034 		crtc_state->mst_master_transcoder =  in intel_ddi_read_func_ctl_dp_sst()
4037 	intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n);  in intel_ddi_read_func_ctl_dp_sst()
4038 	intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2);  in intel_ddi_read_func_ctl_dp_sst()
4040 	crtc_state->enhanced_framing =  in intel_ddi_read_func_ctl_dp_sst()
4045 		crtc_state->fec_enable =  in intel_ddi_read_func_ctl_dp_sst()
4049 	if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp))  in intel_ddi_read_func_ctl_dp_sst()
4050 		crtc_state->infoframes.enable |=  in intel_ddi_read_func_ctl_dp_sst()
4053 		crtc_state->infoframes.enable |=  in intel_ddi_read_func_ctl_dp_sst()
4062 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_ddi_read_func_ctl_dp_mst()
4063 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_ddi_read_func_ctl_dp_mst()
4065 	crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST);  in intel_ddi_read_func_ctl_dp_mst()
4066 	crtc_state->lane_count =  in intel_ddi_read_func_ctl_dp_mst()
4070 		crtc_state->mst_master_transcoder =  in intel_ddi_read_func_ctl_dp_mst()
4073 	intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n);  in intel_ddi_read_func_ctl_dp_mst()
4076 		crtc_state->fec_enable =  in intel_ddi_read_func_ctl_dp_mst()
4080 	crtc_state->infoframes.enable |=  in intel_ddi_read_func_ctl_dp_mst()
4088 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_ddi_read_func_ctl()
4089 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;  in intel_ddi_read_func_ctl()
4102 	pipe_config->hw.adjusted_mode.flags |= flags;  in intel_ddi_read_func_ctl()
4106 		pipe_config->pipe_bpp = 18;  in intel_ddi_read_func_ctl()
4109 		pipe_config->pipe_bpp = 24;  in intel_ddi_read_func_ctl()
4112 		pipe_config->pipe_bpp = 30;  in intel_ddi_read_func_ctl()
4115 		pipe_config->pipe_bpp = 36;  in intel_ddi_read_func_ctl()
4138 		 * encoder's ->get_config().  in intel_ddi_read_func_ctl()
4148  * Note: Also called from the ->get_config of the MST stream encoders on their
4155 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_ddi_get_config()
4156 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;  in intel_ddi_get_config()
4159 	if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))  in intel_ddi_get_config()
4166 	pipe_config->has_audio =  in intel_ddi_get_config()
4169 	if (encoder->type == INTEL_OUTPUT_EDP)  in intel_ddi_get_config()
4170 		intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp);  in intel_ddi_get_config()
4175 		pipe_config->lane_lat_optim_mask =  in intel_ddi_get_config()
4184 			     &pipe_config->infoframes.avi);  in intel_ddi_get_config()
4187 			     &pipe_config->infoframes.spd);  in intel_ddi_get_config()
4190 			     &pipe_config->infoframes.hdmi);  in intel_ddi_get_config()
4193 			     &pipe_config->infoframes.drm);  in intel_ddi_get_config()
4213 	struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];  in intel_ddi_get_clock()
4216 	if (drm_WARN_ON(display->drm, !pll))  in intel_ddi_get_clock()
4219 	port_dpll->pll = pll;  in intel_ddi_get_clock()
4220 	pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);  in intel_ddi_get_clock()
4221 	drm_WARN_ON(display->drm, !pll_active);  in intel_ddi_get_clock()
4225 	crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll,  in intel_ddi_get_clock()
4226 						     &crtc_state->dpll_hw_state);  in intel_ddi_get_clock()
4232 	intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll);  in mtl_ddi_get_config()
4234 	if (crtc_state->dpll_hw_state.cx0pll.tbt_mode)  in mtl_ddi_get_config()
4235 		crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);  in mtl_ddi_get_config()
4237 		crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);  in mtl_ddi_get_config()
4245 	intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb);  in dg2_ddi_get_config()
4246 	crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb);  in dg2_ddi_get_config()
4281 	return pll->info->id == DPLL_ID_ICL_TBTPLL;  in icl_ddi_tc_pll_is_tbt()
4288 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in icl_ddi_tc_port_pll_type()
4289 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;  in icl_ddi_tc_port_pll_type()
4291 	if (drm_WARN_ON(&i915->drm, !pll))  in icl_ddi_tc_port_pll_type()
4304 	if (!encoder->port_pll_type)  in intel_ddi_port_pll_type()
4307 	return encoder->port_pll_type(encoder, crtc_state);  in intel_ddi_port_pll_type()
4319 	if (drm_WARN_ON(display->drm, !pll))  in icl_ddi_tc_get_clock()
4327 	port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];  in icl_ddi_tc_get_clock()
4329 	port_dpll->pll = pll;  in icl_ddi_tc_get_clock()
4330 	pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);  in icl_ddi_tc_get_clock()
4331 	drm_WARN_ON(display->drm, !pll_active);  in icl_ddi_tc_get_clock()
4335 	if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll))  in icl_ddi_tc_get_clock()
4336 		crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port);  in icl_ddi_tc_get_clock()
4338 		crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll,  in icl_ddi_tc_get_clock()
4339 							     &crtc_state->dpll_hw_state);  in icl_ddi_tc_get_clock()
4385 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_ddi_initial_fastset_check()
4389 		drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n",  in intel_ddi_initial_fastset_check()
4390 			    encoder->base.base.id, encoder->base.name);  in intel_ddi_initial_fastset_check()
4391 		crtc_state->uapi.mode_changed = true;  in intel_ddi_initial_fastset_check()
4407 	switch (conn_state->connector->connector_type) {  in intel_ddi_compute_output_type()
4415 		MISSING_CASE(conn_state->connector->connector_type);  in intel_ddi_compute_output_type()
4424 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);  in intel_ddi_compute_config()
4425 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_ddi_compute_config()
4426 	enum port port = encoder->port;  in intel_ddi_compute_config()  local
4429 	if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)  in intel_ddi_compute_config()
4430 		pipe_config->cpu_transcoder = TRANSCODER_EDP;  in intel_ddi_compute_config()
4433 		pipe_config->has_hdmi_sink =  in intel_ddi_compute_config()
4444 	if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&  in intel_ddi_compute_config()
4445 	    pipe_config->cpu_transcoder == TRANSCODER_EDP)  in intel_ddi_compute_config()
4446 		pipe_config->pch_pfit.force_thru =  in intel_ddi_compute_config()
4447 			pipe_config->pch_pfit.enabled ||  in intel_ddi_compute_config()
4448 			pipe_config->crc_enabled;  in intel_ddi_compute_config()
4451 		pipe_config->lane_lat_optim_mask =  in intel_ddi_compute_config()
4452 			bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);  in intel_ddi_compute_config()
4466 		mode1->clock == mode2->clock; /* we want an exact match */  in mode_equal()
4472 	return m_n_1->tu == m_n_2->tu &&  in m_n_equal()
4473 		m_n_1->data_m == m_n_2->data_m &&  in m_n_equal()
4474 		m_n_1->data_n == m_n_2->data_n &&  in m_n_equal()
4475 		m_n_1->link_m == m_n_2->link_m &&  in m_n_equal()
4476 		m_n_1->link_n == m_n_2->link_n;  in m_n_equal()
4484 	 * can't deal with joiner + port sync at the same time.  in crtcs_port_sync_compatible()
4486 	return crtc_state1->hw.active && crtc_state2->hw.active &&  in crtcs_port_sync_compatible()
4487 		!crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes &&  in crtcs_port_sync_compatible()
4488 		crtc_state1->output_types == crtc_state2->output_types &&  in crtcs_port_sync_compatible()
4489 		crtc_state1->output_format == crtc_state2->output_format &&  in crtcs_port_sync_compatible()
4490 		crtc_state1->lane_count == crtc_state2->lane_count &&  in crtcs_port_sync_compatible()
4491 		crtc_state1->port_clock == crtc_state2->port_clock &&  in crtcs_port_sync_compatible()
4492 		mode_equal(&crtc_state1->hw.adjusted_mode,  in crtcs_port_sync_compatible()
4493 			   &crtc_state2->hw.adjusted_mode) &&  in crtcs_port_sync_compatible()
4494 		m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n);  in crtcs_port_sync_compatible()
4503 	struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev);  in intel_ddi_port_sync_transcoders()
4505 		to_intel_atomic_state(ref_crtc_state->uapi.state);  in intel_ddi_port_sync_transcoders()
4510 	 * We don't enable port sync on BDW due to missing w/as and  in intel_ddi_port_sync_transcoders()
4519 	for_each_new_connector_in_state(&state->base, connector, conn_state, i) {  in intel_ddi_port_sync_transcoders()
4520 		struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);  in intel_ddi_port_sync_transcoders()
4526 		if (!connector->has_tile ||  in intel_ddi_port_sync_transcoders()
4527 		    connector->tile_group->id !=  in intel_ddi_port_sync_transcoders()
4535 		transcoders |= BIT(crtc_state->cpu_transcoder);  in intel_ddi_port_sync_transcoders()
4545 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_ddi_compute_config_late()
4546 	struct drm_connector *connector = conn_state->connector;  in intel_ddi_compute_config_late()
4549 	drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n",  in intel_ddi_compute_config_late()
4550 		    encoder->base.base.id, encoder->base.name,  in intel_ddi_compute_config_late()
4551 		    crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);  in intel_ddi_compute_config_late()
4553 	if (connector->has_tile)  in intel_ddi_compute_config_late()
4555 									connector->tile_group->id);  in intel_ddi_compute_config_late()
4562 		crtc_state->master_transcoder = TRANSCODER_EDP;  in intel_ddi_compute_config_late()
4564 		crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;  in intel_ddi_compute_config_late()
4566 	if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {  in intel_ddi_compute_config_late()
4567 		crtc_state->master_transcoder = INVALID_TRANSCODER;  in intel_ddi_compute_config_late()
4568 		crtc_state->sync_mode_slaves_mask =  in intel_ddi_compute_config_late()
4569 			port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);  in intel_ddi_compute_config_late()
4577 	struct intel_display *display = to_intel_display(encoder->dev);  in intel_ddi_encoder_destroy()
4581 	if (intel_encoder_is_tc(&dig_port->base))  in intel_ddi_encoder_destroy()
4586 	kfree(dig_port->hdcp.port_data.streams);  in intel_ddi_encoder_destroy()
4595 	intel_dp->reset_link_params = true;  in intel_ddi_encoder_reset()
4600 	if (intel_encoder_is_tc(&dig_port->base))  in intel_ddi_encoder_reset()
4621 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);  in intel_ddi_init_dp_connector()
4623 	enum port port = dig_port->base.port;  in intel_ddi_init_dp_connector()  local
4627 		return -ENOMEM;  in intel_ddi_init_dp_connector()
4629 	dig_port->dp.output_reg = DDI_BUF_CTL(port);  in intel_ddi_init_dp_connector()
4631 		dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain;  in intel_ddi_init_dp_connector()
4633 		dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain;  in intel_ddi_init_dp_connector()
4634 	dig_port->dp.set_link_train = intel_ddi_set_link_train;  in intel_ddi_init_dp_connector()
4635 	dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;  in intel_ddi_init_dp_connector()
4637 	dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;  in intel_ddi_init_dp_connector()
4638 	dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;  in intel_ddi_init_dp_connector()
4642 		return -EINVAL;  in intel_ddi_init_dp_connector()
4645 	if (dig_port->base.type == INTEL_OUTPUT_EDP) {  in intel_ddi_init_dp_connector()
4646 		struct drm_device *dev = dig_port->base.base.dev;  in intel_ddi_init_dp_connector()
4649 		privacy_screen = drm_privacy_screen_get(dev->dev, NULL);  in intel_ddi_init_dp_connector()
4651 			drm_connector_attach_privacy_screen_provider(&connector->base,  in intel_ddi_init_dp_connector()
4653 		} else if (PTR_ERR(privacy_screen) != -ENODEV) {  in intel_ddi_init_dp_connector()
4654 			drm_warn(dev, "Error getting privacy-screen\n");  in intel_ddi_init_dp_connector()
4665 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_hdmi_reset_link()
4667 	struct intel_connector *connector = hdmi->attached_connector;  in intel_hdmi_reset_link()
4668 	struct i2c_adapter *ddc = connector->base.ddc;  in intel_hdmi_reset_link()
4675 	if (connector->base.status != connector_status_connected)  in intel_hdmi_reset_link()
4678 	ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,  in intel_hdmi_reset_link()
4683 	conn_state = connector->base.state;  in intel_hdmi_reset_link()
4685 	crtc = to_intel_crtc(conn_state->crtc);  in intel_hdmi_reset_link()
4689 	ret = drm_modeset_lock(&crtc->base.mutex, ctx);  in intel_hdmi_reset_link()
4693 	crtc_state = to_intel_crtc_state(crtc->base.state);  in intel_hdmi_reset_link()
4695 	drm_WARN_ON(&dev_priv->drm,  in intel_hdmi_reset_link()
4698 	if (!crtc_state->hw.active)  in intel_hdmi_reset_link()
4701 	if (!crtc_state->hdmi_high_tmds_clock_ratio &&  in intel_hdmi_reset_link()
4702 	    !crtc_state->hdmi_scrambling)  in intel_hdmi_reset_link()
4705 	if (conn_state->commit &&  in intel_hdmi_reset_link()
4706 	    !try_wait_for_completion(&conn_state->commit->hw_done))  in intel_hdmi_reset_link()
4711 		drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n",  in intel_hdmi_reset_link()
4712 			connector->base.base.id, connector->base.name, ret);  in intel_hdmi_reset_link()
4717 	    crtc_state->hdmi_high_tmds_clock_ratio &&  in intel_hdmi_reset_link()
4719 	    crtc_state->hdmi_scrambling)  in intel_hdmi_reset_link()
4731 	return intel_modeset_commit_pipes(display, BIT(crtc->pipe), ctx);  in intel_hdmi_reset_link()
4736 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_ddi_link_check()
4740 	drm_WARN_ON(&i915->drm, !dig_port->dp.attached_connector);  in intel_ddi_link_check()
4750 	struct intel_dp *intel_dp = &dig_port->dp;  in intel_ddi_hotplug()
4762 		if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) {  in intel_ddi_hotplug()
4765 			drm_WARN_ON(encoder->base.dev, ret);  in intel_ddi_hotplug()
4772 	 * Unpowered type-c dongles can take some time to boot and be  in intel_ddi_hotplug()
4787 	 * Type-c connectors which get their HPD signal deasserted then  in intel_ddi_hotplug()
4790 	 * becomes functional. Retry the detection for 5 seconds on type-c  in intel_ddi_hotplug()
4794 	    connector->hotplug_retries < (is_tc ? 5 : 1) &&  in intel_ddi_hotplug()
4795 	    !dig_port->dp.is_mst)  in intel_ddi_hotplug()
4803 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in lpt_digital_port_connected()
4804 	u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin];  in lpt_digital_port_connected()
4811 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in hsw_digital_port_connected()
4812 	u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];  in hsw_digital_port_connected()
4819 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in bdw_digital_port_connected()
4820 	u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];  in bdw_digital_port_connected()
4828 	enum port port = dig_port->base.port;  in intel_ddi_init_hdmi_connector()  local
4832 		return -ENOMEM;  in intel_ddi_init_hdmi_connector()
4834 	dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);  in intel_ddi_init_hdmi_connector()
4842 		dig_port->hdmi.hdmi_reg = INVALID_MMIO_REG;  in intel_ddi_init_hdmi_connector()
4851 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);  in intel_ddi_a_force_4_lanes()
4853 	if (dig_port->base.port != PORT_A)  in intel_ddi_a_force_4_lanes()
4856 	if (dig_port->ddi_a_4_lanes)  in intel_ddi_a_force_4_lanes()
4871 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);  in intel_ddi_max_lanes()
4872 	enum port port = dig_port->base.port;  in intel_ddi_max_lanes()  local
4878 	if (port == PORT_A || port == PORT_E) {  in intel_ddi_max_lanes()
4880 			max_lanes = port == PORT_A ? 4 : 0;  in intel_ddi_max_lanes()
4887 	 * Some BIOS might fail to set this bit on port A if eDP  in intel_ddi_max_lanes()
4892 		drm_dbg_kms(&dev_priv->drm,  in intel_ddi_max_lanes()
4893 			    "Forcing DDI_A_4_LANES for port A\n");  in intel_ddi_max_lanes()
4894 		dig_port->ddi_a_4_lanes = true;  in intel_ddi_max_lanes()
4902 				  enum port port)  in xelpd_hpd_pin()  argument
4904 	if (port >= PORT_D_XELPD)  in xelpd_hpd_pin()
4905 		return HPD_PORT_D + port - PORT_D_XELPD;  in xelpd_hpd_pin()
4906 	else if (port >= PORT_TC1)  in xelpd_hpd_pin()
4907 		return HPD_PORT_TC1 + port - PORT_TC1;  in xelpd_hpd_pin()
4909 		return HPD_PORT_A + port - PORT_A;  in xelpd_hpd_pin()
4913 				enum port port)  in dg1_hpd_pin()  argument
4915 	if (port >= PORT_TC1)  in dg1_hpd_pin()
4916 		return HPD_PORT_C + port - PORT_TC1;  in dg1_hpd_pin()
4918 		return HPD_PORT_A + port - PORT_A;  in dg1_hpd_pin()
4922 				enum port port)  in tgl_hpd_pin()  argument
4924 	if (port >= PORT_TC1)  in tgl_hpd_pin()
4925 		return HPD_PORT_TC1 + port - PORT_TC1;  in tgl_hpd_pin()
4927 		return HPD_PORT_A + port - PORT_A;  in tgl_hpd_pin()
4931 				enum port port)  in rkl_hpd_pin()  argument
4934 		return tgl_hpd_pin(dev_priv, port);  in rkl_hpd_pin()
4936 	if (port >= PORT_TC1)  in rkl_hpd_pin()
4937 		return HPD_PORT_C + port - PORT_TC1;  in rkl_hpd_pin()
4939 		return HPD_PORT_A + port - PORT_A;  in rkl_hpd_pin()
4943 				enum port port)  in icl_hpd_pin()  argument
4945 	if (port >= PORT_C)  in icl_hpd_pin()
4946 		return HPD_PORT_TC1 + port - PORT_C;  in icl_hpd_pin()
4948 		return HPD_PORT_A + port - PORT_A;  in icl_hpd_pin()
4952 				enum port port)  in ehl_hpd_pin()  argument
4954 	if (port == PORT_D)  in ehl_hpd_pin()
4958 		return icl_hpd_pin(dev_priv, port);  in ehl_hpd_pin()
4960 	return HPD_PORT_A + port - PORT_A;  in ehl_hpd_pin()
4963 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port)  in skl_hpd_pin()  argument
4966 		return icl_hpd_pin(dev_priv, port);  in skl_hpd_pin()
4968 	return HPD_PORT_A + port - PORT_A;  in skl_hpd_pin()
4971 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port)  in intel_ddi_is_tc()  argument
4974 		return port >= PORT_TC1;  in intel_ddi_is_tc()
4976 		return port >= PORT_C;  in intel_ddi_is_tc()
5015 #define port_tc_name(port) ((port) - PORT_TC1 + '1')  argument
5016 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
5018 static bool port_strap_detected(struct drm_i915_private *i915, enum port port)  in port_strap_detected()  argument
5024 	switch (port) {  in port_strap_detected()
5034 		return true; /* no strap for DDI-E */  in port_strap_detected()
5036 		MISSING_CASE(port);  in port_strap_detected()
5048 	return !drm_WARN(&i915->drm, !IS_ALDERLAKE_P(i915) &&  in assert_has_icl_dsi()
5053 static bool port_in_use(struct drm_i915_private *i915, enum port port)  in port_in_use()  argument
5057 	for_each_intel_encoder(&i915->drm, encoder) {  in port_in_use()
5058 		/* FIXME what about second port for dual link DSI? */  in port_in_use()
5059 		if (encoder->port == port)  in port_in_use()
5069 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in intel_ddi_init()
5073 	enum port port;  in intel_ddi_init()  local
5077 	port = intel_bios_encoder_port(devdata);  in intel_ddi_init()
5078 	if (port == PORT_NONE)  in intel_ddi_init()
5081 	if (!port_strap_detected(dev_priv, port)) {  in intel_ddi_init()
5082 		drm_dbg_kms(&dev_priv->drm,  in intel_ddi_init()
5083 			    "Port %c strap not detected\n", port_name(port));  in intel_ddi_init()
5087 	if (!assert_port_valid(display, port))  in intel_ddi_init()
5090 	if (port_in_use(dev_priv, port)) {  in intel_ddi_init()
5091 		drm_dbg_kms(&dev_priv->drm,  in intel_ddi_init()
5092 			    "Port %c already claimed\n", port_name(port));  in intel_ddi_init()
5105 	phy = intel_port_to_phy(display, port);  in intel_ddi_init()
5114 		drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n",  in intel_ddi_init()
5115 			    port_name(port), phy_name(phy));  in intel_ddi_init()
5131 		drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n",  in intel_ddi_init()
5132 			    port_name(port));  in intel_ddi_init()
5136 		drm_dbg_kms(&dev_priv->drm,  in intel_ddi_init()
5137 			    "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",  in intel_ddi_init()
5138 			    port_name(port));  in intel_ddi_init()
5143 	    dev_priv->display.snps.phy_failed_calibration & BIT(phy)) {  in intel_ddi_init()
5144 		drm_dbg_kms(&dev_priv->drm,  in intel_ddi_init()
5153 	dig_port->aux_ch = AUX_CH_NONE;  in intel_ddi_init()
5155 	encoder = &dig_port->base;  in intel_ddi_init()
5156 	encoder->devdata = devdata;  in intel_ddi_init()
5158 	if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) {  in intel_ddi_init()
5159 		drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,  in intel_ddi_init()
5162 				 port_name(port - PORT_D_XELPD + PORT_D),  in intel_ddi_init()
5165 		enum tc_port tc_port = intel_port_to_tc(display, port);  in intel_ddi_init()
5167 		drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,  in intel_ddi_init()
5170 				 port >= PORT_TC1 ? "TC" : "",  in intel_ddi_init()
5171 				 port >= PORT_TC1 ? port_tc_name(port) : port_name(port),  in intel_ddi_init()
5175 		enum tc_port tc_port = intel_port_to_tc(display, port);  in intel_ddi_init()
5177 		drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,  in intel_ddi_init()
5180 				 port_name(port),  in intel_ddi_init()
5181 				 port >= PORT_C ? " (TC)" : "",  in intel_ddi_init()
5185 		drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,  in intel_ddi_init()
5187 				 "DDI %c/PHY %c", port_name(port), phy_name(phy));  in intel_ddi_init()
5192 	mutex_init(&dig_port->hdcp.mutex);  in intel_ddi_init()
5193 	dig_port->hdcp.num_streams = 0;  in intel_ddi_init()
5195 	encoder->hotplug = intel_ddi_hotplug;  in intel_ddi_init()
5196 	encoder->compute_output_type = intel_ddi_compute_output_type;  in intel_ddi_init()
5197 	encoder->compute_config = intel_ddi_compute_config;  in intel_ddi_init()
5198 	encoder->compute_config_late = intel_ddi_compute_config_late;  in intel_ddi_init()
5199 	encoder->enable = intel_ddi_enable;  in intel_ddi_init()
5200 	encoder->pre_pll_enable = intel_ddi_pre_pll_enable;  in intel_ddi_init()
5201 	encoder->pre_enable = intel_ddi_pre_enable;  in intel_ddi_init()
5202 	encoder->disable = intel_ddi_disable;  in intel_ddi_init()
5203 	encoder->post_pll_disable = intel_ddi_post_pll_disable;  in intel_ddi_init()
5204 	encoder->post_disable = intel_ddi_post_disable;  in intel_ddi_init()
5205 	encoder->update_pipe = intel_ddi_update_pipe;  in intel_ddi_init()
5206 	encoder->audio_enable = intel_audio_codec_enable;  in intel_ddi_init()
5207 	encoder->audio_disable = intel_audio_codec_disable;  in intel_ddi_init()
5208 	encoder->get_hw_state = intel_ddi_get_hw_state;  in intel_ddi_init()
5209 	encoder->sync_state = intel_ddi_sync_state;  in intel_ddi_init()
5210 	encoder->initial_fastset_check = intel_ddi_initial_fastset_check;  in intel_ddi_init()
5211 	encoder->suspend = intel_ddi_encoder_suspend;  in intel_ddi_init()
5212 	encoder->shutdown = intel_ddi_encoder_shutdown;  in intel_ddi_init()
5213 	encoder->get_power_domains = intel_ddi_get_power_domains;  in intel_ddi_init()
5215 	encoder->type = INTEL_OUTPUT_DDI;  in intel_ddi_init()
5216 	encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port);  in intel_ddi_init()
5217 	encoder->port = port;  in intel_ddi_init()
5218 	encoder->cloneable = 0;  in intel_ddi_init()
5219 	encoder->pipe_mask = ~0;  in intel_ddi_init()
5222 		encoder->enable_clock = intel_mtl_pll_enable;  in intel_ddi_init()
5223 		encoder->disable_clock = intel_mtl_pll_disable;  in intel_ddi_init()
5224 		encoder->port_pll_type = intel_mtl_port_pll_type;  in intel_ddi_init()
5225 		encoder->get_config = mtl_ddi_get_config;  in intel_ddi_init()
5227 		encoder->enable_clock = intel_mpllb_enable;  in intel_ddi_init()
5228 		encoder->disable_clock = intel_mpllb_disable;  in intel_ddi_init()
5229 		encoder->get_config = dg2_ddi_get_config;  in intel_ddi_init()
5231 		encoder->enable_clock = adls_ddi_enable_clock;  in intel_ddi_init()
5232 		encoder->disable_clock = adls_ddi_disable_clock;  in intel_ddi_init()
5233 		encoder->is_clock_enabled = adls_ddi_is_clock_enabled;  in intel_ddi_init()
5234 		encoder->get_config = adls_ddi_get_config;  in intel_ddi_init()
5236 		encoder->enable_clock = rkl_ddi_enable_clock;  in intel_ddi_init()
5237 		encoder->disable_clock = rkl_ddi_disable_clock;  in intel_ddi_init()
5238 		encoder->is_clock_enabled = rkl_ddi_is_clock_enabled;  in intel_ddi_init()
5239 		encoder->get_config = rkl_ddi_get_config;  in intel_ddi_init()
5241 		encoder->enable_clock = dg1_ddi_enable_clock;  in intel_ddi_init()
5242 		encoder->disable_clock = dg1_ddi_disable_clock;  in intel_ddi_init()
5243 		encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;  in intel_ddi_init()
5244 		encoder->get_config = dg1_ddi_get_config;  in intel_ddi_init()
5246 		if (intel_ddi_is_tc(dev_priv, port)) {  in intel_ddi_init()
5247 			encoder->enable_clock = jsl_ddi_tc_enable_clock;  in intel_ddi_init()
5248 			encoder->disable_clock = jsl_ddi_tc_disable_clock;  in intel_ddi_init()
5249 			encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled;  in intel_ddi_init()
5250 			encoder->port_pll_type = icl_ddi_tc_port_pll_type;  in intel_ddi_init()
5251 			encoder->get_config = icl_ddi_combo_get_config;  in intel_ddi_init()
5253 			encoder->enable_clock = icl_ddi_combo_enable_clock;  in intel_ddi_init()
5254 			encoder->disable_clock = icl_ddi_combo_disable_clock;  in intel_ddi_init()
5255 			encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;  in intel_ddi_init()
5256 			encoder->get_config = icl_ddi_combo_get_config;  in intel_ddi_init()
5259 		if (intel_ddi_is_tc(dev_priv, port)) {  in intel_ddi_init()
5260 			encoder->enable_clock = icl_ddi_tc_enable_clock;  in intel_ddi_init()
5261 			encoder->disable_clock = icl_ddi_tc_disable_clock;  in intel_ddi_init()
5262 			encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled;  in intel_ddi_init()
5263 			encoder->port_pll_type = icl_ddi_tc_port_pll_type;  in intel_ddi_init()
5264 			encoder->get_config = icl_ddi_tc_get_config;  in intel_ddi_init()
5266 			encoder->enable_clock = icl_ddi_combo_enable_clock;  in intel_ddi_init()
5267 			encoder->disable_clock = icl_ddi_combo_disable_clock;  in intel_ddi_init()
5268 			encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;  in intel_ddi_init()
5269 			encoder->get_config = icl_ddi_combo_get_config;  in intel_ddi_init()
5272 		/* BXT/GLK have fixed PLL->port mapping */  in intel_ddi_init()
5273 		encoder->get_config = bxt_ddi_get_config;  in intel_ddi_init()
5275 		encoder->enable_clock = skl_ddi_enable_clock;  in intel_ddi_init()
5276 		encoder->disable_clock = skl_ddi_disable_clock;  in intel_ddi_init()
5277 		encoder->is_clock_enabled = skl_ddi_is_clock_enabled;  in intel_ddi_init()
5278 		encoder->get_config = skl_ddi_get_config;  in intel_ddi_init()
5280 		encoder->enable_clock = hsw_ddi_enable_clock;  in intel_ddi_init()
5281 		encoder->disable_clock = hsw_ddi_disable_clock;  in intel_ddi_init()
5282 		encoder->is_clock_enabled = hsw_ddi_is_clock_enabled;  in intel_ddi_init()
5283 		encoder->get_config = hsw_ddi_get_config;  in intel_ddi_init()
5287 		encoder->set_signal_levels = intel_cx0_phy_set_signal_levels;  in intel_ddi_init()
5289 		encoder->set_signal_levels = intel_snps_phy_set_signal_levels;  in intel_ddi_init()
5292 			encoder->set_signal_levels = icl_combo_phy_set_signal_levels;  in intel_ddi_init()
5294 			encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels;  in intel_ddi_init()
5297 			encoder->set_signal_levels = icl_combo_phy_set_signal_levels;  in intel_ddi_init()
5299 			encoder->set_signal_levels = icl_mg_phy_set_signal_levels;  in intel_ddi_init()
5301 		encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels;  in intel_ddi_init()
5303 		encoder->set_signal_levels = hsw_set_signal_levels;  in intel_ddi_init()
5309 		encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port);  in intel_ddi_init()
5311 		encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);  in intel_ddi_init()
5313 		encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);  in intel_ddi_init()
5315 		encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);  in intel_ddi_init()
5317 		encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);  in intel_ddi_init()
5319 		encoder->hpd_pin = icl_hpd_pin(dev_priv, port);  in intel_ddi_init()
5321 		encoder->hpd_pin = skl_hpd_pin(dev_priv, port);  in intel_ddi_init()
5323 		encoder->hpd_pin = intel_hpd_pin_default(port);  in intel_ddi_init()
5325 	ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));  in intel_ddi_init()
5327 	dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) ||  in intel_ddi_init()
5330 	dig_port->ddi_a_4_lanes = DISPLAY_VER(dev_priv) < 11 && ddi_buf_ctl & DDI_A_4_LANES;  in intel_ddi_init()
5332 	dig_port->dp.output_reg = INVALID_MMIO_REG;  in intel_ddi_init()
5333 	dig_port->max_lanes = intel_ddi_max_lanes(dig_port);  in intel_ddi_init()
5336 		dig_port->aux_ch = intel_dp_aux_ch(encoder);  in intel_ddi_init()
5337 		if (dig_port->aux_ch == AUX_CH_NONE)  in intel_ddi_init()
5349 			drm_dbg_kms(&dev_priv->drm,  in intel_ddi_init()
5350 				    "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n",  in intel_ddi_init()
5351 				    port_name(port),  in intel_ddi_init()
5353 				    is_legacy ? "legacy" : "non-legacy");  in intel_ddi_init()
5356 		encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete;  in intel_ddi_init()
5357 		encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete;  in intel_ddi_init()
5359 		dig_port->lock = intel_tc_port_lock;  in intel_ddi_init()
5360 		dig_port->unlock = intel_tc_port_unlock;  in intel_ddi_init()
5366 	drm_WARN_ON(&dev_priv->drm, port > PORT_I);  in intel_ddi_init()
5367 	dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(display, port);  in intel_ddi_init()
5371 			dig_port->connected = intel_tc_port_connected;  in intel_ddi_init()
5373 			dig_port->connected = lpt_digital_port_connected;  in intel_ddi_init()
5375 		dig_port->connected = bdw_digital_port_connected;  in intel_ddi_init()
5377 		dig_port->connected = lpt_digital_port_connected;  in intel_ddi_init()
5379 		if (port == PORT_A)  in intel_ddi_init()
5380 			dig_port->connected = bdw_digital_port_connected;  in intel_ddi_init()
5382 			dig_port->connected = lpt_digital_port_connected;  in intel_ddi_init()
5384 		if (port == PORT_A)  in intel_ddi_init()
5385 			dig_port->connected = hsw_digital_port_connected;  in intel_ddi_init()
5387 			dig_port->connected = lpt_digital_port_connected;  in intel_ddi_init()
5396 		dig_port->hpd_pulse = intel_dp_hpd_pulse;  in intel_ddi_init()
5398 		if (dig_port->dp.mso_link_count)  in intel_ddi_init()
5399 			encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv);  in intel_ddi_init()
5403 	 * In theory we don't need the encoder->type check,  in intel_ddi_init()
5406 	if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {  in intel_ddi_init()
5414 	drm_encoder_cleanup(&encoder->base);  in intel_ddi_init()