Lines Matching +full:hdmi +full:- +full:dp2

108 	level = intel_bios_hdmi_level_shift(encoder->devdata);  in intel_ddi_hdmi_level()
110 level = trans->hdmi_default_entry; in intel_ddi_hdmi_level()
117 return DISPLAY_VER(display) < 10 && !display->platform.broxton; in has_buf_trans_select()
122 return DISPLAY_VER(display) == 9 && !display->platform.broxton; in has_iboost()
136 enum port port = encoder->port; in hsw_prepare_dp_ddi_buffers()
139 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in hsw_prepare_dp_ddi_buffers()
140 if (drm_WARN_ON_ONCE(display->drm, !trans)) in hsw_prepare_dp_ddi_buffers()
145 intel_bios_dp_boost_level(encoder->devdata)) in hsw_prepare_dp_ddi_buffers()
150 trans->entries[i].hsw.trans1 | iboost_bit); in hsw_prepare_dp_ddi_buffers()
152 trans->entries[i].hsw.trans2); in hsw_prepare_dp_ddi_buffers()
159 * HDMI/DVI use cases.
168 enum port port = encoder->port; in hsw_prepare_hdmi_ddi_buffers()
171 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in hsw_prepare_hdmi_ddi_buffers()
172 if (drm_WARN_ON_ONCE(display->drm, !trans)) in hsw_prepare_hdmi_ddi_buffers()
177 intel_bios_hdmi_boost_level(encoder->devdata)) in hsw_prepare_hdmi_ddi_buffers()
180 /* Entry 9 is for HDMI: */ in hsw_prepare_hdmi_ddi_buffers()
182 trans->entries[level].hsw.trans1 | iboost_bit); in hsw_prepare_hdmi_ddi_buffers()
184 trans->entries[level].hsw.trans2); in hsw_prepare_hdmi_ddi_buffers()
201 * HSW-ADL: 8 us in intel_wait_ddi_buf_idle()
205 if (display->platform.broxton) { in intel_wait_ddi_buf_idle()
213 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n", in intel_wait_ddi_buf_idle()
220 enum port port = encoder->port; in intel_wait_ddi_buf_active()
226 * TGL-ADL combo PHY: 1000 us in intel_wait_ddi_buf_active()
227 * TGL-ADL TypeC PHY: 3000 us in intel_wait_ddi_buf_active()
228 * HSW-ICL : fixed 518 us in intel_wait_ddi_buf_active()
238 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n", in intel_wait_ddi_buf_active()
244 switch (pll->info->id) { in hsw_pll_to_ddi_pll_sel()
258 MISSING_CASE(pll->info->id); in hsw_pll_to_ddi_pll_sel()
266 const struct intel_dpll *pll = crtc_state->intel_dpll; in icl_pll_to_ddi_clk_sel()
267 int clock = crtc_state->port_clock; in icl_pll_to_ddi_clk_sel()
268 const enum intel_dpll_id id = pll->info->id; in icl_pll_to_ddi_clk_sel()
342 * port_clock (10 kHz) -> bits / 100 us in dp_phy_lane_stagger_delay()
343 * / symbol_size -> symbols / 100 us in dp_phy_lane_stagger_delay()
344 * / 1000 -> symbols / 100 ns in dp_phy_lane_stagger_delay()
357 intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) | in intel_ddi_init_dp_buf_reg()
360 if (dig_port->lane_reversal) in intel_ddi_init_dp_buf_reg()
361 intel_dp->DP |= DDI_BUF_PORT_REVERSAL; in intel_ddi_init_dp_buf_reg()
362 if (dig_port->ddi_a_4_lanes) in intel_ddi_init_dp_buf_reg()
363 intel_dp->DP |= DDI_A_4_LANES; in intel_ddi_init_dp_buf_reg()
367 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; in intel_ddi_init_dp_buf_reg()
369 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; in intel_ddi_init_dp_buf_reg()
372 if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { in intel_ddi_init_dp_buf_reg()
373 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); in intel_ddi_init_dp_buf_reg()
375 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; in intel_ddi_init_dp_buf_reg()
379 int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock); in intel_ddi_init_dp_buf_reg()
381 intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay); in intel_ddi_init_dp_buf_reg()
409 if (pipe_config->has_pch_encoder) in ddi_dotclock_get()
412 pipe_config->hw.adjusted_mode.crtc_clock = in ddi_dotclock_get()
420 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_set_dp_msa()
426 drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)); in intel_ddi_set_dp_msa()
430 switch (crtc_state->pipe_bpp) { in intel_ddi_set_dp_msa()
444 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_set_dp_msa()
449 drm_WARN_ON(display->drm, crtc_state->limited_color_range && in intel_ddi_set_dp_msa()
450 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); in intel_ddi_set_dp_msa()
452 if (crtc_state->limited_color_range) in intel_ddi_set_dp_msa()
460 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) in intel_ddi_set_dp_msa()
489 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_config_transcoder_dp2()
512 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_transcoder_func_reg_val_get()
513 enum pipe pipe = crtc->pipe; in intel_ddi_transcoder_func_reg_val_get()
514 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_transcoder_func_reg_val_get()
515 enum port port = encoder->port; in intel_ddi_transcoder_func_reg_val_get()
518 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ in intel_ddi_transcoder_func_reg_val_get()
525 switch (crtc_state->pipe_bpp) { in intel_ddi_transcoder_func_reg_val_get()
527 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_transcoder_func_reg_val_get()
543 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) in intel_ddi_transcoder_func_reg_val_get()
545 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) in intel_ddi_transcoder_func_reg_val_get()
554 /* On Haswell, can only use the always-on power well for in intel_ddi_transcoder_func_reg_val_get()
558 if (crtc_state->pch_pfit.force_thru) in intel_ddi_transcoder_func_reg_val_get()
573 if (crtc_state->has_hdmi_sink) in intel_ddi_transcoder_func_reg_val_get()
578 if (crtc_state->hdmi_scrambling) in intel_ddi_transcoder_func_reg_val_get()
580 if (crtc_state->hdmi_high_tmds_clock_ratio) in intel_ddi_transcoder_func_reg_val_get()
583 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_transcoder_func_reg_val_get()
586 temp |= (crtc_state->fdi_lanes - 1) << 1; in intel_ddi_transcoder_func_reg_val_get()
593 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_transcoder_func_reg_val_get()
598 master = crtc_state->mst_master_transcoder; in intel_ddi_transcoder_func_reg_val_get()
599 drm_WARN_ON(display->drm, in intel_ddi_transcoder_func_reg_val_get()
605 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_transcoder_func_reg_val_get()
609 crtc_state->master_transcoder != INVALID_TRANSCODER) { in intel_ddi_transcoder_func_reg_val_get()
611 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); in intel_ddi_transcoder_func_reg_val_get()
624 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_enable_transcoder_func()
627 enum transcoder master_transcoder = crtc_state->master_transcoder; in intel_ddi_enable_transcoder_func()
650 * bit for the DDI function and enables the DP2 configuration. Called for all
658 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_config_transcoder_func()
671 * For SST, pre-TGL MST, TGL+ MST-slave transcoders: deselect the DDI port,
672 * SST/MST mode and disable the DP2 configuration. For TGL+ MST-master
678 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_disable_transcoder_func()
679 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_disable_transcoder_func()
690 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); in intel_ddi_disable_transcoder_func()
715 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); in intel_ddi_disable_transcoder_func()
730 intel_encoder->power_domain); in intel_ddi_toggle_hdcp_bits()
731 if (drm_WARN_ON(display->drm, !wakeref)) in intel_ddi_toggle_hdcp_bits()
732 return -ENXIO; in intel_ddi_toggle_hdcp_bits()
736 intel_display_power_put(display, intel_encoder->power_domain, wakeref); in intel_ddi_toggle_hdcp_bits()
744 int type = intel_connector->base.connector_type; in intel_ddi_connector_get_hw_state()
745 enum port port = encoder->port; in intel_ddi_connector_get_hw_state()
753 encoder->power_domain); in intel_ddi_connector_get_hw_state()
758 if (!encoder->get_hw_state(encoder, &pipe)) { in intel_ddi_connector_get_hw_state()
781 * encoder->get_hw_state() should have bailed out on MST. This in intel_ddi_connector_get_hw_state()
782 * must be SST and non-eDP. in intel_ddi_connector_get_hw_state()
785 } else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) { in intel_ddi_connector_get_hw_state()
786 /* encoder->get_hw_state() should have bailed out on MST. */ in intel_ddi_connector_get_hw_state()
793 intel_display_power_put(display, encoder->power_domain, wakeref); in intel_ddi_connector_get_hw_state()
802 enum port port = encoder->port; in intel_ddi_get_encoder_pipes()
812 encoder->power_domain); in intel_ddi_get_encoder_pipes()
880 drm_dbg_kms(display->drm, in intel_ddi_get_encoder_pipes()
882 encoder->base.base.id, encoder->base.name); in intel_ddi_get_encoder_pipes()
903 drm_dbg_kms(display->drm, in intel_ddi_get_encoder_pipes()
905 encoder->base.base.id, encoder->base.name, in intel_ddi_get_encoder_pipes()
907 *pipe_mask = BIT(ffs(*pipe_mask) - 1); in intel_ddi_get_encoder_pipes()
911 drm_dbg_kms(display->drm, in intel_ddi_get_encoder_pipes()
912 …"Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b … in intel_ddi_get_encoder_pipes()
913 encoder->base.base.id, encoder->base.name, in intel_ddi_get_encoder_pipes()
919 if (*pipe_mask && (display->platform.geminilake || display->platform.broxton)) { in intel_ddi_get_encoder_pipes()
924 drm_err(display->drm, in intel_ddi_get_encoder_pipes()
926 encoder->base.base.id, encoder->base.name, tmp); in intel_ddi_get_encoder_pipes()
929 intel_display_power_put(display, encoder->power_domain, wakeref); in intel_ddi_get_encoder_pipes()
943 *pipe = ffs(pipe_mask) - 1; in intel_ddi_get_hw_state()
961 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require in intel_ddi_main_link_aux_domain()
967 if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state)) in intel_ddi_main_link_aux_domain()
968 return intel_display_power_aux_io_domain(display, dig_port->aux_ch); in intel_ddi_main_link_aux_domain()
971 intel_encoder_is_tc(&dig_port->base))) in intel_ddi_main_link_aux_domain()
985 drm_WARN_ON(display->drm, dig_port->aux_wakeref); in main_link_aux_power_domain_get()
990 dig_port->aux_wakeref = intel_display_power_get(display, domain); in main_link_aux_power_domain_get()
1002 wf = fetch_and_zero(&dig_port->aux_wakeref); in main_link_aux_power_domain_put()
1017 * happen since fake-MST encoders don't set their get_power_domains() in intel_ddi_get_power_domains()
1020 if (drm_WARN_ON(display->drm, in intel_ddi_get_power_domains()
1027 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); in intel_ddi_get_power_domains()
1028 dig_port->ddi_io_wakeref = intel_display_power_get(display, in intel_ddi_get_power_domains()
1029 dig_port->ddi_io_power_domain); in intel_ddi_get_power_domains()
1039 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_enable_transcoder_clock()
1049 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); in intel_ddi_enable_transcoder_clock()
1051 val = TRANS_CLK_SEL_PORT(encoder->port); in intel_ddi_enable_transcoder_clock()
1059 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_disable_transcoder_clock()
1096 iboost = intel_bios_hdmi_boost_level(encoder->devdata); in skl_ddi_set_iboost()
1098 iboost = intel_bios_dp_boost_level(encoder->devdata); in skl_ddi_set_iboost()
1104 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in skl_ddi_set_iboost()
1105 if (drm_WARN_ON_ONCE(display->drm, !trans)) in skl_ddi_set_iboost()
1108 iboost = trans->entries[level].hsw.i_boost; in skl_ddi_set_iboost()
1113 drm_err(display->drm, "Invalid I_boost value %u\n", iboost); in skl_ddi_set_iboost()
1117 _skl_ddi_set_iboost(display, encoder->port, iboost); in skl_ddi_set_iboost()
1119 if (encoder->port == PORT_A && dig_port->max_lanes == 4) in skl_ddi_set_iboost()
1127 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_ddi_dp_voltage_max()
1130 encoder->get_buf_trans(encoder, crtc_state, &n_entries); in intel_ddi_dp_voltage_max()
1132 if (drm_WARN_ON(display->drm, n_entries < 1)) in intel_ddi_dp_voltage_max()
1134 if (drm_WARN_ON(display->drm, in intel_ddi_dp_voltage_max()
1138 return index_to_dp_signal_levels[n_entries - 1] & in intel_ddi_dp_voltage_max()
1143 * We assume that the full set of pre-emphasis values can be
1155 if (crtc_state->port_clock > 600000) in icl_combo_phy_loadgen_select()
1158 if (crtc_state->lane_count == 4) in icl_combo_phy_loadgen_select()
1173 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in icl_ddi_combo_vswing_program()
1174 if (drm_WARN_ON_ONCE(display->drm, !trans)) in icl_ddi_combo_vswing_program()
1181 intel_dp->hobl_active = is_hobl_buf_trans(trans); in icl_ddi_combo_vswing_program()
1183 intel_dp->hobl_active ? val : 0); in icl_ddi_combo_vswing_program()
1202 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | in icl_ddi_combo_vswing_program()
1203 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | in icl_ddi_combo_vswing_program()
1214 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | in icl_ddi_combo_vswing_program()
1215 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | in icl_ddi_combo_vswing_program()
1216 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); in icl_ddi_combo_vswing_program()
1225 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); in icl_ddi_combo_vswing_program()
1271 /* 5. Program swing and de-emphasis */ in icl_combo_phy_set_signal_levels()
1291 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in icl_mg_phy_set_signal_levels()
1292 if (drm_WARN_ON_ONCE(display->drm, !trans)) in icl_mg_phy_set_signal_levels()
1310 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); in icl_mg_phy_set_signal_levels()
1316 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); in icl_mg_phy_set_signal_levels()
1328 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | in icl_mg_phy_set_signal_levels()
1329 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | in icl_mg_phy_set_signal_levels()
1337 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | in icl_mg_phy_set_signal_levels()
1338 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | in icl_mg_phy_set_signal_levels()
1352 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); in icl_mg_phy_set_signal_levels()
1360 crtc_state->port_clock > 500000 ? in icl_mg_phy_set_signal_levels()
1367 crtc_state->port_clock > 500000 ? in icl_mg_phy_set_signal_levels()
1392 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in tgl_dkl_phy_set_signal_levels()
1393 if (drm_WARN_ON_ONCE(display->drm, !trans)) in tgl_dkl_phy_set_signal_levels()
1399 /* Wa_16011342517:adl-p */ in tgl_dkl_phy_set_signal_levels()
1400 if (display->platform.alderlake_p && in tgl_dkl_phy_set_signal_levels()
1403 crtc_state->port_clock == 594000) || in tgl_dkl_phy_set_signal_levels()
1405 crtc_state->port_clock == 162000)) { in tgl_dkl_phy_set_signal_levels()
1422 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | in tgl_dkl_phy_set_signal_levels()
1423 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | in tgl_dkl_phy_set_signal_levels()
1424 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); in tgl_dkl_phy_set_signal_levels()
1432 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | in tgl_dkl_phy_set_signal_levels()
1433 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | in tgl_dkl_phy_set_signal_levels()
1434 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); in tgl_dkl_phy_set_signal_levels()
1439 if (display->platform.alderlake_p) { in tgl_dkl_phy_set_signal_levels()
1474 drm_WARN(display->drm, 1, in translate_signal_level()
1475 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", in translate_signal_level()
1485 u8 train_set = intel_dp->train_set[lane]; in intel_ddi_dp_level()
1505 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in intel_ddi_level()
1506 if (drm_WARN_ON_ONCE(display->drm, !trans)) in intel_ddi_level()
1515 if (drm_WARN_ON_ONCE(display->drm, level >= n_entries)) in intel_ddi_level()
1516 level = n_entries - 1; in intel_ddi_level()
1528 enum port port = encoder->port; in hsw_set_signal_levels()
1534 /* HDMI ignores the rest */ in hsw_set_signal_levels()
1540 drm_dbg_kms(display->drm, "Using signal levels %08x\n", in hsw_set_signal_levels()
1543 intel_dp->DP &= ~DDI_BUF_EMP_MASK; in hsw_set_signal_levels()
1544 intel_dp->DP |= signal_levels; in hsw_set_signal_levels()
1546 intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP); in hsw_set_signal_levels()
1553 mutex_lock(&display->dpll.lock); in _icl_ddi_enable_clock()
1563 mutex_unlock(&display->dpll.lock); in _icl_ddi_enable_clock()
1569 mutex_lock(&display->dpll.lock); in _icl_ddi_disable_clock()
1573 mutex_unlock(&display->dpll.lock); in _icl_ddi_disable_clock()
1597 const struct intel_dpll *pll = crtc_state->intel_dpll; in adls_ddi_enable_clock()
1600 if (drm_WARN_ON(display->drm, !pll)) in adls_ddi_enable_clock()
1605 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), in adls_ddi_enable_clock()
1641 const struct intel_dpll *pll = crtc_state->intel_dpll; in rkl_ddi_enable_clock()
1644 if (drm_WARN_ON(display->drm, !pll)) in rkl_ddi_enable_clock()
1649 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), in rkl_ddi_enable_clock()
1685 const struct intel_dpll *pll = crtc_state->intel_dpll; in dg1_ddi_enable_clock()
1688 if (drm_WARN_ON(display->drm, !pll)) in dg1_ddi_enable_clock()
1695 if (drm_WARN_ON(display->drm, in dg1_ddi_enable_clock()
1696 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || in dg1_ddi_enable_clock()
1697 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) in dg1_ddi_enable_clock()
1702 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), in dg1_ddi_enable_clock()
1751 const struct intel_dpll *pll = crtc_state->intel_dpll; in icl_ddi_combo_enable_clock()
1754 if (drm_WARN_ON(display->drm, !pll)) in icl_ddi_combo_enable_clock()
1759 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), in icl_ddi_combo_enable_clock()
1795 const struct intel_dpll *pll = crtc_state->intel_dpll; in jsl_ddi_tc_enable_clock()
1796 enum port port = encoder->port; in jsl_ddi_tc_enable_clock()
1798 if (drm_WARN_ON(display->drm, !pll)) in jsl_ddi_tc_enable_clock()
1813 enum port port = encoder->port; in jsl_ddi_tc_disable_clock()
1823 enum port port = encoder->port; in jsl_ddi_tc_is_clock_enabled()
1838 const struct intel_dpll *pll = crtc_state->intel_dpll; in icl_ddi_tc_enable_clock()
1840 enum port port = encoder->port; in icl_ddi_tc_enable_clock()
1842 if (drm_WARN_ON(display->drm, !pll)) in icl_ddi_tc_enable_clock()
1848 mutex_lock(&display->dpll.lock); in icl_ddi_tc_enable_clock()
1853 mutex_unlock(&display->dpll.lock); in icl_ddi_tc_enable_clock()
1860 enum port port = encoder->port; in icl_ddi_tc_disable_clock()
1862 mutex_lock(&display->dpll.lock); in icl_ddi_tc_disable_clock()
1867 mutex_unlock(&display->dpll.lock); in icl_ddi_tc_disable_clock()
1876 enum port port = encoder->port; in icl_ddi_tc_is_clock_enabled()
1893 enum port port = encoder->port; in icl_ddi_tc_get_pll()
1921 struct intel_display *display = to_intel_display(encoder->base.dev); in bxt_ddi_get_pll()
1924 switch (encoder->port) { in bxt_ddi_get_pll()
1935 MISSING_CASE(encoder->port); in bxt_ddi_get_pll()
1946 const struct intel_dpll *pll = crtc_state->intel_dpll; in skl_ddi_enable_clock()
1947 enum port port = encoder->port; in skl_ddi_enable_clock()
1949 if (drm_WARN_ON(display->drm, !pll)) in skl_ddi_enable_clock()
1952 mutex_lock(&display->dpll.lock); in skl_ddi_enable_clock()
1957 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | in skl_ddi_enable_clock()
1960 mutex_unlock(&display->dpll.lock); in skl_ddi_enable_clock()
1966 enum port port = encoder->port; in skl_ddi_disable_clock()
1968 mutex_lock(&display->dpll.lock); in skl_ddi_disable_clock()
1973 mutex_unlock(&display->dpll.lock); in skl_ddi_disable_clock()
1979 enum port port = encoder->port; in skl_ddi_is_clock_enabled()
1991 enum port port = encoder->port; in skl_ddi_get_pll()
2014 const struct intel_dpll *pll = crtc_state->intel_dpll; in hsw_ddi_enable_clock()
2015 enum port port = encoder->port; in hsw_ddi_enable_clock()
2017 if (drm_WARN_ON(display->drm, !pll)) in hsw_ddi_enable_clock()
2026 enum port port = encoder->port; in hsw_ddi_disable_clock()
2034 enum port port = encoder->port; in hsw_ddi_is_clock_enabled()
2042 enum port port = encoder->port; in hsw_ddi_get_pll()
2080 if (encoder->enable_clock) in intel_ddi_enable_clock()
2081 encoder->enable_clock(encoder, crtc_state); in intel_ddi_enable_clock()
2086 if (encoder->disable_clock) in intel_ddi_disable_clock()
2087 encoder->disable_clock(encoder); in intel_ddi_disable_clock()
2100 if (encoder->type == INTEL_OUTPUT_DP_MST) in intel_ddi_sanitize_encoder_pll_mapping()
2103 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { in intel_ddi_sanitize_encoder_pll_mapping()
2112 if (drm_WARN_ON(display->drm, is_mst)) in intel_ddi_sanitize_encoder_pll_mapping()
2116 port_mask = BIT(encoder->port); in intel_ddi_sanitize_encoder_pll_mapping()
2117 ddi_clk_needed = encoder->base.crtc; in intel_ddi_sanitize_encoder_pll_mapping()
2119 if (encoder->type == INTEL_OUTPUT_DSI) { in intel_ddi_sanitize_encoder_pll_mapping()
2127 for_each_intel_encoder(display->drm, other_encoder) { in intel_ddi_sanitize_encoder_pll_mapping()
2131 if (drm_WARN_ON(display->drm, in intel_ddi_sanitize_encoder_pll_mapping()
2132 port_mask & BIT(other_encoder->port))) in intel_ddi_sanitize_encoder_pll_mapping()
2142 if (ddi_clk_needed || !encoder->is_clock_enabled || in intel_ddi_sanitize_encoder_pll_mapping()
2143 !encoder->is_clock_enabled(encoder)) in intel_ddi_sanitize_encoder_pll_mapping()
2146 drm_dbg_kms(display->drm, in intel_ddi_sanitize_encoder_pll_mapping()
2148 encoder->base.base.id, encoder->base.name); in intel_ddi_sanitize_encoder_pll_mapping()
2150 encoder->disable_clock(encoder); in intel_ddi_sanitize_encoder_pll_mapping()
2168 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); in icl_program_mg_dp_mode()
2175 if (!intel_encoder_is_tc(&dig_port->base) || in icl_program_mg_dp_mode()
2192 width = crtc_state->lane_count; in icl_program_mg_dp_mode()
2196 drm_WARN_ON(display->drm, in icl_program_mg_dp_mode()
2258 return crtc_state->mst_master_transcoder; in tgl_dp_tp_transcoder()
2260 return crtc_state->cpu_transcoder; in tgl_dp_tp_transcoder()
2272 return DP_TP_CTL(encoder->port); in dp_tp_ctl_reg()
2284 return DP_TP_STATUS(encoder->port); in dp_tp_status_reg()
2303 drm_err(display->drm, "Timed out waiting for ACT sent\n"); in intel_ddi_wait_for_act_sent()
2312 if (!crtc_state->vrr.enable) in intel_dp_sink_set_msa_timing_par_ignore_state()
2315 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, in intel_dp_sink_set_msa_timing_par_ignore_state()
2317 drm_dbg_kms(display->drm, in intel_dp_sink_set_msa_timing_par_ignore_state()
2328 if (!crtc_state->fec_enable) in intel_dp_sink_set_fec_ready()
2331 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, in intel_dp_sink_set_fec_ready()
2333 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n", in intel_dp_sink_set_fec_ready()
2337 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, in intel_dp_sink_set_fec_ready()
2339 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n"); in intel_dp_sink_set_fec_ready()
2356 struct intel_display *display = to_intel_display(aux->drm_dev); in wait_for_fec_detected()
2366 drm_dbg_kms(display->drm, in wait_for_fec_detected()
2383 if (!crtc_state->fec_enable) in intel_ddi_wait_for_fec_status()
2394 drm_err(display->drm, in intel_ddi_wait_for_fec_status()
2404 ret = wait_for_fec_detected(&intel_dp->aux, enabled); in intel_ddi_wait_for_fec_status()
2419 if (!crtc_state->fec_enable) in intel_ddi_enable_fec()
2433 drm_dbg_kms(display->drm, "Retry FEC enabling\n"); in intel_ddi_enable_fec()
2450 drm_err(display->drm, "Failed to enable FEC after retries\n"); in intel_ddi_enable_fec()
2458 if (!crtc_state->fec_enable) in intel_ddi_disable_fec()
2476 crtc_state->lane_count, in intel_ddi_power_up_lanes()
2477 dig_port->lane_reversal); in intel_ddi_power_up_lanes()
2489 else if (display->platform.alderlake_p) in intel_ddi_splitter_pipe_mask()
2499 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_ddi_mso_get_config()
2500 enum pipe pipe = crtc->pipe; in intel_ddi_mso_get_config()
2508 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; in intel_ddi_mso_get_config()
2509 if (!pipe_config->splitter.enable) in intel_ddi_mso_get_config()
2512 if (drm_WARN_ON(display->drm, !(intel_ddi_splitter_pipe_mask(display) & BIT(pipe)))) { in intel_ddi_mso_get_config()
2513 pipe_config->splitter.enable = false; in intel_ddi_mso_get_config()
2519 drm_WARN(display->drm, true, in intel_ddi_mso_get_config()
2523 pipe_config->splitter.link_count = 2; in intel_ddi_mso_get_config()
2526 pipe_config->splitter.link_count = 4; in intel_ddi_mso_get_config()
2530 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); in intel_ddi_mso_get_config()
2536 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_mso_configure()
2537 enum pipe pipe = crtc->pipe; in intel_ddi_mso_configure()
2543 if (crtc_state->splitter.enable) { in intel_ddi_mso_configure()
2545 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); in intel_ddi_mso_configure()
2546 if (crtc_state->splitter.link_count == 2) in intel_ddi_mso_configure()
2561 enum port port = encoder->port; in mtl_ddi_enable_d2d()
2580 drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", in mtl_ddi_enable_d2d()
2590 enum port port = encoder->port; in mtl_port_buf_ctl_program()
2593 val |= XELPDP_PORT_WIDTH(crtc_state->lane_count); in mtl_port_buf_ctl_program()
2600 if (dig_port->lane_reversal) in mtl_port_buf_ctl_program()
2616 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), in mtl_port_buf_ctl_io_selection()
2631 crtc_state->port_clock, in mtl_ddi_pre_enable_dp()
2632 crtc_state->lane_count); in mtl_ddi_pre_enable_dp()
2665 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. in mtl_ddi_pre_enable_dp()
2680 drm_dp_lttpr_wake_timeout_setup(&intel_dp->aux, transparent_mode); in mtl_ddi_pre_enable_dp()
2685 to_intel_connector(conn_state->connector), in mtl_ddi_pre_enable_dp()
2704 * stream or multi-stream master transcoder" can just be performed in mtl_ddi_pre_enable_dp()
2713 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle in mtl_ddi_pre_enable_dp()
2729 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); in mtl_ddi_pre_enable_dp()
2750 crtc_state->port_clock, in tgl_ddi_pre_enable_dp()
2751 crtc_state->lane_count); in tgl_ddi_pre_enable_dp()
2770 * 3. For non-TBT Type-C ports, set FIA lane count in tgl_ddi_pre_enable_dp()
2774 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). in tgl_ddi_pre_enable_dp()
2781 * hsw_crtc_enable()->intel_enable_dpll(). We need only in tgl_ddi_pre_enable_dp()
2788 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); in tgl_ddi_pre_enable_dp()
2789 dig_port->ddi_io_wakeref = intel_display_power_get(display, in tgl_ddi_pre_enable_dp()
2790 dig_port->ddi_io_power_domain); in tgl_ddi_pre_enable_dp()
2802 * stream or multi-stream master transcoder" can just be performed in tgl_ddi_pre_enable_dp()
2827 encoder->set_signal_levels(encoder, crtc_state); in tgl_ddi_pre_enable_dp()
2846 to_intel_connector(conn_state->connector), in tgl_ddi_pre_enable_dp()
2861 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle in tgl_ddi_pre_enable_dp()
2876 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); in tgl_ddi_pre_enable_dp()
2892 enum port port = encoder->port; in hsw_ddi_pre_enable_dp()
2897 drm_WARN_ON(display->drm, in hsw_ddi_pre_enable_dp()
2900 drm_WARN_ON(display->drm, is_mst && port == PORT_A); in hsw_ddi_pre_enable_dp()
2903 crtc_state->port_clock, in hsw_ddi_pre_enable_dp()
2904 crtc_state->lane_count); in hsw_ddi_pre_enable_dp()
2917 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); in hsw_ddi_pre_enable_dp()
2918 dig_port->ddi_io_wakeref = intel_display_power_get(display, in hsw_ddi_pre_enable_dp()
2919 dig_port->ddi_io_power_domain); in hsw_ddi_pre_enable_dp()
2927 encoder->set_signal_levels(encoder, crtc_state); in hsw_ddi_pre_enable_dp()
2936 to_intel_connector(conn_state->connector), in hsw_ddi_pre_enable_dp()
2987 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; in intel_ddi_pre_enable_hdmi()
2992 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); in intel_ddi_pre_enable_hdmi()
2993 dig_port->ddi_io_wakeref = intel_display_power_get(display, in intel_ddi_pre_enable_hdmi()
2994 dig_port->ddi_io_power_domain); in intel_ddi_pre_enable_hdmi()
3000 dig_port->set_infoframes(encoder, in intel_ddi_pre_enable_hdmi()
3001 crtc_state->has_infoframe, in intel_ddi_pre_enable_hdmi()
3006 * Note: Also called from the ->pre_enable of the first active MST stream
3011 * - conn_state will be NULL
3013 * - encoder will be the primary encoder (i.e. mst->primary)
3015 * - the main connector associated with this port won't be active or linked to a
3018 * - crtc_state will be the state of the first stream to be activated on this
3029 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_pre_enable()
3030 enum pipe pipe = crtc->pipe; in intel_ddi_pre_enable()
3032 drm_WARN_ON(display->drm, crtc_state->has_pch_encoder); in intel_ddi_pre_enable()
3047 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) in intel_ddi_pre_enable()
3048 dig_port->set_infoframes(encoder, in intel_ddi_pre_enable()
3049 crtc_state->has_infoframe, in intel_ddi_pre_enable()
3058 enum port port = encoder->port; in mtl_ddi_disable_d2d()
3077 drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", in mtl_ddi_disable_d2d()
3084 enum port port = encoder->port; in intel_ddi_buf_enable()
3096 enum port port = encoder->port; in intel_ddi_buf_disable()
3125 struct intel_dp *intel_dp = &dig_port->dp; in intel_ddi_post_disable_dp()
3142 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; in intel_ddi_post_disable_dp()
3161 * From TGL spec: "If single stream or multi-stream master transcoder: in intel_ddi_post_disable_dp()
3171 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); in intel_ddi_post_disable_dp()
3175 dig_port->ddi_io_power_domain, in intel_ddi_post_disable_dp()
3180 /* De-select Thunderbolt */ in intel_ddi_post_disable_dp()
3182 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), in intel_ddi_post_disable_dp()
3193 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; in intel_ddi_post_disable_hdmi()
3196 dig_port->set_infoframes(encoder, false, in intel_ddi_post_disable_hdmi()
3207 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); in intel_ddi_post_disable_hdmi()
3210 dig_port->ddi_io_power_domain, in intel_ddi_post_disable_hdmi()
3241 drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, 0); in intel_ddi_post_disable_hdmi_or_sst()
3245 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder), in intel_ddi_post_disable_hdmi_or_sst()
3249 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); in intel_ddi_post_disable_hdmi_or_sst()
3270 * Note: Also called from the ->post_disable of the last active MST stream
3285 * - old_conn_state will be NULL in intel_ddi_post_disable()
3286 * - encoder will be the main encoder (ie. mst->primary) in intel_ddi_post_disable()
3287 * - the main connector associated with this port in intel_ddi_post_disable()
3289 * - old_crtc_state will be the state of the last stream to in intel_ddi_post_disable()
3305 * Note: Also called from the ->post_pll_disable of the last active MST stream
3330 if (!crtc_state->sync_mode_slaves_mask) in trans_port_sync_stop_link_train()
3333 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { in trans_port_sync_stop_link_train()
3335 to_intel_encoder(conn_state->best_encoder); in trans_port_sync_stop_link_train()
3336 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); in trans_port_sync_stop_link_train()
3345 if (slave_crtc_state->master_transcoder != in trans_port_sync_stop_link_train()
3346 crtc_state->cpu_transcoder) in trans_port_sync_stop_link_train()
3367 enum port port = encoder->port; in intel_ddi_enable_dp()
3377 if (!intel_lspcon_active(dig_port) || intel_dp_has_hdmi_sink(&dig_port->dp)) in intel_ddi_enable_dp()
3394 drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9); in gen9_chicken_trans_reg_by_port()
3396 if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E)) in gen9_chicken_trans_reg_by_port()
3409 struct drm_connector *connector = conn_state->connector; in intel_ddi_enable_hdmi()
3410 enum port port = encoder->port; in intel_ddi_enable_hdmi()
3414 crtc_state->hdmi_high_tmds_clock_ratio, in intel_ddi_enable_hdmi()
3415 crtc_state->hdmi_scrambling)) in intel_ddi_enable_hdmi()
3416 drm_dbg_kms(display->drm, in intel_ddi_enable_hdmi()
3418 connector->base.id, connector->name); in intel_ddi_enable_hdmi()
3426 encoder->set_signal_levels(encoder, crtc_state); in intel_ddi_enable_hdmi()
3429 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) { in intel_ddi_enable_hdmi()
3465 /* In HDMI/DVI mode, the port width, and swing/emphasis values in intel_ddi_enable_hdmi()
3470 * these are both 0 for HDMI. in intel_ddi_enable_hdmi()
3476 if (dig_port->lane_reversal) in intel_ddi_enable_hdmi()
3478 if (dig_port->ddi_a_4_lanes) in intel_ddi_enable_hdmi()
3484 port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_enable_hdmi()
3486 if (dig_port->lane_reversal) in intel_ddi_enable_hdmi()
3492 buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_enable_hdmi()
3496 } else if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { in intel_ddi_enable_hdmi()
3497 drm_WARN_ON(display->drm, !intel_tc_port_in_legacy_mode(dig_port)); in intel_ddi_enable_hdmi()
3511 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_enable()
3517 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_ddi_enable()
3518 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); in intel_ddi_enable()
3540 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); in intel_ddi_enable()
3570 to_intel_connector(old_conn_state->connector); in intel_ddi_disable_dp()
3572 intel_dp->link.active = false; in intel_ddi_disable_dp()
3592 struct drm_connector *connector = old_conn_state->connector; in intel_ddi_disable_hdmi()
3596 drm_dbg_kms(display->drm, in intel_ddi_disable_hdmi()
3598 connector->base.id, connector->name); in intel_ddi_disable_hdmi()
3608 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); in intel_ddi_disable()
3669 for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, in intel_ddi_update_active_dpll()
3675 * Note: Also called from the ->pre_pll_enable of the first active MST stream
3690 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_pre_pll_enable()
3692 intel_tc_port_get_link(dig_port, crtc_state->lane_count); in intel_ddi_pre_pll_enable()
3701 * Type-C ports. Skip this step for TBT. in intel_ddi_pre_pll_enable()
3703 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); in intel_ddi_pre_pll_enable()
3704 else if (display->platform.geminilake || display->platform.broxton) in intel_ddi_pre_pll_enable()
3706 crtc_state->lane_lat_optim_mask); in intel_ddi_pre_pll_enable()
3725 struct intel_encoder *encoder = &dig_port->base; in mtl_ddi_prepare_link_retrain()
3734 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); in mtl_ddi_prepare_link_retrain()
3743 if (crtc_state->enhanced_framing) in mtl_ddi_prepare_link_retrain()
3753 encoder->set_signal_levels(encoder, crtc_state); in mtl_ddi_prepare_link_retrain()
3760 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; in mtl_ddi_prepare_link_retrain()
3762 intel_ddi_buf_enable(encoder, intel_dp->DP); in mtl_ddi_prepare_link_retrain()
3763 intel_dp->DP |= DDI_BUF_CTL_ENABLE; in mtl_ddi_prepare_link_retrain()
3766 * 6.k If AUX-Less ALPM is going to be enabled: in mtl_ddi_prepare_link_retrain()
3783 struct intel_encoder *encoder = &dig_port->base; in intel_ddi_prepare_link_retrain()
3788 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); in intel_ddi_prepare_link_retrain()
3796 if (crtc_state->enhanced_framing) in intel_ddi_prepare_link_retrain()
3802 if (display->platform.alderlake_p && in intel_ddi_prepare_link_retrain()
3806 intel_ddi_buf_enable(encoder, intel_dp->DP); in intel_ddi_prepare_link_retrain()
3807 intel_dp->DP |= DDI_BUF_CTL_ENABLE; in intel_ddi_prepare_link_retrain()
3815 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_ddi_set_link_train()
3846 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_ddi_set_idle_link_train()
3847 enum port port = encoder->port; in intel_ddi_set_idle_link_train()
3855 * issue where we enable the pipe while not in idle link-training mode. in intel_ddi_set_idle_link_train()
3865 drm_err(display->drm, in intel_ddi_set_idle_link_train()
3884 if (crtc_state->port_clock > 594000) in tgl_ddi_min_voltage_level()
3892 if (crtc_state->port_clock > 594000) in jsl_ddi_min_voltage_level()
3900 if (crtc_state->port_clock > 594000) in icl_ddi_min_voltage_level()
3911 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); in intel_ddi_compute_min_voltage_level()
3913 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); in intel_ddi_compute_min_voltage_level()
3914 else if (display->platform.jasperlake || display->platform.elkhartlake) in intel_ddi_compute_min_voltage_level()
3915 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); in intel_ddi_compute_min_voltage_level()
3917 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); in intel_ddi_compute_min_voltage_level()
3946 return master_select - 1; in bdw_transcoder_master_readout()
3956 crtc_state->master_transcoder = in bdw_get_trans_port_sync_config()
3957 bdw_transcoder_master_readout(display, crtc_state->cpu_transcoder); in bdw_get_trans_port_sync_config()
3971 crtc_state->cpu_transcoder) in bdw_get_trans_port_sync_config()
3972 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); in bdw_get_trans_port_sync_config()
3977 drm_WARN_ON(display->drm, in bdw_get_trans_port_sync_config()
3978 crtc_state->master_transcoder != INVALID_TRANSCODER && in bdw_get_trans_port_sync_config()
3979 crtc_state->sync_mode_slaves_mask); in bdw_get_trans_port_sync_config()
3988 crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI); in intel_ddi_read_func_ctl_dvi()
3990 crtc_state->lane_count = in intel_ddi_read_func_ctl_dvi()
3993 crtc_state->lane_count = 4; in intel_ddi_read_func_ctl_dvi()
4000 crtc_state->has_hdmi_sink = true; in intel_ddi_read_func_ctl_hdmi()
4002 crtc_state->infoframes.enable |= in intel_ddi_read_func_ctl_hdmi()
4005 if (crtc_state->infoframes.enable) in intel_ddi_read_func_ctl_hdmi()
4006 crtc_state->has_infoframe = true; in intel_ddi_read_func_ctl_hdmi()
4009 crtc_state->hdmi_scrambling = true; in intel_ddi_read_func_ctl_hdmi()
4011 crtc_state->hdmi_high_tmds_clock_ratio = true; in intel_ddi_read_func_ctl_hdmi()
4022 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG); in intel_ddi_read_func_ctl_fdi()
4023 crtc_state->enhanced_framing = in intel_ddi_read_func_ctl_fdi()
4033 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_read_func_ctl_dp_sst()
4035 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_read_func_ctl_dp_sst()
4037 if (encoder->type == INTEL_OUTPUT_EDP) in intel_ddi_read_func_ctl_dp_sst()
4038 crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP); in intel_ddi_read_func_ctl_dp_sst()
4040 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP); in intel_ddi_read_func_ctl_dp_sst()
4041 crtc_state->lane_count = in intel_ddi_read_func_ctl_dp_sst()
4046 crtc_state->mst_master_transcoder = in intel_ddi_read_func_ctl_dp_sst()
4049 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); in intel_ddi_read_func_ctl_dp_sst()
4050 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2); in intel_ddi_read_func_ctl_dp_sst()
4052 crtc_state->enhanced_framing = in intel_ddi_read_func_ctl_dp_sst()
4057 crtc_state->fec_enable = in intel_ddi_read_func_ctl_dp_sst()
4061 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) in intel_ddi_read_func_ctl_dp_sst()
4062 crtc_state->infoframes.enable |= in intel_ddi_read_func_ctl_dp_sst()
4065 crtc_state->infoframes.enable |= in intel_ddi_read_func_ctl_dp_sst()
4074 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_read_func_ctl_dp_mst()
4075 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_read_func_ctl_dp_mst()
4077 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST); in intel_ddi_read_func_ctl_dp_mst()
4078 crtc_state->lane_count = in intel_ddi_read_func_ctl_dp_mst()
4082 crtc_state->mst_master_transcoder = in intel_ddi_read_func_ctl_dp_mst()
4085 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); in intel_ddi_read_func_ctl_dp_mst()
4088 crtc_state->fec_enable = in intel_ddi_read_func_ctl_dp_mst()
4092 crtc_state->infoframes.enable |= in intel_ddi_read_func_ctl_dp_mst()
4100 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in intel_ddi_read_func_ctl()
4113 pipe_config->hw.adjusted_mode.flags |= flags; in intel_ddi_read_func_ctl()
4117 pipe_config->pipe_bpp = 18; in intel_ddi_read_func_ctl()
4120 pipe_config->pipe_bpp = 24; in intel_ddi_read_func_ctl()
4123 pipe_config->pipe_bpp = 30; in intel_ddi_read_func_ctl()
4126 pipe_config->pipe_bpp = 36; in intel_ddi_read_func_ctl()
4149 * encoder's ->get_config(). in intel_ddi_read_func_ctl()
4159 * Note: Also called from the ->get_config of the MST stream encoders on their
4167 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in intel_ddi_get_config()
4170 if (drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder))) in intel_ddi_get_config()
4177 pipe_config->has_audio = in intel_ddi_get_config()
4180 if (encoder->type == INTEL_OUTPUT_EDP) in intel_ddi_get_config()
4181 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); in intel_ddi_get_config()
4185 if (display->platform.geminilake || display->platform.broxton) in intel_ddi_get_config()
4186 pipe_config->lane_lat_optim_mask = in intel_ddi_get_config()
4195 &pipe_config->infoframes.avi); in intel_ddi_get_config()
4198 &pipe_config->infoframes.spd); in intel_ddi_get_config()
4201 &pipe_config->infoframes.hdmi); in intel_ddi_get_config()
4204 &pipe_config->infoframes.drm); in intel_ddi_get_config()
4224 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; in intel_ddi_get_clock()
4227 if (drm_WARN_ON(display->drm, !pll)) in intel_ddi_get_clock()
4230 port_dpll->pll = pll; in intel_ddi_get_clock()
4231 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); in intel_ddi_get_clock()
4232 drm_WARN_ON(display->drm, !pll_active); in intel_ddi_get_clock()
4236 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, in intel_ddi_get_clock()
4237 &crtc_state->dpll_hw_state); in intel_ddi_get_clock()
4243 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); in mtl_ddi_get_config()
4245 if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) in mtl_ddi_get_config()
4246 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); in mtl_ddi_get_config()
4248 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); in mtl_ddi_get_config()
4256 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); in dg2_ddi_get_config()
4257 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); in dg2_ddi_get_config()
4292 return pll->info->id == DPLL_ID_ICL_TBTPLL; in icl_ddi_tc_pll_is_tbt()
4300 const struct intel_dpll *pll = crtc_state->intel_dpll; in icl_ddi_tc_port_pll_type()
4302 if (drm_WARN_ON(display->drm, !pll)) in icl_ddi_tc_port_pll_type()
4315 if (!encoder->port_pll_type) in intel_ddi_port_pll_type()
4318 return encoder->port_pll_type(encoder, crtc_state); in intel_ddi_port_pll_type()
4330 if (drm_WARN_ON(display->drm, !pll)) in icl_ddi_tc_get_clock()
4338 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; in icl_ddi_tc_get_clock()
4340 port_dpll->pll = pll; in icl_ddi_tc_get_clock()
4341 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); in icl_ddi_tc_get_clock()
4342 drm_WARN_ON(display->drm, !pll_active); in icl_ddi_tc_get_clock()
4346 if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll)) in icl_ddi_tc_get_clock()
4347 crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port); in icl_ddi_tc_get_clock()
4349 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, in icl_ddi_tc_get_clock()
4350 &crtc_state->dpll_hw_state); in icl_ddi_tc_get_clock()
4400 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", in intel_ddi_initial_fastset_check()
4401 encoder->base.base.id, encoder->base.name); in intel_ddi_initial_fastset_check()
4402 crtc_state->uapi.mode_changed = true; in intel_ddi_initial_fastset_check()
4418 switch (conn_state->connector->connector_type) { in intel_ddi_compute_output_type()
4426 MISSING_CASE(conn_state->connector->connector_type); in intel_ddi_compute_output_type()
4436 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_ddi_compute_config()
4437 enum port port = encoder->port; in intel_ddi_compute_config()
4441 pipe_config->cpu_transcoder = TRANSCODER_EDP; in intel_ddi_compute_config()
4444 pipe_config->has_hdmi_sink = in intel_ddi_compute_config()
4455 if (display->platform.haswell && crtc->pipe == PIPE_A && in intel_ddi_compute_config()
4456 pipe_config->cpu_transcoder == TRANSCODER_EDP) in intel_ddi_compute_config()
4457 pipe_config->pch_pfit.force_thru = in intel_ddi_compute_config()
4458 pipe_config->pch_pfit.enabled || in intel_ddi_compute_config()
4459 pipe_config->crc_enabled; in intel_ddi_compute_config()
4461 if (display->platform.geminilake || display->platform.broxton) in intel_ddi_compute_config()
4462 pipe_config->lane_lat_optim_mask = in intel_ddi_compute_config()
4463 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); in intel_ddi_compute_config()
4477 mode1->clock == mode2->clock; /* we want an exact match */ in mode_equal()
4483 return m_n_1->tu == m_n_2->tu && in m_n_equal()
4484 m_n_1->data_m == m_n_2->data_m && in m_n_equal()
4485 m_n_1->data_n == m_n_2->data_n && in m_n_equal()
4486 m_n_1->link_m == m_n_2->link_m && in m_n_equal()
4487 m_n_1->link_n == m_n_2->link_n; in m_n_equal()
4497 return crtc_state1->hw.active && crtc_state2->hw.active && in crtcs_port_sync_compatible()
4498 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes && in crtcs_port_sync_compatible()
4499 crtc_state1->output_types == crtc_state2->output_types && in crtcs_port_sync_compatible()
4500 crtc_state1->output_format == crtc_state2->output_format && in crtcs_port_sync_compatible()
4501 crtc_state1->lane_count == crtc_state2->lane_count && in crtcs_port_sync_compatible()
4502 crtc_state1->port_clock == crtc_state2->port_clock && in crtcs_port_sync_compatible()
4503 mode_equal(&crtc_state1->hw.adjusted_mode, in crtcs_port_sync_compatible()
4504 &crtc_state2->hw.adjusted_mode) && in crtcs_port_sync_compatible()
4505 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); in crtcs_port_sync_compatible()
4516 to_intel_atomic_state(ref_crtc_state->uapi.state); in intel_ddi_port_sync_transcoders()
4530 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { in intel_ddi_port_sync_transcoders()
4531 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); in intel_ddi_port_sync_transcoders()
4537 if (!connector->has_tile || in intel_ddi_port_sync_transcoders()
4538 connector->tile_group->id != in intel_ddi_port_sync_transcoders()
4546 transcoders |= BIT(crtc_state->cpu_transcoder); in intel_ddi_port_sync_transcoders()
4557 struct drm_connector *connector = conn_state->connector; in intel_ddi_compute_config_late()
4560 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", in intel_ddi_compute_config_late()
4561 encoder->base.base.id, encoder->base.name, in intel_ddi_compute_config_late()
4562 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); in intel_ddi_compute_config_late()
4564 if (connector->has_tile) in intel_ddi_compute_config_late()
4566 connector->tile_group->id); in intel_ddi_compute_config_late()
4573 crtc_state->master_transcoder = TRANSCODER_EDP; in intel_ddi_compute_config_late()
4575 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; in intel_ddi_compute_config_late()
4577 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { in intel_ddi_compute_config_late()
4578 crtc_state->master_transcoder = INVALID_TRANSCODER; in intel_ddi_compute_config_late()
4579 crtc_state->sync_mode_slaves_mask = in intel_ddi_compute_config_late()
4580 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); in intel_ddi_compute_config_late()
4588 struct intel_display *display = to_intel_display(encoder->dev); in intel_ddi_encoder_destroy()
4592 if (intel_encoder_is_tc(&dig_port->base)) in intel_ddi_encoder_destroy()
4597 kfree(dig_port->hdcp.port_data.streams); in intel_ddi_encoder_destroy()
4606 intel_dp->reset_link_params = true; in intel_ddi_encoder_reset()
4611 if (intel_encoder_is_tc(&dig_port->base)) in intel_ddi_encoder_reset()
4634 enum port port = dig_port->base.port; in intel_ddi_init_dp_connector()
4638 return -ENOMEM; in intel_ddi_init_dp_connector()
4640 dig_port->dp.output_reg = DDI_BUF_CTL(port); in intel_ddi_init_dp_connector()
4642 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; in intel_ddi_init_dp_connector()
4644 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; in intel_ddi_init_dp_connector()
4645 dig_port->dp.set_link_train = intel_ddi_set_link_train; in intel_ddi_init_dp_connector()
4646 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; in intel_ddi_init_dp_connector()
4648 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; in intel_ddi_init_dp_connector()
4649 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; in intel_ddi_init_dp_connector()
4653 return -EINVAL; in intel_ddi_init_dp_connector()
4656 if (dig_port->base.type == INTEL_OUTPUT_EDP) { in intel_ddi_init_dp_connector()
4659 privacy_screen = drm_privacy_screen_get(display->drm->dev, NULL); in intel_ddi_init_dp_connector()
4661 drm_connector_attach_privacy_screen_provider(&connector->base, in intel_ddi_init_dp_connector()
4663 } else if (PTR_ERR(privacy_screen) != -ENODEV) { in intel_ddi_init_dp_connector()
4664 drm_warn(display->drm, "Error getting privacy-screen\n"); in intel_ddi_init_dp_connector()
4675 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); in intel_hdmi_reset_link() local
4676 struct intel_connector *connector = hdmi->attached_connector; in intel_hdmi_reset_link()
4677 struct i2c_adapter *ddc = connector->base.ddc; in intel_hdmi_reset_link()
4684 if (connector->base.status != connector_status_connected) in intel_hdmi_reset_link()
4687 ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, in intel_hdmi_reset_link()
4692 conn_state = connector->base.state; in intel_hdmi_reset_link()
4694 crtc = to_intel_crtc(conn_state->crtc); in intel_hdmi_reset_link()
4698 ret = drm_modeset_lock(&crtc->base.mutex, ctx); in intel_hdmi_reset_link()
4702 crtc_state = to_intel_crtc_state(crtc->base.state); in intel_hdmi_reset_link()
4704 drm_WARN_ON(display->drm, in intel_hdmi_reset_link()
4707 if (!crtc_state->hw.active) in intel_hdmi_reset_link()
4710 if (!crtc_state->hdmi_high_tmds_clock_ratio && in intel_hdmi_reset_link()
4711 !crtc_state->hdmi_scrambling) in intel_hdmi_reset_link()
4714 if (conn_state->commit && in intel_hdmi_reset_link()
4715 !try_wait_for_completion(&conn_state->commit->hw_done)) in intel_hdmi_reset_link()
4720 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", in intel_hdmi_reset_link()
4721 connector->base.base.id, connector->base.name, ret); in intel_hdmi_reset_link()
4726 crtc_state->hdmi_high_tmds_clock_ratio && in intel_hdmi_reset_link()
4728 crtc_state->hdmi_scrambling) in intel_hdmi_reset_link()
4732 * HDMI 2.0 says that one should not send scrambled data in intel_hdmi_reset_link()
4740 return intel_modeset_commit_pipes(display, BIT(crtc->pipe), ctx); in intel_hdmi_reset_link()
4748 /* TODO: Move checking the HDMI link state here as well. */ in intel_ddi_link_check()
4749 drm_WARN_ON(display->drm, !dig_port->dp.attached_connector); in intel_ddi_link_check()
4759 struct intel_dp *intel_dp = &dig_port->dp; in intel_ddi_hotplug()
4771 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { in intel_ddi_hotplug()
4774 drm_WARN_ON(encoder->base.dev, ret); in intel_ddi_hotplug()
4781 * Unpowered type-c dongles can take some time to boot and be in intel_ddi_hotplug()
4785 * On many platforms the HDMI live state signal is known to be in intel_ddi_hotplug()
4796 * Type-c connectors which get their HPD signal deasserted then in intel_ddi_hotplug()
4799 * becomes functional. Retry the detection for 5 seconds on type-c in intel_ddi_hotplug()
4803 connector->hotplug_retries < (is_tc ? 5 : 1) && in intel_ddi_hotplug()
4804 !dig_port->dp.is_mst) in intel_ddi_hotplug()
4813 u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin]; in lpt_digital_port_connected()
4821 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; in hsw_digital_port_connected()
4829 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; in bdw_digital_port_connected()
4837 enum port port = dig_port->base.port; in intel_ddi_init_hdmi_connector()
4841 return -ENOMEM; in intel_ddi_init_hdmi_connector()
4843 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); in intel_ddi_init_hdmi_connector()
4847 * HDMI connector init failures may just mean conflicting DDC in intel_ddi_init_hdmi_connector()
4851 dig_port->hdmi.hdmi_reg = INVALID_MMIO_REG; in intel_ddi_init_hdmi_connector()
4862 if (dig_port->base.port != PORT_A) in intel_ddi_a_force_4_lanes()
4865 if (dig_port->ddi_a_4_lanes) in intel_ddi_a_force_4_lanes()
4871 if (display->platform.geminilake || display->platform.broxton) in intel_ddi_a_force_4_lanes()
4881 enum port port = dig_port->base.port; in intel_ddi_max_lanes()
4901 drm_dbg_kms(display->drm, in intel_ddi_max_lanes()
4903 dig_port->ddi_a_4_lanes = true; in intel_ddi_max_lanes()
4913 return HPD_PORT_D + port - PORT_D_XELPD; in xelpd_hpd_pin()
4915 return HPD_PORT_TC1 + port - PORT_TC1; in xelpd_hpd_pin()
4917 return HPD_PORT_A + port - PORT_A; in xelpd_hpd_pin()
4923 return HPD_PORT_C + port - PORT_TC1; in dg1_hpd_pin()
4925 return HPD_PORT_A + port - PORT_A; in dg1_hpd_pin()
4931 return HPD_PORT_TC1 + port - PORT_TC1; in tgl_hpd_pin()
4933 return HPD_PORT_A + port - PORT_A; in tgl_hpd_pin()
4942 return HPD_PORT_C + port - PORT_TC1; in rkl_hpd_pin()
4944 return HPD_PORT_A + port - PORT_A; in rkl_hpd_pin()
4950 return HPD_PORT_TC1 + port - PORT_C; in icl_hpd_pin()
4952 return HPD_PORT_A + port - PORT_A; in icl_hpd_pin()
4963 return HPD_PORT_A + port - PORT_A; in ehl_hpd_pin()
4971 return HPD_PORT_A + port - PORT_A; in skl_hpd_pin()
5018 #define port_tc_name(port) ((port) - PORT_TC1 + '1')
5019 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
5037 return true; /* no strap for DDI-E */ in port_strap_detected()
5051 return !drm_WARN(display->drm, !display->platform.alderlake_p && in assert_has_icl_dsi()
5052 !display->platform.tigerlake && DISPLAY_VER(display) != 11, in assert_has_icl_dsi()
5060 for_each_intel_encoder(display->drm, encoder) { in port_in_use()
5062 if (encoder->port == port) in port_in_use()
5084 drm_dbg_kms(display->drm, in intel_ddi_init()
5093 drm_dbg_kms(display->drm, in intel_ddi_init()
5116 drm_dbg_kms(display->drm, "PORT %c / PHY %c reserved by HTI\n", in intel_ddi_init()
5133 drm_dbg_kms(display->drm, "VBT says port %c has lspcon\n", in intel_ddi_init()
5138 drm_dbg_kms(display->drm, in intel_ddi_init()
5139 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", in intel_ddi_init()
5145 display->snps.phy_failed_calibration & BIT(phy)) { in intel_ddi_init()
5146 drm_dbg_kms(display->drm, in intel_ddi_init()
5155 dig_port->aux_ch = AUX_CH_NONE; in intel_ddi_init()
5157 encoder = &dig_port->base; in intel_ddi_init()
5158 encoder->devdata = devdata; in intel_ddi_init()
5161 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, in intel_ddi_init()
5164 port_name(port - PORT_D_XELPD + PORT_D), in intel_ddi_init()
5169 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, in intel_ddi_init()
5179 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, in intel_ddi_init()
5187 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, in intel_ddi_init()
5194 mutex_init(&dig_port->hdcp.mutex); in intel_ddi_init()
5195 dig_port->hdcp.num_streams = 0; in intel_ddi_init()
5197 encoder->hotplug = intel_ddi_hotplug; in intel_ddi_init()
5198 encoder->compute_output_type = intel_ddi_compute_output_type; in intel_ddi_init()
5199 encoder->compute_config = intel_ddi_compute_config; in intel_ddi_init()
5200 encoder->compute_config_late = intel_ddi_compute_config_late; in intel_ddi_init()
5201 encoder->enable = intel_ddi_enable; in intel_ddi_init()
5202 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; in intel_ddi_init()
5203 encoder->pre_enable = intel_ddi_pre_enable; in intel_ddi_init()
5204 encoder->disable = intel_ddi_disable; in intel_ddi_init()
5205 encoder->post_pll_disable = intel_ddi_post_pll_disable; in intel_ddi_init()
5206 encoder->post_disable = intel_ddi_post_disable; in intel_ddi_init()
5207 encoder->update_pipe = intel_ddi_update_pipe; in intel_ddi_init()
5208 encoder->audio_enable = intel_audio_codec_enable; in intel_ddi_init()
5209 encoder->audio_disable = intel_audio_codec_disable; in intel_ddi_init()
5210 encoder->get_hw_state = intel_ddi_get_hw_state; in intel_ddi_init()
5211 encoder->sync_state = intel_ddi_sync_state; in intel_ddi_init()
5212 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; in intel_ddi_init()
5213 encoder->suspend = intel_ddi_encoder_suspend; in intel_ddi_init()
5214 encoder->shutdown = intel_ddi_encoder_shutdown; in intel_ddi_init()
5215 encoder->get_power_domains = intel_ddi_get_power_domains; in intel_ddi_init()
5217 encoder->type = INTEL_OUTPUT_DDI; in intel_ddi_init()
5218 encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port); in intel_ddi_init()
5219 encoder->port = port; in intel_ddi_init()
5220 encoder->cloneable = 0; in intel_ddi_init()
5221 encoder->pipe_mask = ~0; in intel_ddi_init()
5224 encoder->enable_clock = intel_mtl_pll_enable; in intel_ddi_init()
5225 encoder->disable_clock = intel_mtl_pll_disable; in intel_ddi_init()
5226 encoder->port_pll_type = intel_mtl_port_pll_type; in intel_ddi_init()
5227 encoder->get_config = mtl_ddi_get_config; in intel_ddi_init()
5228 } else if (display->platform.dg2) { in intel_ddi_init()
5229 encoder->enable_clock = intel_mpllb_enable; in intel_ddi_init()
5230 encoder->disable_clock = intel_mpllb_disable; in intel_ddi_init()
5231 encoder->get_config = dg2_ddi_get_config; in intel_ddi_init()
5232 } else if (display->platform.alderlake_s) { in intel_ddi_init()
5233 encoder->enable_clock = adls_ddi_enable_clock; in intel_ddi_init()
5234 encoder->disable_clock = adls_ddi_disable_clock; in intel_ddi_init()
5235 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; in intel_ddi_init()
5236 encoder->get_config = adls_ddi_get_config; in intel_ddi_init()
5237 } else if (display->platform.rocketlake) { in intel_ddi_init()
5238 encoder->enable_clock = rkl_ddi_enable_clock; in intel_ddi_init()
5239 encoder->disable_clock = rkl_ddi_disable_clock; in intel_ddi_init()
5240 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; in intel_ddi_init()
5241 encoder->get_config = rkl_ddi_get_config; in intel_ddi_init()
5242 } else if (display->platform.dg1) { in intel_ddi_init()
5243 encoder->enable_clock = dg1_ddi_enable_clock; in intel_ddi_init()
5244 encoder->disable_clock = dg1_ddi_disable_clock; in intel_ddi_init()
5245 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; in intel_ddi_init()
5246 encoder->get_config = dg1_ddi_get_config; in intel_ddi_init()
5247 } else if (display->platform.jasperlake || display->platform.elkhartlake) { in intel_ddi_init()
5249 encoder->enable_clock = jsl_ddi_tc_enable_clock; in intel_ddi_init()
5250 encoder->disable_clock = jsl_ddi_tc_disable_clock; in intel_ddi_init()
5251 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; in intel_ddi_init()
5252 encoder->port_pll_type = icl_ddi_tc_port_pll_type; in intel_ddi_init()
5253 encoder->get_config = icl_ddi_combo_get_config; in intel_ddi_init()
5255 encoder->enable_clock = icl_ddi_combo_enable_clock; in intel_ddi_init()
5256 encoder->disable_clock = icl_ddi_combo_disable_clock; in intel_ddi_init()
5257 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; in intel_ddi_init()
5258 encoder->get_config = icl_ddi_combo_get_config; in intel_ddi_init()
5262 encoder->enable_clock = icl_ddi_tc_enable_clock; in intel_ddi_init()
5263 encoder->disable_clock = icl_ddi_tc_disable_clock; in intel_ddi_init()
5264 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; in intel_ddi_init()
5265 encoder->port_pll_type = icl_ddi_tc_port_pll_type; in intel_ddi_init()
5266 encoder->get_config = icl_ddi_tc_get_config; in intel_ddi_init()
5268 encoder->enable_clock = icl_ddi_combo_enable_clock; in intel_ddi_init()
5269 encoder->disable_clock = icl_ddi_combo_disable_clock; in intel_ddi_init()
5270 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; in intel_ddi_init()
5271 encoder->get_config = icl_ddi_combo_get_config; in intel_ddi_init()
5273 } else if (display->platform.geminilake || display->platform.broxton) { in intel_ddi_init()
5274 /* BXT/GLK have fixed PLL->port mapping */ in intel_ddi_init()
5275 encoder->get_config = bxt_ddi_get_config; in intel_ddi_init()
5277 encoder->enable_clock = skl_ddi_enable_clock; in intel_ddi_init()
5278 encoder->disable_clock = skl_ddi_disable_clock; in intel_ddi_init()
5279 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; in intel_ddi_init()
5280 encoder->get_config = skl_ddi_get_config; in intel_ddi_init()
5281 } else if (display->platform.broadwell || display->platform.haswell) { in intel_ddi_init()
5282 encoder->enable_clock = hsw_ddi_enable_clock; in intel_ddi_init()
5283 encoder->disable_clock = hsw_ddi_disable_clock; in intel_ddi_init()
5284 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; in intel_ddi_init()
5285 encoder->get_config = hsw_ddi_get_config; in intel_ddi_init()
5289 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; in intel_ddi_init()
5290 } else if (display->platform.dg2) { in intel_ddi_init()
5291 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; in intel_ddi_init()
5294 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; in intel_ddi_init()
5296 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; in intel_ddi_init()
5299 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; in intel_ddi_init()
5301 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; in intel_ddi_init()
5302 } else if (display->platform.geminilake || display->platform.broxton) { in intel_ddi_init()
5303 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; in intel_ddi_init()
5305 encoder->set_signal_levels = hsw_set_signal_levels; in intel_ddi_init()
5311 encoder->hpd_pin = xelpd_hpd_pin(display, port); in intel_ddi_init()
5312 else if (display->platform.dg1) in intel_ddi_init()
5313 encoder->hpd_pin = dg1_hpd_pin(display, port); in intel_ddi_init()
5314 else if (display->platform.rocketlake) in intel_ddi_init()
5315 encoder->hpd_pin = rkl_hpd_pin(display, port); in intel_ddi_init()
5317 encoder->hpd_pin = tgl_hpd_pin(display, port); in intel_ddi_init()
5318 else if (display->platform.jasperlake || display->platform.elkhartlake) in intel_ddi_init()
5319 encoder->hpd_pin = ehl_hpd_pin(display, port); in intel_ddi_init()
5321 encoder->hpd_pin = icl_hpd_pin(display, port); in intel_ddi_init()
5322 else if (DISPLAY_VER(display) == 9 && !display->platform.broxton) in intel_ddi_init()
5323 encoder->hpd_pin = skl_hpd_pin(display, port); in intel_ddi_init()
5325 encoder->hpd_pin = intel_hpd_pin_default(port); in intel_ddi_init()
5329 dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) || in intel_ddi_init()
5332 dig_port->ddi_a_4_lanes = DISPLAY_VER(display) < 11 && ddi_buf_ctl & DDI_A_4_LANES; in intel_ddi_init()
5334 dig_port->dp.output_reg = INVALID_MMIO_REG; in intel_ddi_init()
5335 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); in intel_ddi_init()
5338 dig_port->aux_ch = intel_dp_aux_ch(encoder); in intel_ddi_init()
5339 if (dig_port->aux_ch == AUX_CH_NONE) in intel_ddi_init()
5351 drm_dbg_kms(display->drm, in intel_ddi_init()
5352 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", in intel_ddi_init()
5355 is_legacy ? "legacy" : "non-legacy"); in intel_ddi_init()
5358 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; in intel_ddi_init()
5359 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; in intel_ddi_init()
5361 dig_port->lock = intel_tc_port_lock; in intel_ddi_init()
5362 dig_port->unlock = intel_tc_port_unlock; in intel_ddi_init()
5368 drm_WARN_ON(display->drm, port > PORT_I); in intel_ddi_init()
5369 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(display, port); in intel_ddi_init()
5373 dig_port->connected = intel_tc_port_connected; in intel_ddi_init()
5375 dig_port->connected = lpt_digital_port_connected; in intel_ddi_init()
5376 } else if (display->platform.geminilake || display->platform.broxton) { in intel_ddi_init()
5377 dig_port->connected = bdw_digital_port_connected; in intel_ddi_init()
5379 dig_port->connected = lpt_digital_port_connected; in intel_ddi_init()
5380 } else if (display->platform.broadwell) { in intel_ddi_init()
5382 dig_port->connected = bdw_digital_port_connected; in intel_ddi_init()
5384 dig_port->connected = lpt_digital_port_connected; in intel_ddi_init()
5385 } else if (display->platform.haswell) { in intel_ddi_init()
5387 dig_port->connected = hsw_digital_port_connected; in intel_ddi_init()
5389 dig_port->connected = lpt_digital_port_connected; in intel_ddi_init()
5398 dig_port->hpd_pulse = intel_dp_hpd_pulse; in intel_ddi_init()
5400 if (dig_port->dp.mso_link_count) in intel_ddi_init()
5401 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(display); in intel_ddi_init()
5405 * In theory we don't need the encoder->type check, in intel_ddi_init()
5408 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { in intel_ddi_init()
5416 drm_encoder_cleanup(&encoder->base); in intel_ddi_init()