Lines Matching full:display
31 #include <drm/display/drm_dp_helper.h>
32 #include <drm/display/drm_scdc_helper.h>
112 static bool has_buf_trans_select(struct intel_display *display) in has_buf_trans_select() argument
114 return DISPLAY_VER(display) < 10 && !display->platform.broxton; in has_buf_trans_select()
117 static bool has_iboost(struct intel_display *display) in has_iboost() argument
119 return DISPLAY_VER(display) == 9 && !display->platform.broxton; in has_iboost()
130 struct intel_display *display = to_intel_display(encoder); in hsw_prepare_dp_ddi_buffers() local
137 if (drm_WARN_ON_ONCE(display->drm, !trans)) in hsw_prepare_dp_ddi_buffers()
141 if (has_iboost(display) && in hsw_prepare_dp_ddi_buffers()
146 intel_de_write(display, DDI_BUF_TRANS_LO(port, i), in hsw_prepare_dp_ddi_buffers()
148 intel_de_write(display, DDI_BUF_TRANS_HI(port, i), in hsw_prepare_dp_ddi_buffers()
161 struct intel_display *display = to_intel_display(encoder); in hsw_prepare_hdmi_ddi_buffers() local
169 if (drm_WARN_ON_ONCE(display->drm, !trans)) in hsw_prepare_hdmi_ddi_buffers()
173 if (has_iboost(display) && in hsw_prepare_hdmi_ddi_buffers()
178 intel_de_write(display, DDI_BUF_TRANS_LO(port, 9), in hsw_prepare_hdmi_ddi_buffers()
180 intel_de_write(display, DDI_BUF_TRANS_HI(port, 9), in hsw_prepare_hdmi_ddi_buffers()
184 static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port) in intel_ddi_buf_status_reg() argument
186 if (DISPLAY_VER(display) >= 14) in intel_ddi_buf_status_reg()
187 return XELPDP_PORT_BUF_CTL1(display, port); in intel_ddi_buf_status_reg()
192 void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port) in intel_wait_ddi_buf_idle() argument
202 if (display->platform.broxton) { in intel_wait_ddi_buf_idle()
208 if (intel_de_wait_for_set(display, intel_ddi_buf_status_reg(display, port), in intel_wait_ddi_buf_idle()
210 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n", in intel_wait_ddi_buf_idle()
216 struct intel_display *display = to_intel_display(encoder); in intel_wait_ddi_buf_active() local
227 if (DISPLAY_VER(display) < 10) { in intel_wait_ddi_buf_active()
233 if (intel_de_wait_for_clear(display, intel_ddi_buf_status_reg(display, port), in intel_wait_ddi_buf_active()
235 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n", in intel_wait_ddi_buf_active()
349 struct intel_display *display = to_intel_display(encoder); in intel_ddi_init_dp_buf_reg() local
362 if (DISPLAY_VER(display) >= 14) { in intel_ddi_init_dp_buf_reg()
369 if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { in intel_ddi_init_dp_buf_reg()
375 if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) { in intel_ddi_init_dp_buf_reg()
382 static int icl_calc_tbt_pll_link(struct intel_display *display, enum port port) in icl_calc_tbt_pll_link() argument
384 u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; in icl_calc_tbt_pll_link()
416 struct intel_display *display = to_intel_display(crtc_state); in intel_ddi_set_dp_msa() local
423 drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)); in intel_ddi_set_dp_msa()
446 drm_WARN_ON(display->drm, crtc_state->limited_color_range && in intel_ddi_set_dp_msa()
469 intel_de_write(display, TRANS_MSA_MISC(display, cpu_transcoder), in intel_ddi_set_dp_msa()
485 struct intel_display *display = to_intel_display(crtc_state); in intel_ddi_config_transcoder_dp2() local
489 if (!HAS_DP20(display)) in intel_ddi_config_transcoder_dp2()
495 intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val); in intel_ddi_config_transcoder_dp2()
508 struct intel_display *display = to_intel_display(crtc_state); in intel_ddi_transcoder_func_reg_val_get() local
517 if (DISPLAY_VER(display) >= 12) in intel_ddi_transcoder_func_reg_val_get()
579 if (DISPLAY_VER(display) >= 14) in intel_ddi_transcoder_func_reg_val_get()
592 if (DISPLAY_VER(display) >= 12) { in intel_ddi_transcoder_func_reg_val_get()
596 drm_WARN_ON(display->drm, in intel_ddi_transcoder_func_reg_val_get()
605 if (IS_DISPLAY_VER(display, 8, 10) && in intel_ddi_transcoder_func_reg_val_get()
620 struct intel_display *display = to_intel_display(crtc_state); in intel_ddi_enable_transcoder_func() local
623 if (DISPLAY_VER(display) >= 11) { in intel_ddi_enable_transcoder_func()
635 intel_de_write(display, in intel_ddi_enable_transcoder_func()
636 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), in intel_ddi_enable_transcoder_func()
640 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), in intel_ddi_enable_transcoder_func()
654 struct intel_display *display = to_intel_display(crtc_state); in intel_ddi_config_transcoder_func() local
662 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), in intel_ddi_config_transcoder_func()
674 struct intel_display *display = to_intel_display(crtc_state); in intel_ddi_disable_transcoder_func() local
679 if (DISPLAY_VER(display) >= 11) in intel_ddi_disable_transcoder_func()
680 intel_de_write(display, in intel_ddi_disable_transcoder_func()
681 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), in intel_ddi_disable_transcoder_func()
684 ctl = intel_de_read(display, in intel_ddi_disable_transcoder_func()
685 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); in intel_ddi_disable_transcoder_func()
691 if (IS_DISPLAY_VER(display, 8, 10)) in intel_ddi_disable_transcoder_func()
695 if (DISPLAY_VER(display) >= 12) { in intel_ddi_disable_transcoder_func()
704 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), in intel_ddi_disable_transcoder_func()
710 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && in intel_ddi_disable_transcoder_func()
712 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); in intel_ddi_disable_transcoder_func()
722 struct intel_display *display = to_intel_display(intel_encoder); in intel_ddi_toggle_hdcp_bits() local
726 wakeref = intel_display_power_get_if_enabled(display, in intel_ddi_toggle_hdcp_bits()
728 if (drm_WARN_ON(display->drm, !wakeref)) in intel_ddi_toggle_hdcp_bits()
731 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), in intel_ddi_toggle_hdcp_bits()
733 intel_display_power_put(display, intel_encoder->power_domain, wakeref); in intel_ddi_toggle_hdcp_bits()
739 struct intel_display *display = to_intel_display(intel_connector); in intel_ddi_connector_get_hw_state() local
749 wakeref = intel_display_power_get_if_enabled(display, in intel_ddi_connector_get_hw_state()
760 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) in intel_ddi_connector_get_hw_state()
765 ddi_mode = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & in intel_ddi_connector_get_hw_state()
771 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { in intel_ddi_connector_get_hw_state()
776 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { in intel_ddi_connector_get_hw_state()
782 } else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) { in intel_ddi_connector_get_hw_state()
790 intel_display_power_put(display, encoder->power_domain, wakeref); in intel_ddi_connector_get_hw_state()
798 struct intel_display *display = to_intel_display(encoder); in intel_ddi_get_encoder_pipes() local
808 wakeref = intel_display_power_get_if_enabled(display, in intel_ddi_get_encoder_pipes()
813 tmp = intel_de_read(display, DDI_BUF_CTL(port)); in intel_ddi_get_encoder_pipes()
817 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) { in intel_ddi_get_encoder_pipes()
818 tmp = intel_de_read(display, in intel_ddi_get_encoder_pipes()
819 TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP)); in intel_ddi_get_encoder_pipes()
840 for_each_pipe(display, p) { in intel_ddi_get_encoder_pipes()
845 trans_wakeref = intel_display_power_get_if_enabled(display, in intel_ddi_get_encoder_pipes()
850 if (DISPLAY_VER(display) >= 12) { in intel_ddi_get_encoder_pipes()
858 tmp = intel_de_read(display, in intel_ddi_get_encoder_pipes()
859 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); in intel_ddi_get_encoder_pipes()
860 intel_display_power_put(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder), in intel_ddi_get_encoder_pipes()
870 else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) in intel_ddi_get_encoder_pipes()
877 drm_dbg_kms(display->drm, in intel_ddi_get_encoder_pipes()
900 drm_dbg_kms(display->drm, in intel_ddi_get_encoder_pipes()
908 drm_dbg_kms(display->drm, in intel_ddi_get_encoder_pipes()
916 if (*pipe_mask && (display->platform.geminilake || display->platform.broxton)) { in intel_ddi_get_encoder_pipes()
917 tmp = intel_de_read(display, BXT_PHY_CTL(port)); in intel_ddi_get_encoder_pipes()
921 drm_err(display->drm, in intel_ddi_get_encoder_pipes()
926 intel_display_power_put(display, encoder->power_domain, wakeref); in intel_ddi_get_encoder_pipes()
949 struct intel_display *display = to_intel_display(dig_port); in intel_ddi_main_link_aux_domain() local
965 return intel_display_power_aux_io_domain(display, dig_port->aux_ch); in intel_ddi_main_link_aux_domain()
966 else if (DISPLAY_VER(display) < 14 && in intel_ddi_main_link_aux_domain()
978 struct intel_display *display = to_intel_display(dig_port); in main_link_aux_power_domain_get() local
982 drm_WARN_ON(display->drm, dig_port->aux_wakeref); in main_link_aux_power_domain_get()
987 dig_port->aux_wakeref = intel_display_power_get(display, domain); in main_link_aux_power_domain_get()
994 struct intel_display *display = to_intel_display(dig_port); in main_link_aux_power_domain_put() local
1003 intel_display_power_put(display, domain, wf); in main_link_aux_power_domain_put()
1009 struct intel_display *display = to_intel_display(encoder); in intel_ddi_get_power_domains() local
1017 if (drm_WARN_ON(display->drm, in intel_ddi_get_power_domains()
1024 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); in intel_ddi_get_power_domains()
1025 dig_port->ddi_io_wakeref = intel_display_power_get(display, in intel_ddi_get_power_domains()
1035 struct intel_display *display = to_intel_display(crtc_state); in intel_ddi_enable_transcoder_clock() local
1043 if (DISPLAY_VER(display) >= 13) in intel_ddi_enable_transcoder_clock()
1045 else if (DISPLAY_VER(display) >= 12) in intel_ddi_enable_transcoder_clock()
1050 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); in intel_ddi_enable_transcoder_clock()
1055 struct intel_display *display = to_intel_display(crtc_state); in intel_ddi_disable_transcoder_clock() local
1062 if (DISPLAY_VER(display) >= 12) in intel_ddi_disable_transcoder_clock()
1067 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); in intel_ddi_disable_transcoder_clock()
1070 static void _skl_ddi_set_iboost(struct intel_display *display, in _skl_ddi_set_iboost() argument
1075 tmp = intel_de_read(display, DISPIO_CR_TX_BMU_CR0); in _skl_ddi_set_iboost()
1081 intel_de_write(display, DISPIO_CR_TX_BMU_CR0, tmp); in _skl_ddi_set_iboost()
1088 struct intel_display *display = to_intel_display(encoder); in skl_ddi_set_iboost() local
1102 if (drm_WARN_ON_ONCE(display->drm, !trans)) in skl_ddi_set_iboost()
1110 drm_err(display->drm, "Invalid I_boost value %u\n", iboost); in skl_ddi_set_iboost()
1114 _skl_ddi_set_iboost(display, encoder->port, iboost); in skl_ddi_set_iboost()
1117 _skl_ddi_set_iboost(display, PORT_E, iboost); in skl_ddi_set_iboost()
1123 struct intel_display *display = to_intel_display(intel_dp); in intel_ddi_dp_voltage_max() local
1129 if (drm_WARN_ON(display->drm, n_entries < 1)) in intel_ddi_dp_voltage_max()
1131 if (drm_WARN_ON(display->drm, in intel_ddi_dp_voltage_max()
1164 struct intel_display *display = to_intel_display(encoder); in icl_ddi_combo_vswing_program() local
1171 if (drm_WARN_ON_ONCE(display->drm, !trans)) in icl_ddi_combo_vswing_program()
1179 intel_de_rmw(display, ICL_PORT_CL_DW10(phy), val, in icl_ddi_combo_vswing_program()
1184 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); in icl_ddi_combo_vswing_program()
1191 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); in icl_ddi_combo_vswing_program()
1197 intel_de_rmw(display, ICL_PORT_TX_DW2_LN(ln, phy), in icl_ddi_combo_vswing_program()
1209 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), in icl_ddi_combo_vswing_program()
1220 intel_de_rmw(display, ICL_PORT_TX_DW7_LN(ln, phy), in icl_ddi_combo_vswing_program()
1229 struct intel_display *display = to_intel_display(encoder); in icl_combo_phy_set_signal_levels() local
1239 val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy)); in icl_combo_phy_set_signal_levels()
1244 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val); in icl_combo_phy_set_signal_levels()
1254 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), in icl_combo_phy_set_signal_levels()
1260 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), in icl_combo_phy_set_signal_levels()
1264 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); in icl_combo_phy_set_signal_levels()
1266 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); in icl_combo_phy_set_signal_levels()
1272 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); in icl_combo_phy_set_signal_levels()
1274 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); in icl_combo_phy_set_signal_levels()
1280 struct intel_display *display = to_intel_display(encoder); in icl_mg_phy_set_signal_levels() local
1289 if (drm_WARN_ON_ONCE(display->drm, !trans)) in icl_mg_phy_set_signal_levels()
1293 intel_de_rmw(display, MG_TX1_LINK_PARAMS(ln, tc_port), in icl_mg_phy_set_signal_levels()
1295 intel_de_rmw(display, MG_TX2_LINK_PARAMS(ln, tc_port), in icl_mg_phy_set_signal_levels()
1305 intel_de_rmw(display, MG_TX1_SWINGCTRL(ln, tc_port), in icl_mg_phy_set_signal_levels()
1311 intel_de_rmw(display, MG_TX2_SWINGCTRL(ln, tc_port), in icl_mg_phy_set_signal_levels()
1322 intel_de_rmw(display, MG_TX1_DRVCTRL(ln, tc_port), in icl_mg_phy_set_signal_levels()
1331 intel_de_rmw(display, MG_TX2_DRVCTRL(ln, tc_port), in icl_mg_phy_set_signal_levels()
1347 intel_de_rmw(display, MG_CLKHUB(ln, tc_port), in icl_mg_phy_set_signal_levels()
1354 intel_de_rmw(display, MG_TX1_DCC(ln, tc_port), in icl_mg_phy_set_signal_levels()
1361 intel_de_rmw(display, MG_TX2_DCC(ln, tc_port), in icl_mg_phy_set_signal_levels()
1371 intel_de_rmw(display, MG_TX1_PISO_READLOAD(ln, tc_port), in icl_mg_phy_set_signal_levels()
1373 intel_de_rmw(display, MG_TX2_PISO_READLOAD(ln, tc_port), in icl_mg_phy_set_signal_levels()
1381 struct intel_display *display = to_intel_display(encoder); in tgl_dkl_phy_set_signal_levels() local
1390 if (drm_WARN_ON_ONCE(display->drm, !trans)) in tgl_dkl_phy_set_signal_levels()
1396 intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); in tgl_dkl_phy_set_signal_levels()
1400 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln), in tgl_dkl_phy_set_signal_levels()
1410 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln), in tgl_dkl_phy_set_signal_levels()
1418 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), in tgl_dkl_phy_set_signal_levels()
1421 if (display->platform.alderlake_p) { in tgl_dkl_phy_set_signal_levels()
1437 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), in tgl_dkl_phy_set_signal_levels()
1448 struct intel_display *display = to_intel_display(intel_dp); in translate_signal_level() local
1456 drm_WARN(display->drm, 1, in translate_signal_level()
1483 struct intel_display *display = to_intel_display(encoder); in intel_ddi_level() local
1488 if (drm_WARN_ON_ONCE(display->drm, !trans)) in intel_ddi_level()
1497 if (drm_WARN_ON_ONCE(display->drm, level >= n_entries)) in intel_ddi_level()
1507 struct intel_display *display = to_intel_display(encoder); in hsw_set_signal_levels() local
1513 if (has_iboost(display)) in hsw_set_signal_levels()
1522 drm_dbg_kms(display->drm, "Using signal levels %08x\n", in hsw_set_signal_levels()
1528 intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP); in hsw_set_signal_levels()
1529 intel_de_posting_read(display, DDI_BUF_CTL(port)); in hsw_set_signal_levels()
1532 static void _icl_ddi_enable_clock(struct intel_display *display, i915_reg_t reg, in _icl_ddi_enable_clock() argument
1535 mutex_lock(&display->dpll.lock); in _icl_ddi_enable_clock()
1537 intel_de_rmw(display, reg, clk_sel_mask, clk_sel); in _icl_ddi_enable_clock()
1543 intel_de_rmw(display, reg, clk_off, 0); in _icl_ddi_enable_clock()
1545 mutex_unlock(&display->dpll.lock); in _icl_ddi_enable_clock()
1548 static void _icl_ddi_disable_clock(struct intel_display *display, i915_reg_t reg, in _icl_ddi_disable_clock() argument
1551 mutex_lock(&display->dpll.lock); in _icl_ddi_disable_clock()
1553 intel_de_rmw(display, reg, 0, clk_off); in _icl_ddi_disable_clock()
1555 mutex_unlock(&display->dpll.lock); in _icl_ddi_disable_clock()
1558 static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t reg, in _icl_ddi_is_clock_enabled() argument
1561 return !(intel_de_read(display, reg) & clk_off); in _icl_ddi_is_clock_enabled()
1565 _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg, in _icl_ddi_get_pll() argument
1570 id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift; in _icl_ddi_get_pll()
1572 return intel_get_shared_dpll_by_id(display, id); in _icl_ddi_get_pll()
1578 struct intel_display *display = to_intel_display(encoder); in adls_ddi_enable_clock() local
1582 if (drm_WARN_ON(display->drm, !pll)) in adls_ddi_enable_clock()
1585 _icl_ddi_enable_clock(display, ADLS_DPCLKA_CFGCR(phy), in adls_ddi_enable_clock()
1593 struct intel_display *display = to_intel_display(encoder); in adls_ddi_disable_clock() local
1596 _icl_ddi_disable_clock(display, ADLS_DPCLKA_CFGCR(phy), in adls_ddi_disable_clock()
1602 struct intel_display *display = to_intel_display(encoder); in adls_ddi_is_clock_enabled() local
1605 return _icl_ddi_is_clock_enabled(display, ADLS_DPCLKA_CFGCR(phy), in adls_ddi_is_clock_enabled()
1611 struct intel_display *display = to_intel_display(encoder); in adls_ddi_get_pll() local
1614 return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy), in adls_ddi_get_pll()
1622 struct intel_display *display = to_intel_display(encoder); in rkl_ddi_enable_clock() local
1626 if (drm_WARN_ON(display->drm, !pll)) in rkl_ddi_enable_clock()
1629 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, in rkl_ddi_enable_clock()
1637 struct intel_display *display = to_intel_display(encoder); in rkl_ddi_disable_clock() local
1640 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, in rkl_ddi_disable_clock()
1646 struct intel_display *display = to_intel_display(encoder); in rkl_ddi_is_clock_enabled() local
1649 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, in rkl_ddi_is_clock_enabled()
1655 struct intel_display *display = to_intel_display(encoder); in rkl_ddi_get_pll() local
1658 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, in rkl_ddi_get_pll()
1666 struct intel_display *display = to_intel_display(encoder); in dg1_ddi_enable_clock() local
1670 if (drm_WARN_ON(display->drm, !pll)) in dg1_ddi_enable_clock()
1677 if (drm_WARN_ON(display->drm, in dg1_ddi_enable_clock()
1682 _icl_ddi_enable_clock(display, DG1_DPCLKA_CFGCR0(phy), in dg1_ddi_enable_clock()
1690 struct intel_display *display = to_intel_display(encoder); in dg1_ddi_disable_clock() local
1693 _icl_ddi_disable_clock(display, DG1_DPCLKA_CFGCR0(phy), in dg1_ddi_disable_clock()
1699 struct intel_display *display = to_intel_display(encoder); in dg1_ddi_is_clock_enabled() local
1702 return _icl_ddi_is_clock_enabled(display, DG1_DPCLKA_CFGCR0(phy), in dg1_ddi_is_clock_enabled()
1708 struct intel_display *display = to_intel_display(encoder); in dg1_ddi_get_pll() local
1713 val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy)); in dg1_ddi_get_pll()
1726 return intel_get_shared_dpll_by_id(display, id); in dg1_ddi_get_pll()
1732 struct intel_display *display = to_intel_display(encoder); in icl_ddi_combo_enable_clock() local
1736 if (drm_WARN_ON(display->drm, !pll)) in icl_ddi_combo_enable_clock()
1739 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, in icl_ddi_combo_enable_clock()
1747 struct intel_display *display = to_intel_display(encoder); in icl_ddi_combo_disable_clock() local
1750 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, in icl_ddi_combo_disable_clock()
1756 struct intel_display *display = to_intel_display(encoder); in icl_ddi_combo_is_clock_enabled() local
1759 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, in icl_ddi_combo_is_clock_enabled()
1765 struct intel_display *display = to_intel_display(encoder); in icl_ddi_combo_get_pll() local
1768 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, in icl_ddi_combo_get_pll()
1776 struct intel_display *display = to_intel_display(encoder); in jsl_ddi_tc_enable_clock() local
1780 if (drm_WARN_ON(display->drm, !pll)) in jsl_ddi_tc_enable_clock()
1787 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); in jsl_ddi_tc_enable_clock()
1794 struct intel_display *display = to_intel_display(encoder); in jsl_ddi_tc_disable_clock() local
1799 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); in jsl_ddi_tc_disable_clock()
1804 struct intel_display *display = to_intel_display(encoder); in jsl_ddi_tc_is_clock_enabled() local
1808 tmp = intel_de_read(display, DDI_CLK_SEL(port)); in jsl_ddi_tc_is_clock_enabled()
1819 struct intel_display *display = to_intel_display(encoder); in icl_ddi_tc_enable_clock() local
1824 if (drm_WARN_ON(display->drm, !pll)) in icl_ddi_tc_enable_clock()
1827 intel_de_write(display, DDI_CLK_SEL(port), in icl_ddi_tc_enable_clock()
1830 mutex_lock(&display->dpll.lock); in icl_ddi_tc_enable_clock()
1832 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, in icl_ddi_tc_enable_clock()
1835 mutex_unlock(&display->dpll.lock); in icl_ddi_tc_enable_clock()
1840 struct intel_display *display = to_intel_display(encoder); in icl_ddi_tc_disable_clock() local
1844 mutex_lock(&display->dpll.lock); in icl_ddi_tc_disable_clock()
1846 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, in icl_ddi_tc_disable_clock()
1849 mutex_unlock(&display->dpll.lock); in icl_ddi_tc_disable_clock()
1851 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); in icl_ddi_tc_disable_clock()
1856 struct intel_display *display = to_intel_display(encoder); in icl_ddi_tc_is_clock_enabled() local
1861 tmp = intel_de_read(display, DDI_CLK_SEL(port)); in icl_ddi_tc_is_clock_enabled()
1866 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); in icl_ddi_tc_is_clock_enabled()
1873 struct intel_display *display = to_intel_display(encoder); in icl_ddi_tc_get_pll() local
1879 tmp = intel_de_read(display, DDI_CLK_SEL(port)); in icl_ddi_tc_get_pll()
1898 return intel_get_shared_dpll_by_id(display, id); in icl_ddi_tc_get_pll()
1903 struct intel_display *display = to_intel_display(encoder->base.dev); in bxt_ddi_get_pll() local
1921 return intel_get_shared_dpll_by_id(display, id); in bxt_ddi_get_pll()
1927 struct intel_display *display = to_intel_display(encoder); in skl_ddi_enable_clock() local
1931 if (drm_WARN_ON(display->drm, !pll)) in skl_ddi_enable_clock()
1934 mutex_lock(&display->dpll.lock); in skl_ddi_enable_clock()
1936 intel_de_rmw(display, DPLL_CTRL2, in skl_ddi_enable_clock()
1942 mutex_unlock(&display->dpll.lock); in skl_ddi_enable_clock()
1947 struct intel_display *display = to_intel_display(encoder); in skl_ddi_disable_clock() local
1950 mutex_lock(&display->dpll.lock); in skl_ddi_disable_clock()
1952 intel_de_rmw(display, DPLL_CTRL2, in skl_ddi_disable_clock()
1955 mutex_unlock(&display->dpll.lock); in skl_ddi_disable_clock()
1960 struct intel_display *display = to_intel_display(encoder); in skl_ddi_is_clock_enabled() local
1967 return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); in skl_ddi_is_clock_enabled()
1972 struct intel_display *display = to_intel_display(encoder); in skl_ddi_get_pll() local
1977 tmp = intel_de_read(display, DPLL_CTRL2); in skl_ddi_get_pll()
1989 return intel_get_shared_dpll_by_id(display, id); in skl_ddi_get_pll()
1995 struct intel_display *display = to_intel_display(encoder); in hsw_ddi_enable_clock() local
1999 if (drm_WARN_ON(display->drm, !pll)) in hsw_ddi_enable_clock()
2002 intel_de_write(display, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); in hsw_ddi_enable_clock()
2007 struct intel_display *display = to_intel_display(encoder); in hsw_ddi_disable_clock() local
2010 intel_de_write(display, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); in hsw_ddi_disable_clock()
2015 struct intel_display *display = to_intel_display(encoder); in hsw_ddi_is_clock_enabled() local
2018 return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; in hsw_ddi_is_clock_enabled()
2023 struct intel_display *display = to_intel_display(encoder); in hsw_ddi_get_pll() local
2028 tmp = intel_de_read(display, PORT_CLK_SEL(port)); in hsw_ddi_get_pll()
2056 return intel_get_shared_dpll_by_id(display, id); in hsw_ddi_get_pll()
2074 struct intel_display *display = to_intel_display(encoder); in intel_ddi_sanitize_encoder_pll_mapping() local
2094 if (drm_WARN_ON(display->drm, is_mst)) in intel_ddi_sanitize_encoder_pll_mapping()
2109 for_each_intel_encoder(display->drm, other_encoder) { in intel_ddi_sanitize_encoder_pll_mapping()
2113 if (drm_WARN_ON(display->drm, in intel_ddi_sanitize_encoder_pll_mapping()
2128 drm_dbg_kms(display->drm, in intel_ddi_sanitize_encoder_pll_mapping()
2136 tgl_dkl_phy_check_and_rewrite(struct intel_display *display, in tgl_dkl_phy_check_and_rewrite() argument
2139 if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0))) in tgl_dkl_phy_check_and_rewrite()
2140 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); in tgl_dkl_phy_check_and_rewrite()
2141 if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1))) in tgl_dkl_phy_check_and_rewrite()
2142 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); in tgl_dkl_phy_check_and_rewrite()
2149 struct intel_display *display = to_intel_display(crtc_state); in icl_program_mg_dp_mode() local
2154 if (DISPLAY_VER(display) >= 14) in icl_program_mg_dp_mode()
2161 if (DISPLAY_VER(display) >= 12) { in icl_program_mg_dp_mode()
2162 ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)); in icl_program_mg_dp_mode()
2163 ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)); in icl_program_mg_dp_mode()
2165 ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port)); in icl_program_mg_dp_mode()
2166 ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port)); in icl_program_mg_dp_mode()
2178 drm_WARN_ON(display->drm, in icl_program_mg_dp_mode()
2223 if (DISPLAY_VER(display) >= 12) { in icl_program_mg_dp_mode()
2224 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); in icl_program_mg_dp_mode()
2225 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); in icl_program_mg_dp_mode()
2227 if (IS_DISPLAY_VER(display, 12, 13)) in icl_program_mg_dp_mode()
2228 tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1); in icl_program_mg_dp_mode()
2231 intel_de_write(display, MG_DP_MODE(0, tc_port), ln0); in icl_program_mg_dp_mode()
2232 intel_de_write(display, MG_DP_MODE(1, tc_port), ln1); in icl_program_mg_dp_mode()
2248 struct intel_display *display = to_intel_display(encoder); in dp_tp_ctl_reg() local
2250 if (DISPLAY_VER(display) >= 12) in dp_tp_ctl_reg()
2251 return TGL_DP_TP_CTL(display, in dp_tp_ctl_reg()
2260 struct intel_display *display = to_intel_display(encoder); in dp_tp_status_reg() local
2262 if (DISPLAY_VER(display) >= 12) in dp_tp_status_reg()
2263 return TGL_DP_TP_STATUS(display, in dp_tp_status_reg()
2272 struct intel_display *display = to_intel_display(encoder); in intel_ddi_clear_act_sent() local
2274 intel_de_write(display, dp_tp_status_reg(encoder, crtc_state), in intel_ddi_clear_act_sent()
2281 struct intel_display *display = to_intel_display(encoder); in intel_ddi_wait_for_act_sent() local
2283 if (intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), in intel_ddi_wait_for_act_sent()
2285 drm_err(display->drm, "Timed out waiting for ACT sent\n"); in intel_ddi_wait_for_act_sent()
2292 struct intel_display *display = to_intel_display(intel_dp); in intel_dp_sink_set_msa_timing_par_ignore_state() local
2299 drm_dbg_kms(display->drm, in intel_dp_sink_set_msa_timing_par_ignore_state()
2308 struct intel_display *display = to_intel_display(intel_dp); in intel_dp_sink_set_fec_ready() local
2315 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n", in intel_dp_sink_set_fec_ready()
2321 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n"); in intel_dp_sink_set_fec_ready()
2338 struct intel_display *display = to_intel_display(aux->drm_dev); in wait_for_fec_detected() local
2348 drm_dbg_kms(display->drm, in wait_for_fec_detected()
2361 struct intel_display *display = to_intel_display(encoder); in intel_ddi_wait_for_fec_status() local
2369 ret = intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), in intel_ddi_wait_for_fec_status()
2372 ret = intel_de_wait_for_clear(display, dp_tp_status_reg(encoder, crtc_state), in intel_ddi_wait_for_fec_status()
2376 drm_err(display->drm, in intel_ddi_wait_for_fec_status()
2397 struct intel_display *display = to_intel_display(encoder); in intel_ddi_enable_fec() local
2404 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), in intel_ddi_enable_fec()
2407 if (DISPLAY_VER(display) < 30) in intel_ddi_enable_fec()
2415 drm_dbg_kms(display->drm, "Retry FEC enabling\n"); in intel_ddi_enable_fec()
2417 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), in intel_ddi_enable_fec()
2424 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), in intel_ddi_enable_fec()
2432 drm_err(display->drm, "Failed to enable FEC after retries\n"); in intel_ddi_enable_fec()
2438 struct intel_display *display = to_intel_display(encoder); in intel_ddi_disable_fec() local
2443 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), in intel_ddi_disable_fec()
2445 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); in intel_ddi_disable_fec()
2451 struct intel_display *display = to_intel_display(encoder); in intel_ddi_power_up_lanes() local
2457 intel_combo_phy_power_up_lanes(display, phy, false, in intel_ddi_power_up_lanes()
2467 static u8 intel_ddi_splitter_pipe_mask(struct intel_display *display) in intel_ddi_splitter_pipe_mask() argument
2469 if (DISPLAY_VER(display) > 20) in intel_ddi_splitter_pipe_mask()
2471 else if (display->platform.alderlake_p) in intel_ddi_splitter_pipe_mask()
2480 struct intel_display *display = to_intel_display(pipe_config); in intel_ddi_mso_get_config() local
2485 if (!HAS_MSO(display)) in intel_ddi_mso_get_config()
2488 dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); in intel_ddi_mso_get_config()
2494 if (drm_WARN_ON(display->drm, !(intel_ddi_splitter_pipe_mask(display) & BIT(pipe)))) { in intel_ddi_mso_get_config()
2501 drm_WARN(display->drm, true, in intel_ddi_mso_get_config()
2517 struct intel_display *display = to_intel_display(crtc_state); in intel_ddi_mso_configure() local
2522 if (!HAS_MSO(display)) in intel_ddi_mso_configure()
2534 intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe), in intel_ddi_mso_configure()
2542 struct intel_display *display = to_intel_display(encoder); in mtl_ddi_enable_d2d() local
2547 if (DISPLAY_VER(display) < 14) in mtl_ddi_enable_d2d()
2550 if (DISPLAY_VER(display) >= 20) { in mtl_ddi_enable_d2d()
2555 reg = XELPDP_PORT_BUF_CTL1(display, port); in mtl_ddi_enable_d2d()
2560 intel_de_rmw(display, reg, 0, set_bits); in mtl_ddi_enable_d2d()
2561 if (wait_for_us(intel_de_read(display, reg) & wait_bits, 100)) { in mtl_ddi_enable_d2d()
2562 drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", in mtl_ddi_enable_d2d()
2570 struct intel_display *display = to_intel_display(encoder); in mtl_port_buf_ctl_program() local
2585 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), in mtl_port_buf_ctl_program()
2592 struct intel_display *display = to_intel_display(encoder); in mtl_port_buf_ctl_io_selection() local
2598 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), in mtl_port_buf_ctl_io_selection()
2682 * Train Display Port" step. Note that steps that are specific to in mtl_ddi_pre_enable_dp()
2725 struct intel_display *display = to_intel_display(encoder); in tgl_ddi_pre_enable_dp() local
2770 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); in tgl_ddi_pre_enable_dp()
2771 dig_port->ddi_io_wakeref = intel_display_power_get(display, in tgl_ddi_pre_enable_dp()
2780 * Train Display Port" step. Note that steps that are specific to in tgl_ddi_pre_enable_dp()
2872 struct intel_display *display = to_intel_display(encoder); in hsw_ddi_pre_enable_dp() local
2878 if (DISPLAY_VER(display) < 11) in hsw_ddi_pre_enable_dp()
2879 drm_WARN_ON(display->drm, in hsw_ddi_pre_enable_dp()
2882 drm_WARN_ON(display->drm, is_mst && port == PORT_A); in hsw_ddi_pre_enable_dp()
2899 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); in hsw_ddi_pre_enable_dp()
2900 dig_port->ddi_io_wakeref = intel_display_power_get(display, in hsw_ddi_pre_enable_dp()
2906 if (has_buf_trans_select(display)) in hsw_ddi_pre_enable_dp()
2922 if ((port != PORT_A || DISPLAY_VER(display) >= 9) && in hsw_ddi_pre_enable_dp()
2939 struct intel_display *display = to_intel_display(encoder); in intel_ddi_pre_enable_dp() local
2941 if (HAS_DP20(display)) in intel_ddi_pre_enable_dp()
2948 if (DISPLAY_VER(display) >= 14) in intel_ddi_pre_enable_dp()
2950 else if (DISPLAY_VER(display) >= 12) in intel_ddi_pre_enable_dp()
2967 struct intel_display *display = to_intel_display(encoder); in intel_ddi_pre_enable_hdmi() local
2974 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); in intel_ddi_pre_enable_hdmi()
2975 dig_port->ddi_io_wakeref = intel_display_power_get(display, in intel_ddi_pre_enable_hdmi()
3010 struct intel_display *display = to_intel_display(state); in intel_ddi_pre_enable() local
3014 drm_WARN_ON(display->drm, crtc_state->has_pch_encoder); in intel_ddi_pre_enable()
3016 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); in intel_ddi_pre_enable()
3039 struct intel_display *display = to_intel_display(encoder); in mtl_ddi_disable_d2d() local
3044 if (DISPLAY_VER(display) < 14) in mtl_ddi_disable_d2d()
3047 if (DISPLAY_VER(display) >= 20) { in mtl_ddi_disable_d2d()
3052 reg = XELPDP_PORT_BUF_CTL1(display, port); in mtl_ddi_disable_d2d()
3057 intel_de_rmw(display, reg, clr_bits, 0); in mtl_ddi_disable_d2d()
3058 if (wait_for_us(!(intel_de_read(display, reg) & wait_bits), 100)) in mtl_ddi_disable_d2d()
3059 drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", in mtl_ddi_disable_d2d()
3065 struct intel_display *display = to_intel_display(encoder); in intel_ddi_buf_enable() local
3068 intel_de_write(display, DDI_BUF_CTL(port), buf_ctl | DDI_BUF_CTL_ENABLE); in intel_ddi_buf_enable()
3069 intel_de_posting_read(display, DDI_BUF_CTL(port)); in intel_ddi_buf_enable()
3077 struct intel_display *display = to_intel_display(encoder); in intel_ddi_buf_disable() local
3080 intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); in intel_ddi_buf_disable()
3082 if (DISPLAY_VER(display) >= 14) in intel_ddi_buf_disable()
3083 intel_wait_ddi_buf_idle(display, port); in intel_ddi_buf_disable()
3088 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), in intel_ddi_buf_disable()
3094 if (DISPLAY_VER(display) < 14) in intel_ddi_buf_disable()
3095 intel_wait_ddi_buf_idle(display, port); in intel_ddi_buf_disable()
3105 struct intel_display *display = to_intel_display(encoder); in intel_ddi_post_disable_dp() local
3122 if (DISPLAY_VER(display) >= 12) { in intel_ddi_post_disable_dp()
3126 intel_de_rmw(display, in intel_ddi_post_disable_dp()
3127 TRANS_DDI_FUNC_CTL(display, cpu_transcoder), in intel_ddi_post_disable_dp()
3147 if (DISPLAY_VER(display) >= 12) in intel_ddi_post_disable_dp()
3156 intel_display_power_put(display, in intel_ddi_post_disable_dp()
3163 if (DISPLAY_VER(display) >= 14) in intel_ddi_post_disable_dp()
3164 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), in intel_ddi_post_disable_dp()
3173 struct intel_display *display = to_intel_display(encoder); in intel_ddi_post_disable_hdmi() local
3181 if (DISPLAY_VER(display) < 12) in intel_ddi_post_disable_hdmi()
3186 if (DISPLAY_VER(display) >= 12) in intel_ddi_post_disable_hdmi()
3191 intel_display_power_put(display, in intel_ddi_post_disable_hdmi()
3205 struct intel_display *display = to_intel_display(encoder); in intel_ddi_post_disable_hdmi_or_sst() local
3211 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { in intel_ddi_post_disable_hdmi_or_sst()
3227 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder), in intel_ddi_post_disable_hdmi_or_sst()
3238 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { in intel_ddi_post_disable_hdmi_or_sst()
3244 if (DISPLAY_VER(display) >= 9) in intel_ddi_post_disable_hdmi_or_sst()
3346 struct intel_display *display = to_intel_display(encoder); in intel_ddi_enable_dp() local
3351 if (port == PORT_A && DISPLAY_VER(display) < 9) in intel_ddi_enable_dp()
3364 gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port) in gen9_chicken_trans_reg_by_port() argument
3374 drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9); in gen9_chicken_trans_reg_by_port()
3376 if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E)) in gen9_chicken_trans_reg_by_port()
3379 return CHICKEN_TRANS(display, trans[port]); in gen9_chicken_trans_reg_by_port()
3387 struct intel_display *display = to_intel_display(encoder); in intel_ddi_enable_hdmi() local
3396 drm_dbg_kms(display->drm, in intel_ddi_enable_hdmi()
3400 if (has_buf_trans_select(display)) in intel_ddi_enable_hdmi()
3408 /* Display WA #1143: skl,kbl,cfl */ in intel_ddi_enable_hdmi()
3409 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) { in intel_ddi_enable_hdmi()
3416 i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port); in intel_ddi_enable_hdmi()
3419 val = intel_de_read(display, reg); in intel_ddi_enable_hdmi()
3428 intel_de_write(display, reg, val); in intel_ddi_enable_hdmi()
3429 intel_de_posting_read(display, reg); in intel_ddi_enable_hdmi()
3440 intel_de_write(display, reg, val); in intel_ddi_enable_hdmi()
3461 if (DISPLAY_VER(display) >= 14) { in intel_ddi_enable_hdmi()
3469 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), in intel_ddi_enable_hdmi()
3474 if (DISPLAY_VER(display) >= 20) in intel_ddi_enable_hdmi()
3476 } else if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { in intel_ddi_enable_hdmi()
3477 drm_WARN_ON(display->drm, !intel_tc_port_in_legacy_mode(dig_port)); in intel_ddi_enable_hdmi()
3489 struct intel_display *display = to_intel_display(encoder); in intel_ddi_enable() local
3500 intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder), in intel_ddi_enable()
3502 intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder), in intel_ddi_enable()
3516 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0, in intel_ddi_enable()
3527 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state, i) { in intel_ddi_enable()
3570 struct intel_display *display = to_intel_display(encoder); in intel_ddi_disable_hdmi() local
3575 drm_dbg_kms(display->drm, in intel_ddi_disable_hdmi()
3639 struct intel_display *display = to_intel_display(encoder); in intel_ddi_update_active_dpll() local
3645 if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder)) in intel_ddi_update_active_dpll()
3648 for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, in intel_ddi_update_active_dpll()
3664 struct intel_display *display = to_intel_display(encoder); in intel_ddi_pre_pll_enable() local
3683 else if (display->platform.geminilake || display->platform.broxton) in intel_ddi_pre_pll_enable()
3690 struct intel_display *display = to_intel_display(encoder); in adlp_tbt_to_dp_alt_switch_wa() local
3695 intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln), in adlp_tbt_to_dp_alt_switch_wa()
3702 struct intel_display *display = to_intel_display(crtc_state); in mtl_ddi_prepare_link_retrain() local
3711 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); in mtl_ddi_prepare_link_retrain()
3713 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); in mtl_ddi_prepare_link_retrain()
3725 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); in mtl_ddi_prepare_link_retrain()
3726 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); in mtl_ddi_prepare_link_retrain()
3738 if (DISPLAY_VER(display) >= 20) in mtl_ddi_prepare_link_retrain()
3748 struct intel_display *display = to_intel_display(intel_dp); in intel_ddi_prepare_link_retrain() local
3753 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); in intel_ddi_prepare_link_retrain()
3755 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); in intel_ddi_prepare_link_retrain()
3766 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); in intel_ddi_prepare_link_retrain()
3767 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); in intel_ddi_prepare_link_retrain()
3769 if (display->platform.alderlake_p && in intel_ddi_prepare_link_retrain()
3781 struct intel_display *display = to_intel_display(intel_dp); in intel_ddi_set_link_train() local
3785 temp = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); in intel_ddi_set_link_train()
3806 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), temp); in intel_ddi_set_link_train()
3812 struct intel_display *display = to_intel_display(intel_dp); in intel_ddi_set_idle_link_train() local
3816 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), in intel_ddi_set_idle_link_train()
3826 if (port == PORT_A && DISPLAY_VER(display) < 12) in intel_ddi_set_idle_link_train()
3829 if (intel_de_wait_for_set(display, in intel_ddi_set_idle_link_train()
3832 drm_err(display->drm, in intel_ddi_set_idle_link_train()
3836 static bool intel_ddi_is_audio_enabled(struct intel_display *display, in intel_ddi_is_audio_enabled() argument
3842 if (!intel_display_power_is_enabled(display, POWER_DOMAIN_AUDIO_MMIO)) in intel_ddi_is_audio_enabled()
3845 return intel_de_read(display, HSW_AUD_PIN_ELD_CP_VLD) & in intel_ddi_is_audio_enabled()
3875 struct intel_display *display = to_intel_display(crtc_state); in intel_ddi_compute_min_voltage_level() local
3877 if (DISPLAY_VER(display) >= 14) in intel_ddi_compute_min_voltage_level()
3879 else if (DISPLAY_VER(display) >= 12) in intel_ddi_compute_min_voltage_level()
3881 else if (display->platform.jasperlake || display->platform.elkhartlake) in intel_ddi_compute_min_voltage_level()
3883 else if (DISPLAY_VER(display) >= 11) in intel_ddi_compute_min_voltage_level()
3887 static enum transcoder bdw_transcoder_master_readout(struct intel_display *display, in bdw_transcoder_master_readout() argument
3892 if (DISPLAY_VER(display) >= 11) { in bdw_transcoder_master_readout()
3893 u32 ctl2 = intel_de_read(display, in bdw_transcoder_master_readout()
3894 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder)); in bdw_transcoder_master_readout()
3901 u32 ctl = intel_de_read(display, in bdw_transcoder_master_readout()
3902 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); in bdw_transcoder_master_readout()
3918 struct intel_display *display = to_intel_display(crtc_state); in bdw_get_trans_port_sync_config() local
3924 bdw_transcoder_master_readout(display, crtc_state->cpu_transcoder); in bdw_get_trans_port_sync_config()
3926 for_each_cpu_transcoder_masked(display, cpu_transcoder, transcoders) { in bdw_get_trans_port_sync_config()
3931 trans_wakeref = intel_display_power_get_if_enabled(display, in bdw_get_trans_port_sync_config()
3937 if (bdw_transcoder_master_readout(display, cpu_transcoder) == in bdw_get_trans_port_sync_config()
3941 intel_display_power_put(display, power_domain, trans_wakeref); in bdw_get_trans_port_sync_config()
3944 drm_WARN_ON(display->drm, in bdw_get_trans_port_sync_config()
3953 struct intel_display *display = to_intel_display(encoder); in intel_ddi_read_func_ctl_dvi() local
3956 if (DISPLAY_VER(display) >= 14) in intel_ddi_read_func_ctl_dvi()
3987 struct intel_display *display = to_intel_display(encoder); in intel_ddi_read_func_ctl_fdi() local
3991 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & in intel_ddi_read_func_ctl_fdi()
3999 struct intel_display *display = to_intel_display(encoder); in intel_ddi_read_func_ctl_dp_sst() local
4011 if (DISPLAY_VER(display) >= 12 && in intel_ddi_read_func_ctl_dp_sst()
4020 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & in intel_ddi_read_func_ctl_dp_sst()
4023 if (DISPLAY_VER(display) >= 11) in intel_ddi_read_func_ctl_dp_sst()
4025 intel_de_read(display, in intel_ddi_read_func_ctl_dp_sst()
4040 struct intel_display *display = to_intel_display(encoder); in intel_ddi_read_func_ctl_dp_mst() local
4048 if (DISPLAY_VER(display) >= 12) in intel_ddi_read_func_ctl_dp_mst()
4054 if (DISPLAY_VER(display) >= 11) in intel_ddi_read_func_ctl_dp_mst()
4056 intel_de_read(display, in intel_ddi_read_func_ctl_dp_mst()
4066 struct intel_display *display = to_intel_display(encoder); in intel_ddi_read_func_ctl() local
4070 ddi_func_ctl = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); in intel_ddi_read_func_ctl()
4105 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { in intel_ddi_read_func_ctl()
4111 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { in intel_ddi_read_func_ctl()
4133 struct intel_display *display = to_intel_display(encoder); in intel_ddi_get_config() local
4137 if (drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder))) in intel_ddi_get_config()
4145 intel_ddi_is_audio_enabled(display, cpu_transcoder); in intel_ddi_get_config()
4152 if (display->platform.geminilake || display->platform.broxton) in intel_ddi_get_config()
4173 if (DISPLAY_VER(display) >= 8) in intel_ddi_get_config()
4189 struct intel_display *display = to_intel_display(encoder); in intel_ddi_get_clock() local
4194 if (drm_WARN_ON(display->drm, !pll)) in intel_ddi_get_clock()
4198 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); in intel_ddi_get_clock()
4199 drm_WARN_ON(display->drm, !pll_active); in intel_ddi_get_clock()
4203 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll, in intel_ddi_get_clock()
4266 struct intel_display *display = to_intel_display(encoder); in icl_ddi_tc_port_pll_type() local
4269 if (drm_WARN_ON(display->drm, !pll)) in icl_ddi_tc_port_pll_type()
4292 struct intel_display *display = to_intel_display(encoder); in icl_ddi_tc_get_clock() local
4297 if (drm_WARN_ON(display->drm, !pll)) in icl_ddi_tc_get_clock()
4308 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); in icl_ddi_tc_get_clock()
4309 drm_WARN_ON(display->drm, !pll_active); in icl_ddi_tc_get_clock()
4314 crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port); in icl_ddi_tc_get_clock()
4316 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll, in icl_ddi_tc_get_clock()
4363 struct intel_display *display = to_intel_display(encoder); in intel_ddi_initial_fastset_check() local
4367 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", in intel_ddi_initial_fastset_check()
4402 struct intel_display *display = to_intel_display(encoder); in intel_ddi_compute_config() local
4407 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) in intel_ddi_compute_config()
4422 if (display->platform.haswell && crtc->pipe == PIPE_A && in intel_ddi_compute_config()
4428 if (display->platform.geminilake || display->platform.broxton) in intel_ddi_compute_config()
4479 struct intel_display *display = to_intel_display(ref_crtc_state); in intel_ddi_port_sync_transcoders() local
4491 if (DISPLAY_VER(display) < 9) in intel_ddi_port_sync_transcoders()
4523 struct intel_display *display = to_intel_display(encoder); in intel_ddi_compute_config_late() local
4527 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", in intel_ddi_compute_config_late()
4555 struct intel_display *display = to_intel_display(encoder->dev); in intel_ddi_encoder_destroy() local
4561 intel_display_power_flush_work(display); in intel_ddi_encoder_destroy()
4599 struct intel_display *display = to_intel_display(dig_port); in intel_ddi_init_dp_connector() local
4608 if (DISPLAY_VER(display) >= 14) in intel_ddi_init_dp_connector()
4626 privacy_screen = drm_privacy_screen_get(display->drm->dev, NULL); in intel_ddi_init_dp_connector()
4631 drm_warn(display->drm, "Error getting privacy-screen\n"); in intel_ddi_init_dp_connector()
4641 struct intel_display *display = to_intel_display(encoder); in intel_hdmi_reset_link() local
4654 ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, in intel_hdmi_reset_link()
4671 drm_WARN_ON(display->drm, in intel_hdmi_reset_link()
4687 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", in intel_hdmi_reset_link()
4707 return intel_modeset_commit_pipes(display, BIT(crtc->pipe), ctx); in intel_hdmi_reset_link()
4712 struct intel_display *display = to_intel_display(encoder); in intel_ddi_link_check() local
4716 drm_WARN_ON(display->drm, !dig_port->dp.attached_connector); in intel_ddi_link_check()
4779 struct intel_display *display = to_intel_display(encoder); in lpt_digital_port_connected() local
4780 u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin]; in lpt_digital_port_connected()
4782 return intel_de_read(display, SDEISR) & bit; in lpt_digital_port_connected()
4787 struct intel_display *display = to_intel_display(encoder); in hsw_digital_port_connected() local
4788 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; in hsw_digital_port_connected()
4790 return intel_de_read(display, DEISR) & bit; in hsw_digital_port_connected()
4795 struct intel_display *display = to_intel_display(encoder); in bdw_digital_port_connected() local
4796 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; in bdw_digital_port_connected()
4798 return intel_de_read(display, GEN8_DE_PORT_ISR) & bit; in bdw_digital_port_connected()
4827 struct intel_display *display = to_intel_display(dig_port); in intel_ddi_a_force_4_lanes() local
4838 if (display->platform.geminilake || display->platform.broxton) in intel_ddi_a_force_4_lanes()
4847 struct intel_display *display = to_intel_display(dig_port); in intel_ddi_max_lanes() local
4851 if (DISPLAY_VER(display) >= 11) in intel_ddi_max_lanes()
4855 if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) in intel_ddi_max_lanes()
4868 drm_dbg_kms(display->drm, in intel_ddi_max_lanes()
4877 static enum hpd_pin xelpd_hpd_pin(struct intel_display *display, enum port port) in xelpd_hpd_pin() argument
4887 static enum hpd_pin dg1_hpd_pin(struct intel_display *display, enum port port) in dg1_hpd_pin() argument
4895 static enum hpd_pin tgl_hpd_pin(struct intel_display *display, enum port port) in tgl_hpd_pin() argument
4903 static enum hpd_pin rkl_hpd_pin(struct intel_display *display, enum port port) in rkl_hpd_pin() argument
4905 if (HAS_PCH_TGP(display)) in rkl_hpd_pin()
4906 return tgl_hpd_pin(display, port); in rkl_hpd_pin()
4914 static enum hpd_pin icl_hpd_pin(struct intel_display *display, enum port port) in icl_hpd_pin() argument
4922 static enum hpd_pin ehl_hpd_pin(struct intel_display *display, enum port port) in ehl_hpd_pin() argument
4927 if (HAS_PCH_TGP(display)) in ehl_hpd_pin()
4928 return icl_hpd_pin(display, port); in ehl_hpd_pin()
4933 static enum hpd_pin skl_hpd_pin(struct intel_display *display, enum port port) in skl_hpd_pin() argument
4935 if (HAS_PCH_TGP(display)) in skl_hpd_pin()
4936 return icl_hpd_pin(display, port); in skl_hpd_pin()
4941 static bool intel_ddi_is_tc(struct intel_display *display, enum port port) in intel_ddi_is_tc() argument
4943 if (DISPLAY_VER(display) >= 12) in intel_ddi_is_tc()
4945 else if (DISPLAY_VER(display) >= 11) in intel_ddi_is_tc()
4988 static bool port_strap_detected(struct intel_display *display, enum port port) in port_strap_detected() argument
4991 if (DISPLAY_VER(display) >= 9) in port_strap_detected()
4996 return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; in port_strap_detected()
4998 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; in port_strap_detected()
5000 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; in port_strap_detected()
5002 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; in port_strap_detected()
5016 static bool assert_has_icl_dsi(struct intel_display *display) in assert_has_icl_dsi() argument
5018 return !drm_WARN(display->drm, !display->platform.alderlake_p && in assert_has_icl_dsi()
5019 !display->platform.tigerlake && DISPLAY_VER(display) != 11, in assert_has_icl_dsi()
5023 static bool port_in_use(struct intel_display *display, enum port port) in port_in_use() argument
5027 for_each_intel_encoder(display->drm, encoder) { in port_in_use()
5036 void intel_ddi_init(struct intel_display *display, in intel_ddi_init() argument
5050 if (!port_strap_detected(display, port)) { in intel_ddi_init()
5051 drm_dbg_kms(display->drm, in intel_ddi_init()
5056 if (!assert_port_valid(display, port)) in intel_ddi_init()
5059 if (port_in_use(display, port)) { in intel_ddi_init()
5060 drm_dbg_kms(display->drm, in intel_ddi_init()
5067 if (!assert_has_icl_dsi(display)) in intel_ddi_init()
5070 icl_dsi_init(display, devdata); in intel_ddi_init()
5074 phy = intel_port_to_phy(display, port); in intel_ddi_init()
5082 if (intel_hti_uses_phy(display, phy)) { in intel_ddi_init()
5083 drm_dbg_kms(display->drm, "PORT %c / PHY %c reserved by HTI\n", in intel_ddi_init()
5100 drm_dbg_kms(display->drm, "VBT says port %c has lspcon\n", in intel_ddi_init()
5105 drm_dbg_kms(display->drm, in intel_ddi_init()
5111 if (intel_phy_is_snps(display, phy) && in intel_ddi_init()
5112 display->snps.phy_failed_calibration & BIT(phy)) { in intel_ddi_init()
5113 drm_dbg_kms(display->drm, in intel_ddi_init()
5127 if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) { in intel_ddi_init()
5128 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, in intel_ddi_init()
5133 } else if (DISPLAY_VER(display) >= 12) { in intel_ddi_init()
5134 enum tc_port tc_port = intel_port_to_tc(display, port); in intel_ddi_init()
5136 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, in intel_ddi_init()
5143 } else if (DISPLAY_VER(display) >= 11) { in intel_ddi_init()
5144 enum tc_port tc_port = intel_port_to_tc(display, port); in intel_ddi_init()
5146 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, in intel_ddi_init()
5154 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, in intel_ddi_init()
5185 encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port); in intel_ddi_init()
5190 if (DISPLAY_VER(display) >= 14) { in intel_ddi_init()
5195 } else if (display->platform.dg2) { in intel_ddi_init()
5199 } else if (display->platform.alderlake_s) { in intel_ddi_init()
5204 } else if (display->platform.rocketlake) { in intel_ddi_init()
5209 } else if (display->platform.dg1) { in intel_ddi_init()
5214 } else if (display->platform.jasperlake || display->platform.elkhartlake) { in intel_ddi_init()
5215 if (intel_ddi_is_tc(display, port)) { in intel_ddi_init()
5227 } else if (DISPLAY_VER(display) >= 11) { in intel_ddi_init()
5228 if (intel_ddi_is_tc(display, port)) { in intel_ddi_init()
5240 } else if (display->platform.geminilake || display->platform.broxton) { in intel_ddi_init()
5243 } else if (DISPLAY_VER(display) == 9) { in intel_ddi_init()
5248 } else if (display->platform.broadwell || display->platform.haswell) { in intel_ddi_init()
5255 if (DISPLAY_VER(display) >= 14) { in intel_ddi_init()
5257 } else if (display->platform.dg2) { in intel_ddi_init()
5259 } else if (DISPLAY_VER(display) >= 12) { in intel_ddi_init()
5264 } else if (DISPLAY_VER(display) >= 11) { in intel_ddi_init()
5269 } else if (display->platform.geminilake || display->platform.broxton) { in intel_ddi_init()
5277 if (DISPLAY_VER(display) >= 13) in intel_ddi_init()
5278 encoder->hpd_pin = xelpd_hpd_pin(display, port); in intel_ddi_init()
5279 else if (display->platform.dg1) in intel_ddi_init()
5280 encoder->hpd_pin = dg1_hpd_pin(display, port); in intel_ddi_init()
5281 else if (display->platform.rocketlake) in intel_ddi_init()
5282 encoder->hpd_pin = rkl_hpd_pin(display, port); in intel_ddi_init()
5283 else if (DISPLAY_VER(display) >= 12) in intel_ddi_init()
5284 encoder->hpd_pin = tgl_hpd_pin(display, port); in intel_ddi_init()
5285 else if (display->platform.jasperlake || display->platform.elkhartlake) in intel_ddi_init()
5286 encoder->hpd_pin = ehl_hpd_pin(display, port); in intel_ddi_init()
5287 else if (DISPLAY_VER(display) == 11) in intel_ddi_init()
5288 encoder->hpd_pin = icl_hpd_pin(display, port); in intel_ddi_init()
5289 else if (DISPLAY_VER(display) == 9 && !display->platform.broxton) in intel_ddi_init()
5290 encoder->hpd_pin = skl_hpd_pin(display, port); in intel_ddi_init()
5294 ddi_buf_ctl = intel_de_read(display, DDI_BUF_CTL(port)); in intel_ddi_init()
5299 dig_port->ddi_a_4_lanes = DISPLAY_VER(display) < 11 && ddi_buf_ctl & DDI_A_4_LANES; in intel_ddi_init()
5318 drm_dbg_kms(display->drm, in intel_ddi_init()
5335 drm_WARN_ON(display->drm, port > PORT_I); in intel_ddi_init()
5336 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(display, port); in intel_ddi_init()
5338 if (DISPLAY_VER(display) >= 11) { in intel_ddi_init()
5343 } else if (display->platform.geminilake || display->platform.broxton) { in intel_ddi_init()
5345 } else if (DISPLAY_VER(display) == 9) { in intel_ddi_init()
5347 } else if (display->platform.broadwell) { in intel_ddi_init()
5352 } else if (display->platform.haswell) { in intel_ddi_init()
5368 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(display); in intel_ddi_init()