86 	struct intel_display *display = to_intel_display(plane_state);  in intel_cursor_check_surface()  local
108 		drm_dbg_kms(display->drm,  in intel_cursor_check_surface()
122 	if (HAS_GMCH(display) && rotation & DRM_MODE_ROTATE_180) {  in intel_cursor_check_surface()
140 	struct intel_display *display = to_intel_display(plane_state);  in intel_check_cursor()  local
148 		drm_dbg_kms(display->drm, "[PLANE:%d:%s] cursor cannot be tiled\n",  in intel_check_cursor()
229 	struct intel_display *display = to_intel_display(plane_state);  in i845_check_cursor()  local
244 		drm_dbg_kms(display->drm,  in i845_check_cursor()
252 	drm_WARN_ON(display->drm, plane_state->uapi.visible &&  in i845_check_cursor()
262 		 drm_dbg_kms(display->drm, "[PLANE:%d:%s] invalid cursor stride (%u)\n",  in i845_check_cursor()
279 	struct intel_display *display = to_intel_display(plane);  in i845_cursor_update_arm()  local
301 		intel_de_write_fw(display, CURCNTR(display, PIPE_A), 0);  in i845_cursor_update_arm()
302 		intel_de_write_fw(display, CURBASE(display, PIPE_A), base);  in i845_cursor_update_arm()
303 		intel_de_write_fw(display, CURSIZE(display, PIPE_A), size);  in i845_cursor_update_arm()
304 		intel_de_write_fw(display, CURPOS(display, PIPE_A), pos);  in i845_cursor_update_arm()
305 		intel_de_write_fw(display, CURCNTR(display, PIPE_A), cntl);  in i845_cursor_update_arm()
311 		intel_de_write_fw(display, CURPOS(display, PIPE_A), pos);  in i845_cursor_update_arm()
325 	struct intel_display *display = to_intel_display(plane);  in i845_cursor_get_hw_state()  local
331 	wakeref = intel_display_power_get_if_enabled(display, power_domain);  in i845_cursor_get_hw_state()
335 	ret = intel_de_read(display, CURCNTR(display, PIPE_A)) & CURSOR_ENABLE;  in i845_cursor_get_hw_state()
339 	intel_display_power_put(display, power_domain, wakeref);  in i845_cursor_get_hw_state()
371 	struct intel_display *display = to_intel_display(plane);  in i9xx_cursor_min_alignment()  local
373 	if (intel_scanout_needs_vtd_wa(display))  in i9xx_cursor_min_alignment()
381 	struct intel_display *display = to_intel_display(crtc_state);  in i9xx_cursor_ctl_crtc()  local
385 	if (DISPLAY_VER(display) >= 11)  in i9xx_cursor_ctl_crtc()
394 	if (DISPLAY_VER(display) < 5 && !display->platform.g4x)  in i9xx_cursor_ctl_crtc()
402 	struct intel_display *display = to_intel_display(plane_state);  in i9xx_cursor_ctl()  local
405 	if (display->platform.sandybridge || display->platform.ivybridge)  in i9xx_cursor_ctl()
427 	if (intel_display_wa(display, INTEL_DISPLAY_WA_22012358565))  in i9xx_cursor_ctl()
435 	struct intel_display *display = to_intel_display(plane_state);  in i9xx_cursor_size_ok()  local
458 	if (HAS_CUR_FBC(display) &&  in i9xx_cursor_size_ok()
473 	struct intel_display *display = to_intel_display(plane_state);  in i9xx_check_cursor()  local
489 		drm_dbg_kms(display->drm,  in i9xx_check_cursor()
497 	drm_WARN_ON(display->drm, plane_state->uapi.visible &&  in i9xx_check_cursor()
502 		drm_dbg_kms(display->drm,  in i9xx_check_cursor()
516 	 * display power well must be turned off and on again.  in i9xx_check_cursor()
519 	if (display->platform.cherryview && pipe == PIPE_C &&  in i9xx_check_cursor()
521 		drm_dbg_kms(display->drm,  in i9xx_check_cursor()
536 	struct intel_display *display = to_intel_display(plane);  in i9xx_cursor_disable_sel_fetch_arm()  local
543 	intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), 0);  in i9xx_cursor_disable_sel_fetch_arm()
551 	struct intel_display *display = to_intel_display(plane);  in wa_16021440873()  local
559 	intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), ctl);  in wa_16021440873()
561 	intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(display, pipe),  in wa_16021440873()
570 	struct intel_display *display = to_intel_display(plane);  in i9xx_cursor_update_sel_fetch_arm()  local
583 			intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(display, pipe), val);  in i9xx_cursor_update_sel_fetch_arm()
586 		intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), plane_state->ctl);  in i9xx_cursor_update_sel_fetch_arm()
623 	struct intel_display *display = to_intel_display(plane->base.dev);  in skl_write_cursor_wm()  local
631 	for (level = 0; level < display->wm.num_levels; level++)  in skl_write_cursor_wm()
632 		intel_de_write_dsb(display, dsb, CUR_WM(pipe, level),  in skl_write_cursor_wm()
635 	intel_de_write_dsb(display, dsb, CUR_WM_TRANS(pipe),  in skl_write_cursor_wm()
638 	if (HAS_HW_SAGV_WM(display)) {  in skl_write_cursor_wm()
641 		intel_de_write_dsb(display, dsb, CUR_WM_SAGV(pipe),  in skl_write_cursor_wm()
643 		intel_de_write_dsb(display, dsb, CUR_WM_SAGV_TRANS(pipe),  in skl_write_cursor_wm()
647 	intel_de_write_dsb(display, dsb, CUR_BUF_CFG(pipe),  in skl_write_cursor_wm()
657 	struct intel_display *display = to_intel_display(plane);  in i9xx_cursor_update_arm()  local
668 		if (DISPLAY_VER(display) < 14 && width != height)  in i9xx_cursor_update_arm()
695 	if (DISPLAY_VER(display) >= 9)  in i9xx_cursor_update_arm()
706 		if (HAS_CUR_FBC(display))  in i9xx_cursor_update_arm()
707 			intel_de_write_dsb(display, dsb, CUR_FBC_CTL(display, pipe), fbc_ctl);  in i9xx_cursor_update_arm()
708 		intel_de_write_dsb(display, dsb, CURCNTR(display, pipe), cntl);  in i9xx_cursor_update_arm()
709 		intel_de_write_dsb(display, dsb, CURPOS(display, pipe), pos);  in i9xx_cursor_update_arm()
710 		intel_de_write_dsb(display, dsb, CURBASE(display, pipe), base);  in i9xx_cursor_update_arm()
716 		intel_de_write_dsb(display, dsb, CURPOS(display, pipe), pos);  in i9xx_cursor_update_arm()
717 		intel_de_write_dsb(display, dsb, CURBASE(display, pipe), base);  in i9xx_cursor_update_arm()
731 	struct intel_display *display = to_intel_display(plane);  in i9xx_cursor_get_hw_state()  local
740 	 * display power wells.  in i9xx_cursor_get_hw_state()
743 	wakeref = intel_display_power_get_if_enabled(display, power_domain);  in i9xx_cursor_get_hw_state()
747 	val = intel_de_read(display, CURCNTR(display, plane->pipe));  in i9xx_cursor_get_hw_state()
751 	if (DISPLAY_VER(display) >= 5 || display->platform.g4x)  in i9xx_cursor_get_hw_state()
756 	intel_display_power_put(display, power_domain, wakeref);  in i9xx_cursor_get_hw_state()
765 	struct intel_display *display = to_intel_display(plane);  in g4x_cursor_capture_error()  local
767 	error->ctl = intel_de_read(display, CURCNTR(display, crtc->pipe));  in g4x_cursor_capture_error()
768 	error->surf = intel_de_read(display, CURBASE(display, crtc->pipe));  in g4x_cursor_capture_error()
769 	error->surflive = intel_de_read(display, CURSURFLIVE(display, crtc->pipe));  in g4x_cursor_capture_error()
776 	struct intel_display *display = to_intel_display(plane);  in i9xx_cursor_capture_error()  local
778 	error->ctl = intel_de_read(display, CURCNTR(display, crtc->pipe));  in i9xx_cursor_capture_error()
779 	error->surf = intel_de_read(display, CURBASE(display, crtc->pipe));  in i9xx_cursor_capture_error()
814 	struct intel_display *display = to_intel_display(plane);  in intel_legacy_cursor_update()  local
918 	if (!drm_WARN_ON(display->drm, drm_crtc_vblank_get(&crtc->base))) {  in intel_legacy_cursor_update()
985 	struct intel_display *display = to_intel_display(plane);  in intel_cursor_add_size_hints_property()  local
986 	const struct drm_mode_config *config = &display->drm->mode_config;  in intel_cursor_add_size_hints_property()
994 		if (drm_WARN_ON(display->drm, num_hints >= ARRAY_SIZE(hints)))  in intel_cursor_add_size_hints_property()
1006 intel_cursor_plane_create(struct intel_display *display,  in intel_cursor_plane_create()  argument
1022 	if (display->platform.i845g || display->platform.i865g) {  in intel_cursor_plane_create()
1032 		if (display->platform.i830)  in intel_cursor_plane_create()
1034 		else if (display->platform.i85x)  in intel_cursor_plane_create()
1039 		if (intel_scanout_needs_vtd_wa(display))  in intel_cursor_plane_create()
1050 	if (DISPLAY_VER(display) >= 5 || display->platform.g4x)  in intel_cursor_plane_create()
1058 	if (display->platform.i845g || display->platform.i865g || HAS_CUR_FBC(display))  in intel_cursor_plane_create()
1061 	modifiers = intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_NONE);  in intel_cursor_plane_create()
1063 	ret = drm_universal_plane_init(display->drm, &cursor->base,  in intel_cursor_plane_create()
1076 	if (DISPLAY_VER(display) >= 4)  in intel_cursor_plane_create()
1087 	zpos = DISPLAY_RUNTIME_INFO(display)->num_sprites[pipe] + 1;  in intel_cursor_plane_create()
1090 	if (DISPLAY_VER(display) >= 12)  in intel_cursor_plane_create()
1103 void intel_cursor_mode_config_init(struct intel_display *display)  in intel_cursor_mode_config_init()  argument
1105 	struct drm_mode_config *mode_config = &display->drm->mode_config;  in intel_cursor_mode_config_init()
1107 	if (display->platform.i845g) {  in intel_cursor_mode_config_init()
1110 	} else if (display->platform.i865g) {  in intel_cursor_mode_config_init()
1113 	} else if (display->platform.i830 || display->platform.i85x ||  in intel_cursor_mode_config_init()
1114 		   display->platform.i915g || display->platform.i915gm) {  in intel_cursor_mode_config_init()