Lines Matching defs:phy
56 icl_get_procmon_ref_values(struct intel_display *display, enum phy phy)
60 val = intel_de_read(display, ICL_PORT_COMP_DW3(phy));
79 enum phy phy)
83 procmon = icl_get_procmon_ref_values(display, phy);
85 intel_de_rmw(display, ICL_PORT_COMP_DW1(phy),
88 intel_de_write(display, ICL_PORT_COMP_DW9(phy), procmon->dw9);
89 intel_de_write(display, ICL_PORT_COMP_DW10(phy), procmon->dw10);
93 enum phy phy, i915_reg_t reg, u32 mask,
102 phy_name(phy),
111 enum phy phy)
116 procmon = icl_get_procmon_ref_values(display, phy);
118 ret = check_phy_reg(display, phy, ICL_PORT_COMP_DW1(phy),
120 ret &= check_phy_reg(display, phy, ICL_PORT_COMP_DW9(phy),
122 ret &= check_phy_reg(display, phy, ICL_PORT_COMP_DW10(phy),
128 static bool has_phy_misc(struct intel_display *display, enum phy phy)
140 return phy == PHY_A;
144 return phy < PHY_C;
150 enum phy phy)
153 if (!has_phy_misc(display, phy))
154 return intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT;
156 return !(intel_de_read(display, ICL_PHY_MISC(phy)) &
158 (intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT);
188 static bool phy_is_master(struct intel_display *display, enum phy phy)
206 if (phy == PHY_A)
209 return phy == PHY_D;
211 return phy == PHY_C;
217 enum phy phy)
222 if (!icl_combo_phy_enabled(display, phy))
226 ret &= check_phy_reg(display, phy, ICL_PORT_TX_DW8_LN(0, phy),
232 ret &= check_phy_reg(display, phy, ICL_PORT_PCS_DW1_LN(0, phy),
236 ret &= icl_verify_procmon_ref_values(display, phy);
238 if (phy_is_master(display, phy)) {
239 ret &= check_phy_reg(display, phy, ICL_PORT_COMP_DW8(phy),
246 ret &= check_phy_reg(display, phy, ICL_PHY_MISC(phy),
252 ret &= check_phy_reg(display, phy, ICL_PORT_CL_DW5(phy),
259 enum phy phy, bool is_dsi,
303 intel_de_rmw(display, ICL_PORT_CL_DW10(phy),
309 enum phy phy;
311 for_each_combo_phy(display, phy) {
315 if (icl_combo_phy_verify_state(display, phy))
318 procmon = icl_get_procmon_ref_values(display, phy);
322 phy_name(phy), procmon->name);
324 if (!has_phy_misc(display, phy))
335 val = intel_de_read(display, ICL_PHY_MISC(phy));
337 phy == PHY_A) {
345 intel_de_write(display, ICL_PHY_MISC(phy), val);
349 val = intel_de_read(display, ICL_PORT_TX_DW8_LN(0, phy));
353 intel_de_write(display, ICL_PORT_TX_DW8_GRP(phy), val);
355 val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));
358 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val);
361 icl_set_procmon_ref_values(display, phy);
363 if (phy_is_master(display, phy))
364 intel_de_rmw(display, ICL_PORT_COMP_DW8(phy),
367 intel_de_rmw(display, ICL_PORT_COMP_DW0(phy), 0, COMP_INIT);
368 intel_de_rmw(display, ICL_PORT_CL_DW5(phy),
375 enum phy phy;
377 for_each_combo_phy_reverse(display, phy) {
378 if (phy == PHY_A &&
379 !icl_combo_phy_verify_state(display, phy)) {
388 phy_name(phy));
392 phy_name(phy));
396 if (!has_phy_misc(display, phy))
399 intel_de_rmw(display, ICL_PHY_MISC(phy), 0,
403 intel_de_rmw(display, ICL_PORT_COMP_DW0(phy), COMP_INIT, 0);