Lines Matching refs:vco
89 * cdclk = vco / cd2x_div / (sq_len / sq_div) / 2
91 * , where vco is the frequency generated by the PLL; cd2x_div
318 unsigned int vco;
338 vco = vco_table[tmp & 0x7];
339 if (vco == 0)
343 drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco);
345 return vco;
360 cdclk_config->vco = intel_hpll_vco(display);
369 switch (cdclk_config->vco) {
386 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
393 cdclk_config->vco, tmp);
442 cdclk_config->vco = intel_hpll_vco(display);
451 switch (cdclk_config->vco) {
465 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
472 cdclk_config->vco, tmp);
483 cdclk_config->vco = intel_hpll_vco(display);
489 switch (cdclk_config->vco) {
501 cdclk_config->vco, tmp);
576 cdclk_config->vco = vlv_get_hpll_vco(dev_priv);
579 cdclk_config->vco);
896 static int skl_calc_cdclk(int min_cdclk, int vco)
898 if (vco == 8640000) {
937 cdclk_config->vco = 0;
960 cdclk_config->vco = 8100000;
964 cdclk_config->vco = 8640000;
981 if (cdclk_config->vco == 0)
986 if (cdclk_config->vco == 8640000) {
1039 static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco)
1041 bool changed = display->cdclk.skl_preferred_vco_freq != vco;
1043 display->cdclk.skl_preferred_vco_freq = vco;
1049 static u32 skl_dpll0_link_rate(struct intel_display *display, int vco)
1051 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);
1060 * works with vco.
1062 if (vco == 8640000)
1068 static void skl_dpll0_enable(struct intel_display *display, int vco)
1075 skl_dpll0_link_rate(display, vco));
1084 display->cdclk.hw.vco = vco;
1086 /* We'll want to keep using the current vco from now on. */
1087 skl_set_preferred_cdclk_vco(display, vco);
1098 display->cdclk.hw.vco = 0;
1102 int cdclk, int vco)
1108 drm_WARN_ON(display->drm, vco != 0);
1130 int vco = cdclk_config->vco;
1143 display->platform.skylake && vco == 8640000);
1155 freq_select = skl_cdclk_freq_sel(display, cdclk, vco);
1157 if (display->cdclk.hw.vco != 0 &&
1158 display->cdclk.hw.vco != vco)
1163 if (display->cdclk.hw.vco != vco) {
1175 if (display->cdclk.hw.vco != vco)
1176 skl_dpll0_enable(display, vco);
1213 if (display->cdclk.hw.vco == 0 ||
1236 display->cdclk.hw.vco = ~0;
1246 display->cdclk.hw.vco != 0) {
1248 * Use the current vco as our initial
1249 * guess as to what the preferred vco is.
1253 display->cdclk.hw.vco);
1259 cdclk_config.vco = display->cdclk.skl_preferred_vco_freq;
1260 if (cdclk_config.vco == 0)
1261 cdclk_config.vco = 8100000;
1262 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
1273 cdclk_config.vco = 0;
1510 static int cdclk_divider(int cdclk, int vco, u16 waveform)
1513 return DIV_ROUND_CLOSEST(vco * cdclk_squash_divider(waveform),
1679 cdclk_config->vco = 0;
1692 cdclk_config->vco = ratio * cdclk_config->ref;
1711 if (cdclk_config->vco == 0) {
1747 cdclk_config->vco, size * div);
1749 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
1772 display->cdclk.hw.vco = 0;
1775 static void bxt_de_pll_enable(struct intel_display *display, int vco)
1777 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1789 display->cdclk.hw.vco = vco;
1801 display->cdclk.hw.vco = 0;
1804 static void icl_cdclk_pll_enable(struct intel_display *display, int vco)
1806 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1819 display->cdclk.hw.vco = vco;
1822 static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco)
1824 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1843 display->cdclk.hw.vco = vco;
1867 int cdclk, int vco, u16 waveform)
1869 /* cdclk = vco / 2 / div{1,1.5,2,4} */
1870 switch (cdclk_divider(cdclk, vco, waveform)) {
1874 drm_WARN_ON(display->drm, vco != 0);
1907 static void icl_cdclk_pll_update(struct intel_display *display, int vco)
1909 if (display->cdclk.hw.vco != 0 &&
1910 display->cdclk.hw.vco != vco)
1913 if (display->cdclk.hw.vco != vco)
1914 icl_cdclk_pll_enable(display, vco);
1917 static void bxt_cdclk_pll_update(struct intel_display *display, int vco)
1919 if (display->cdclk.hw.vco != 0 &&
1920 display->cdclk.hw.vco != vco)
1923 if (display->cdclk.hw.vco != vco)
1924 bxt_de_pll_enable(display, vco);
1939 static bool cdclk_pll_is_unknown(unsigned int vco)
1943 * case when the vco is set to ~0 in the
1946 return vco == ~0;
1966 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk);
1989 if (cdclk_pll_is_unknown(old_cdclk_config->vco))
2000 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 ||
2001 old_cdclk_config->vco == new_cdclk_config->vco ||
2006 old_cdclk_config->vco, old_waveform);
2008 new_cdclk_config->vco, new_waveform);
2024 * The mid cdclk config should have the new vco.
2028 mid_cdclk_config->vco = old_cdclk_config->vco;
2032 mid_cdclk_config->vco = new_cdclk_config->vco;
2038 mid_cdclk_config->vco,
2058 display->cdclk.hw.vco > 0;
2066 int vco = cdclk_config->vco;
2072 val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) |
2096 int vco = cdclk_config->vco;
2098 if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 &&
2099 !cdclk_pll_is_unknown(display->cdclk.hw.vco)) {
2100 if (display->cdclk.hw.vco != vco)
2101 adlp_cdclk_pll_crawl(display, vco);
2107 icl_cdclk_pll_update(display, vco);
2109 bxt_cdclk_pll_update(display, vco);
2216 int cdclk, vco;
2221 if (display->cdclk.hw.vco == 0 ||
2231 vco = bxt_calc_cdclk_pll_vco(display, cdclk);
2232 if (vco != display->cdclk.hw.vco)
2262 display->cdclk.hw.vco = ~0;
2272 display->cdclk.hw.vco != 0)
2283 cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk);
2295 cdclk_config.vco = 0;
2341 drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco));
2343 if (a->vco == 0 || b->vco == 0)
2352 return a->vco != b->vco &&
2366 * The vco and cd2x divider will change independently
2369 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
2370 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
2372 return a->vco != 0 && b->vco != 0 &&
2373 a->vco != b->vco &&
2392 a->vco != 0 &&
2393 a->vco == b->vco &&
2410 a->vco != b->vco ||
2443 a->vco != 0 &&
2444 a->vco == b->vco &&
2468 context, cdclk_config->cdclk, cdclk_config->vco,
2992 int vco, i;
2994 vco = cdclk_state->logical.vco;
2995 if (!vco)
2996 vco = display->cdclk.skl_preferred_vco_freq;
3012 vco = 8640000;
3015 vco = 8100000;
3020 return vco;
3027 int min_cdclk, cdclk, vco;
3033 vco = skl_dpll0_vco(state);
3035 cdclk = skl_calc_cdclk(min_cdclk, vco);
3037 cdclk_state->logical.vco = vco;
3043 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco);
3045 cdclk_state->actual.vco = vco;
3061 int min_cdclk, min_voltage_level, cdclk, vco;
3072 vco = bxt_calc_cdclk_pll_vco(display, cdclk);
3074 cdclk_state->logical.vco = vco;
3082 vco = bxt_calc_cdclk_pll_vco(display, cdclk);
3084 cdclk_state->actual.vco = vco;
3409 int max_cdclk, vco;
3411 vco = display->cdclk.skl_preferred_vco_freq;
3412 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);
3415 * Use the lower (vco 8640) cdclk values as a
3417 * if the preferred vco is 8100 instead.
3428 display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);