Lines Matching refs:cdclk_config
117 struct intel_cdclk_config *cdclk_config);
119 const struct intel_cdclk_config *cdclk_config,
126 struct intel_cdclk_config *cdclk_config) in intel_cdclk_get_cdclk() argument
128 display->funcs.cdclk->get_cdclk(display, cdclk_config); in intel_cdclk_get_cdclk()
132 const struct intel_cdclk_config *cdclk_config, in intel_cdclk_set_cdclk() argument
135 display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe); in intel_cdclk_set_cdclk()
152 struct intel_cdclk_config *cdclk_config) in fixed_133mhz_get_cdclk() argument
154 cdclk_config->cdclk = 133333; in fixed_133mhz_get_cdclk()
158 struct intel_cdclk_config *cdclk_config) in fixed_200mhz_get_cdclk() argument
160 cdclk_config->cdclk = 200000; in fixed_200mhz_get_cdclk()
164 struct intel_cdclk_config *cdclk_config) in fixed_266mhz_get_cdclk() argument
166 cdclk_config->cdclk = 266667; in fixed_266mhz_get_cdclk()
170 struct intel_cdclk_config *cdclk_config) in fixed_333mhz_get_cdclk() argument
172 cdclk_config->cdclk = 333333; in fixed_333mhz_get_cdclk()
176 struct intel_cdclk_config *cdclk_config) in fixed_400mhz_get_cdclk() argument
178 cdclk_config->cdclk = 400000; in fixed_400mhz_get_cdclk()
182 struct intel_cdclk_config *cdclk_config) in fixed_450mhz_get_cdclk() argument
184 cdclk_config->cdclk = 450000; in fixed_450mhz_get_cdclk()
188 struct intel_cdclk_config *cdclk_config) in i85x_get_cdclk() argument
199 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
213 cdclk_config->cdclk = 200000; in i85x_get_cdclk()
216 cdclk_config->cdclk = 250000; in i85x_get_cdclk()
219 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
224 cdclk_config->cdclk = 266667; in i85x_get_cdclk()
230 struct intel_cdclk_config *cdclk_config) in i915gm_get_cdclk() argument
238 cdclk_config->cdclk = 133333; in i915gm_get_cdclk()
244 cdclk_config->cdclk = 333333; in i915gm_get_cdclk()
248 cdclk_config->cdclk = 190000; in i915gm_get_cdclk()
254 struct intel_cdclk_config *cdclk_config) in i945gm_get_cdclk() argument
262 cdclk_config->cdclk = 133333; in i945gm_get_cdclk()
268 cdclk_config->cdclk = 320000; in i945gm_get_cdclk()
272 cdclk_config->cdclk = 200000; in i945gm_get_cdclk()
349 struct intel_cdclk_config *cdclk_config) in g33_get_cdclk() argument
360 cdclk_config->vco = intel_hpll_vco(display); in g33_get_cdclk()
369 switch (cdclk_config->vco) { in g33_get_cdclk()
386 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in g33_get_cdclk()
393 cdclk_config->vco, tmp); in g33_get_cdclk()
394 cdclk_config->cdclk = 190476; in g33_get_cdclk()
398 struct intel_cdclk_config *cdclk_config) in pnv_get_cdclk() argument
407 cdclk_config->cdclk = 266667; in pnv_get_cdclk()
410 cdclk_config->cdclk = 333333; in pnv_get_cdclk()
413 cdclk_config->cdclk = 444444; in pnv_get_cdclk()
416 cdclk_config->cdclk = 200000; in pnv_get_cdclk()
423 cdclk_config->cdclk = 133333; in pnv_get_cdclk()
426 cdclk_config->cdclk = 166667; in pnv_get_cdclk()
432 struct intel_cdclk_config *cdclk_config) in i965gm_get_cdclk() argument
442 cdclk_config->vco = intel_hpll_vco(display); in i965gm_get_cdclk()
451 switch (cdclk_config->vco) { in i965gm_get_cdclk()
465 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in i965gm_get_cdclk()
472 cdclk_config->vco, tmp); in i965gm_get_cdclk()
473 cdclk_config->cdclk = 200000; in i965gm_get_cdclk()
477 struct intel_cdclk_config *cdclk_config) in gm45_get_cdclk() argument
483 cdclk_config->vco = intel_hpll_vco(display); in gm45_get_cdclk()
489 switch (cdclk_config->vco) { in gm45_get_cdclk()
493 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; in gm45_get_cdclk()
496 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; in gm45_get_cdclk()
501 cdclk_config->vco, tmp); in gm45_get_cdclk()
502 cdclk_config->cdclk = 222222; in gm45_get_cdclk()
508 struct intel_cdclk_config *cdclk_config) in hsw_get_cdclk() argument
515 cdclk_config->cdclk = 800000; in hsw_get_cdclk()
517 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
519 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
521 cdclk_config->cdclk = 337500; in hsw_get_cdclk()
523 cdclk_config->cdclk = 540000; in hsw_get_cdclk()
569 struct intel_cdclk_config *cdclk_config) in vlv_get_cdclk() argument
577 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); in vlv_get_cdclk()
578 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", in vlv_get_cdclk()
580 cdclk_config->vco); in vlv_get_cdclk()
588 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> in vlv_get_cdclk()
591 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> in vlv_get_cdclk()
634 const struct intel_cdclk_config *cdclk_config, in vlv_set_cdclk() argument
638 int cdclk = cdclk_config->cdclk; in vlv_set_cdclk()
639 u32 val, cmd = cdclk_config->voltage_level; in vlv_set_cdclk()
724 const struct intel_cdclk_config *cdclk_config, in chv_set_cdclk() argument
728 int cdclk = cdclk_config->cdclk; in chv_set_cdclk()
729 u32 val, cmd = cdclk_config->voltage_level; in chv_set_cdclk()
800 struct intel_cdclk_config *cdclk_config) in bdw_get_cdclk() argument
806 cdclk_config->cdclk = 800000; in bdw_get_cdclk()
808 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
810 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
812 cdclk_config->cdclk = 540000; in bdw_get_cdclk()
814 cdclk_config->cdclk = 337500; in bdw_get_cdclk()
816 cdclk_config->cdclk = 675000; in bdw_get_cdclk()
822 cdclk_config->voltage_level = in bdw_get_cdclk()
823 bdw_calc_voltage_level(cdclk_config->cdclk); in bdw_get_cdclk()
844 const struct intel_cdclk_config *cdclk_config, in bdw_set_cdclk() argument
848 int cdclk = cdclk_config->cdclk; in bdw_set_cdclk()
889 cdclk_config->voltage_level); in bdw_set_cdclk()
933 struct intel_cdclk_config *cdclk_config) in skl_dpll0_update() argument
937 cdclk_config->ref = 24000; in skl_dpll0_update()
938 cdclk_config->vco = 0; in skl_dpll0_update()
961 cdclk_config->vco = 8100000; in skl_dpll0_update()
965 cdclk_config->vco = 8640000; in skl_dpll0_update()
974 struct intel_cdclk_config *cdclk_config) in skl_get_cdclk() argument
978 skl_dpll0_update(display, cdclk_config); in skl_get_cdclk()
980 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; in skl_get_cdclk()
982 if (cdclk_config->vco == 0) in skl_get_cdclk()
987 if (cdclk_config->vco == 8640000) { in skl_get_cdclk()
990 cdclk_config->cdclk = 432000; in skl_get_cdclk()
993 cdclk_config->cdclk = 308571; in skl_get_cdclk()
996 cdclk_config->cdclk = 540000; in skl_get_cdclk()
999 cdclk_config->cdclk = 617143; in skl_get_cdclk()
1008 cdclk_config->cdclk = 450000; in skl_get_cdclk()
1011 cdclk_config->cdclk = 337500; in skl_get_cdclk()
1014 cdclk_config->cdclk = 540000; in skl_get_cdclk()
1017 cdclk_config->cdclk = 675000; in skl_get_cdclk()
1030 cdclk_config->voltage_level = in skl_get_cdclk()
1031 skl_calc_voltage_level(cdclk_config->cdclk); in skl_get_cdclk()
1126 const struct intel_cdclk_config *cdclk_config, in skl_set_cdclk() argument
1130 int cdclk = cdclk_config->cdclk; in skl_set_cdclk()
1131 int vco = cdclk_config->vco; in skl_set_cdclk()
1193 cdclk_config->voltage_level); in skl_set_cdclk()
1242 struct intel_cdclk_config cdclk_config; in skl_cdclk_init_hw() local
1258 cdclk_config = display->cdclk.hw; in skl_cdclk_init_hw()
1260 cdclk_config.vco = display->cdclk.skl_preferred_vco_freq; in skl_cdclk_init_hw()
1261 if (cdclk_config.vco == 0) in skl_cdclk_init_hw()
1262 cdclk_config.vco = 8100000; in skl_cdclk_init_hw()
1263 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); in skl_cdclk_init_hw()
1264 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); in skl_cdclk_init_hw()
1266 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); in skl_cdclk_init_hw()
1271 struct intel_cdclk_config cdclk_config = display->cdclk.hw; in skl_cdclk_uninit_hw() local
1273 cdclk_config.cdclk = cdclk_config.bypass; in skl_cdclk_uninit_hw()
1274 cdclk_config.vco = 0; in skl_cdclk_uninit_hw()
1275 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); in skl_cdclk_uninit_hw()
1277 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); in skl_cdclk_uninit_hw()
1641 struct intel_cdclk_config *cdclk_config) in icl_readout_refclk() argument
1650 cdclk_config->ref = 24000; in icl_readout_refclk()
1653 cdclk_config->ref = 19200; in icl_readout_refclk()
1656 cdclk_config->ref = 38400; in icl_readout_refclk()
1662 struct intel_cdclk_config *cdclk_config) in bxt_de_pll_readout() argument
1668 cdclk_config->ref = 38400; in bxt_de_pll_readout()
1670 icl_readout_refclk(display, cdclk_config); in bxt_de_pll_readout()
1672 cdclk_config->ref = 19200; in bxt_de_pll_readout()
1681 cdclk_config->vco = 0; in bxt_de_pll_readout()
1694 cdclk_config->vco = ratio * cdclk_config->ref; in bxt_de_pll_readout()
1698 struct intel_cdclk_config *cdclk_config) in bxt_get_cdclk() argument
1704 bxt_de_pll_readout(display, cdclk_config); in bxt_get_cdclk()
1707 cdclk_config->bypass = cdclk_config->ref / 2; in bxt_get_cdclk()
1709 cdclk_config->bypass = 50000; in bxt_get_cdclk()
1711 cdclk_config->bypass = cdclk_config->ref; in bxt_get_cdclk()
1713 if (cdclk_config->vco == 0) { in bxt_get_cdclk()
1714 cdclk_config->cdclk = cdclk_config->bypass; in bxt_get_cdclk()
1748 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * in bxt_get_cdclk()
1749 cdclk_config->vco, size * div); in bxt_get_cdclk()
1751 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); in bxt_get_cdclk()
1756 cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN; in bxt_get_cdclk()
1761 cdclk_config->voltage_level = in bxt_get_cdclk()
1762 intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk); in bxt_get_cdclk()
1965 const struct intel_cdclk_config *cdclk_config) in intel_mdclk_cdclk_ratio() argument
1968 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk); in intel_mdclk_cdclk_ratio()
1975 const struct intel_cdclk_config *cdclk_config) in xe2lpd_mdclk_cdclk_ratio_program() argument
1980 intel_mdclk_cdclk_ratio(display, cdclk_config), in xe2lpd_mdclk_cdclk_ratio_program()
1981 cdclk_config->joined_mbus); in xe2lpd_mdclk_cdclk_ratio_program()
2068 const struct intel_cdclk_config *cdclk_config, in bxt_cdclk_ctl() argument
2072 int cdclk = cdclk_config->cdclk; in bxt_cdclk_ctl()
2073 int vco = cdclk_config->vco; in bxt_cdclk_ctl()
2099 const struct intel_cdclk_config *cdclk_config, in _bxt_set_cdclk() argument
2102 int cdclk = cdclk_config->cdclk; in _bxt_set_cdclk()
2103 int vco = cdclk_config->vco; in _bxt_set_cdclk()
2125 intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe)); in _bxt_set_cdclk()
2132 const struct intel_cdclk_config *cdclk_config, in bxt_set_cdclk() argument
2137 int cdclk = cdclk_config->cdclk; in bxt_set_cdclk()
2170 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); in bxt_set_cdclk()
2173 cdclk_config, &mid_cdclk_config)) { in bxt_set_cdclk()
2175 _bxt_set_cdclk(display, cdclk_config, pipe); in bxt_set_cdclk()
2177 _bxt_set_cdclk(display, cdclk_config, pipe); in bxt_set_cdclk()
2181 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); in bxt_set_cdclk()
2190 cdclk_config->voltage_level); in bxt_set_cdclk()
2200 cdclk_config->voltage_level, in bxt_set_cdclk()
2217 display->cdclk.hw.voltage_level = cdclk_config->voltage_level; in bxt_set_cdclk()
2274 struct intel_cdclk_config cdclk_config; in bxt_cdclk_init_hw() local
2282 cdclk_config = display->cdclk.hw; in bxt_cdclk_init_hw()
2289 cdclk_config.cdclk = bxt_calc_cdclk(display, 0); in bxt_cdclk_init_hw()
2290 cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2291 cdclk_config.voltage_level = in bxt_cdclk_init_hw()
2292 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2294 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); in bxt_cdclk_init_hw()
2299 struct intel_cdclk_config cdclk_config = display->cdclk.hw; in bxt_cdclk_uninit_hw() local
2301 cdclk_config.cdclk = cdclk_config.bypass; in bxt_cdclk_uninit_hw()
2302 cdclk_config.vco = 0; in bxt_cdclk_uninit_hw()
2303 cdclk_config.voltage_level = in bxt_cdclk_uninit_hw()
2304 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); in bxt_cdclk_uninit_hw()
2306 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); in bxt_cdclk_uninit_hw()
2477 const struct intel_cdclk_config *cdclk_config, in intel_cdclk_dump_config() argument
2481 context, cdclk_config->cdclk, cdclk_config->vco, in intel_cdclk_dump_config()
2482 cdclk_config->ref, cdclk_config->bypass, in intel_cdclk_dump_config()
2483 cdclk_config->voltage_level); in intel_cdclk_dump_config()
2520 const struct intel_cdclk_config *cdclk_config, in intel_set_cdclk() argument
2526 if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config)) in intel_set_cdclk()
2532 intel_cdclk_dump_config(display, cdclk_config, context); in intel_set_cdclk()
2555 intel_cdclk_set_cdclk(display, cdclk_config, pipe); in intel_set_cdclk()
2573 intel_cdclk_changed(&display->cdclk.hw, cdclk_config), in intel_set_cdclk()
2576 intel_cdclk_dump_config(display, cdclk_config, "[sw state]"); in intel_set_cdclk()
2689 struct intel_cdclk_config cdclk_config; in intel_set_cdclk_pre_plane_update() local
2700 cdclk_config = new_cdclk_state->actual; in intel_set_cdclk_pre_plane_update()
2704 cdclk_config = new_cdclk_state->actual; in intel_set_cdclk_pre_plane_update()
2707 cdclk_config = old_cdclk_state->actual; in intel_set_cdclk_pre_plane_update()
2711 cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level, in intel_set_cdclk_pre_plane_update()
2719 cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus; in intel_set_cdclk_pre_plane_update()
2723 intel_set_cdclk(display, &cdclk_config, pipe, in intel_set_cdclk_pre_plane_update()