Lines Matching +full:vco +full:- +full:offset
2 * Copyright © 2006-2017 Intel Corporation
77 * - We have the CDCLK PLL, which generates an output clock based on a
79 * - The CD2X Divider, which divides the output of the PLL based on a
80 * divisor selected from a set of pre-defined choices.
81 * - The CD2X Squasher, which further divides the output based on a
84 * - And, finally, a fixed divider that divides the output frequency by 2.
89 * cdclk = vco / cd2x_div / (sq_len / sq_div) / 2
91 * , where vco is the frequency generated by the PLL; cd2x_div
103 * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive.
104 * - CD2X divider update. Single pipe can be active as the divider update
106 * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active.
107 * - Squash waveform update. Pipes can be active.
108 * - Crawl and squash can also be done back to back. Pipes can be active.
129 display->funcs.cdclk->get_cdclk(display, cdclk_config);
136 display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe);
143 return display->funcs.cdclk->modeset_calc_cdclk(state);
149 return display->funcs.cdclk->calc_voltage_level(cdclk);
155 cdclk_config->cdclk = 133333;
161 cdclk_config->cdclk = 200000;
167 cdclk_config->cdclk = 266667;
173 cdclk_config->cdclk = 333333;
179 cdclk_config->cdclk = 400000;
185 cdclk_config->cdclk = 450000;
191 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
199 if (pdev->revision == 0x1) {
200 cdclk_config->cdclk = 133333;
204 pci_bus_read_config_word(pdev->bus,
214 cdclk_config->cdclk = 200000;
217 cdclk_config->cdclk = 250000;
220 cdclk_config->cdclk = 133333;
225 cdclk_config->cdclk = 266667;
233 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
239 cdclk_config->cdclk = 133333;
245 cdclk_config->cdclk = 333333;
249 cdclk_config->cdclk = 190000;
257 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
263 cdclk_config->cdclk = 133333;
269 cdclk_config->cdclk = 320000;
273 cdclk_config->cdclk = 200000;
318 unsigned int vco;
322 if (display->platform.gm45)
324 else if (display->platform.g45)
326 else if (display->platform.i965gm)
328 else if (display->platform.pineview)
330 else if (display->platform.g33)
335 tmp = intel_de_read(display, display->platform.pineview ||
336 display->platform.mobile ? HPLLVCO_MOBILE : HPLLVCO);
338 vco = vco_table[tmp & 0x7];
339 if (vco == 0)
340 drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",
343 drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco);
345 return vco;
351 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
360 cdclk_config->vco = intel_hpll_vco(display);
369 switch (cdclk_config->vco) {
386 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
391 drm_err(display->drm,
392 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
393 cdclk_config->vco, tmp);
394 cdclk_config->cdclk = 190476;
400 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
407 cdclk_config->cdclk = 266667;
410 cdclk_config->cdclk = 333333;
413 cdclk_config->cdclk = 444444;
416 cdclk_config->cdclk = 200000;
419 drm_err(display->drm,
423 cdclk_config->cdclk = 133333;
426 cdclk_config->cdclk = 166667;
434 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
442 cdclk_config->vco = intel_hpll_vco(display);
446 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
451 switch (cdclk_config->vco) {
465 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
470 drm_err(display->drm,
471 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
472 cdclk_config->vco, tmp);
473 cdclk_config->cdclk = 200000;
479 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
483 cdclk_config->vco = intel_hpll_vco(display);
489 switch (cdclk_config->vco) {
493 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222;
496 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571;
499 drm_err(display->drm,
500 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
501 cdclk_config->vco, tmp);
502 cdclk_config->cdclk = 222222;
514 cdclk_config->cdclk = 800000;
516 cdclk_config->cdclk = 450000;
518 cdclk_config->cdclk = 450000;
519 else if (display->platform.haswell_ult)
520 cdclk_config->cdclk = 337500;
522 cdclk_config->cdclk = 540000;
527 struct drm_i915_private *dev_priv = to_i915(display->drm);
528 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ?
536 if (display->platform.valleyview && min_cdclk > freq_320)
548 struct drm_i915_private *dev_priv = to_i915(display->drm);
550 if (display->platform.valleyview) {
563 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
570 struct drm_i915_private *dev_priv = to_i915(display->drm);
576 cdclk_config->vco = vlv_get_hpll_vco(dev_priv);
577 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
579 cdclk_config->vco);
586 if (display->platform.valleyview)
587 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >>
590 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
596 struct drm_i915_private *dev_priv = to_i915(display->drm);
599 if (display->platform.cherryview)
604 if (display->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
606 if (display->platform.cherryview)
615 * WA - write default credits before re-programming
628 drm_WARN_ON(display->drm,
636 struct drm_i915_private *dev_priv = to_i915(display->drm);
637 int cdclk = cdclk_config->cdclk;
638 u32 val, cmd = cdclk_config->voltage_level;
673 drm_err(display->drm,
680 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
681 cdclk) - 1;
692 drm_err(display->drm,
696 /* adjust self-refresh exit latency value */
726 struct drm_i915_private *dev_priv = to_i915(display->drm);
727 int cdclk = cdclk_config->cdclk;
728 u32 val, cmd = cdclk_config->voltage_level;
758 drm_err(display->drm,
805 cdclk_config->cdclk = 800000;
807 cdclk_config->cdclk = 450000;
809 cdclk_config->cdclk = 450000;
811 cdclk_config->cdclk = 540000;
813 cdclk_config->cdclk = 337500;
815 cdclk_config->cdclk = 675000;
821 cdclk_config->voltage_level =
822 bdw_calc_voltage_level(cdclk_config->cdclk);
846 struct drm_i915_private *dev_priv = to_i915(display->drm);
847 int cdclk = cdclk_config->cdclk;
850 if (drm_WARN(display->drm,
859 ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
861 drm_err(display->drm,
875 drm_err(display->drm, "Switching to FCLK failed\n");
885 drm_err(display->drm, "Switching back to LCPLL failed\n");
887 snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ,
888 cdclk_config->voltage_level);
891 DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
896 static int skl_calc_cdclk(int min_cdclk, int vco)
898 if (vco == 8640000) {
936 cdclk_config->ref = 24000;
937 cdclk_config->vco = 0;
943 if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0))
948 if (drm_WARN_ON(display->drm,
960 cdclk_config->vco = 8100000;
964 cdclk_config->vco = 8640000;
979 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref;
981 if (cdclk_config->vco == 0)
986 if (cdclk_config->vco == 8640000) {
989 cdclk_config->cdclk = 432000;
992 cdclk_config->cdclk = 308571;
995 cdclk_config->cdclk = 540000;
998 cdclk_config->cdclk = 617143;
1007 cdclk_config->cdclk = 450000;
1010 cdclk_config->cdclk = 337500;
1013 cdclk_config->cdclk = 540000;
1016 cdclk_config->cdclk = 675000;
1029 cdclk_config->voltage_level =
1030 skl_calc_voltage_level(cdclk_config->cdclk);
1033 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
1036 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
1039 static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco)
1041 bool changed = display->cdclk.skl_preferred_vco_freq != vco;
1043 display->cdclk.skl_preferred_vco_freq = vco;
1049 static u32 skl_dpll0_link_rate(struct intel_display *display, int vco)
1051 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);
1055 * taking into account the VCO required to operate the eDP panel at the
1056 * desired frequency. The usual DP link rates operate with a VCO of
1057 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
1060 * works with vco.
1062 if (vco == 8640000)
1068 static void skl_dpll0_enable(struct intel_display *display, int vco)
1075 skl_dpll0_link_rate(display, vco));
1082 drm_err(display->drm, "DPLL0 not locked\n");
1084 display->cdclk.hw.vco = vco;
1086 /* We'll want to keep using the current vco from now on. */
1087 skl_set_preferred_cdclk_vco(display, vco);
1096 drm_err(display->drm, "Couldn't disable DPLL0\n");
1098 display->cdclk.hw.vco = 0;
1102 int cdclk, int vco)
1106 drm_WARN_ON(display->drm,
1107 cdclk != display->cdclk.hw.bypass);
1108 drm_WARN_ON(display->drm, vco != 0);
1128 struct drm_i915_private *dev_priv = to_i915(display->drm);
1129 int cdclk = cdclk_config->cdclk;
1130 int vco = cdclk_config->vco;
1139 * use the corresponding VCO freq as that always leads to using the
1142 drm_WARN_ON_ONCE(display->drm,
1143 display->platform.skylake && vco == 8640000);
1145 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
1150 drm_err(display->drm,
1155 freq_select = skl_cdclk_freq_sel(display, cdclk, vco);
1157 if (display->cdclk.hw.vco != 0 &&
1158 display->cdclk.hw.vco != vco)
1163 if (display->cdclk.hw.vco != vco) {
1175 if (display->cdclk.hw.vco != vco)
1176 skl_dpll0_enable(display, vco);
1191 snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
1192 cdclk_config->voltage_level);
1202 * check if the pre-os initialized the display
1204 * pre-os which can be used by the OS drivers to check the status
1210 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
1213 if (display->cdclk.hw.vco == 0 ||
1214 display->cdclk.hw.cdclk == display->cdclk.hw.bypass)
1220 * decimal part is programmed wrong from BIOS where pre-os does not
1225 skl_cdclk_decimal(display->cdclk.hw.cdclk);
1231 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");
1234 display->cdclk.hw.cdclk = 0;
1236 display->cdclk.hw.vco = ~0;
1245 if (display->cdclk.hw.cdclk != 0 &&
1246 display->cdclk.hw.vco != 0) {
1248 * Use the current vco as our initial
1249 * guess as to what the preferred vco is.
1251 if (display->cdclk.skl_preferred_vco_freq == 0)
1253 display->cdclk.hw.vco);
1257 cdclk_config = display->cdclk.hw;
1259 cdclk_config.vco = display->cdclk.skl_preferred_vco_freq;
1260 if (cdclk_config.vco == 0)
1261 cdclk_config.vco = 8100000;
1262 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
1270 struct intel_cdclk_config cdclk_config = display->cdclk.hw;
1273 cdclk_config.vco = 0;
1510 static int cdclk_divider(int cdclk, int vco, u16 waveform)
1513 return DIV_ROUND_CLOSEST(vco * cdclk_squash_divider(waveform),
1519 const struct intel_cdclk_vals *table = display->cdclk.table;
1523 if (table[i].refclk == display->cdclk.hw.ref &&
1527 drm_WARN(display->drm, 1,
1529 min_cdclk, display->cdclk.hw.ref);
1535 const struct intel_cdclk_vals *table = display->cdclk.table;
1538 if (cdclk == display->cdclk.hw.bypass)
1542 if (table[i].refclk == display->cdclk.hw.ref &&
1544 return display->cdclk.hw.ref * table[i].ratio;
1546 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n",
1547 cdclk, display->cdclk.hw.ref);
1567 return num_voltage_levels - 1;
1649 cdclk_config->ref = 24000;
1652 cdclk_config->ref = 19200;
1655 cdclk_config->ref = 38400;
1665 if (display->platform.dg2)
1666 cdclk_config->ref = 38400;
1670 cdclk_config->ref = 19200;
1676 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
1679 cdclk_config->vco = 0;
1692 cdclk_config->vco = ratio * cdclk_config->ref;
1705 cdclk_config->bypass = cdclk_config->ref / 2;
1707 cdclk_config->bypass = 50000;
1709 cdclk_config->bypass = cdclk_config->ref;
1711 if (cdclk_config->vco == 0) {
1712 cdclk_config->cdclk = cdclk_config->bypass;
1744 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size);
1746 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) *
1747 cdclk_config->vco, size * div);
1749 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
1754 cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN;
1759 cdclk_config->voltage_level =
1760 intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk);
1770 drm_err(display->drm, "timeout waiting for DE PLL unlock\n");
1772 display->cdclk.hw.vco = 0;
1775 static void bxt_de_pll_enable(struct intel_display *display, int vco)
1777 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1787 drm_err(display->drm, "timeout waiting for DE PLL lock\n");
1789 display->cdclk.hw.vco = vco;
1799 drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n");
1801 display->cdclk.hw.vco = 0;
1804 static void icl_cdclk_pll_enable(struct intel_display *display, int vco)
1806 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1817 drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n");
1819 display->cdclk.hw.vco = vco;
1822 static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco)
1824 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1838 drm_err(display->drm, "timeout waiting for FREQ change request ack\n");
1843 display->cdclk.hw.vco = vco;
1867 int cdclk, int vco, u16 waveform)
1869 /* cdclk = vco / 2 / div{1,1.5,2,4} */
1870 switch (cdclk_divider(cdclk, vco, waveform)) {
1872 drm_WARN_ON(display->drm,
1873 cdclk != display->cdclk.hw.bypass);
1874 drm_WARN_ON(display->drm, vco != 0);
1890 const struct intel_cdclk_vals *table = display->cdclk.table;
1893 if (cdclk == display->cdclk.hw.bypass)
1897 if (table[i].refclk == display->cdclk.hw.ref &&
1901 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n",
1902 cdclk, display->cdclk.hw.ref);
1907 static void icl_cdclk_pll_update(struct intel_display *display, int vco)
1909 if (display->cdclk.hw.vco != 0 &&
1910 display->cdclk.hw.vco != vco)
1913 if (display->cdclk.hw.vco != vco)
1914 icl_cdclk_pll_enable(display, vco);
1917 static void bxt_cdclk_pll_update(struct intel_display *display, int vco)
1919 if (display->cdclk.hw.vco != 0 &&
1920 display->cdclk.hw.vco != vco)
1923 if (display->cdclk.hw.vco != vco)
1924 bxt_de_pll_enable(display, vco);
1939 static bool cdclk_pll_is_unknown(unsigned int vco)
1943 * case when the vco is set to ~0 in the
1946 return vco == ~0;
1966 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk);
1975 struct drm_i915_private *i915 = to_i915(display->drm);
1979 cdclk_config->joined_mbus);
1990 /* Return if PLL is in an unknown state, force a complete disable and re-enable. */
1991 if (cdclk_pll_is_unknown(old_cdclk_config->vco))
1998 old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk);
1999 new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk);
2002 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 ||
2003 old_cdclk_config->vco == new_cdclk_config->vco ||
2007 old_div = cdclk_divider(old_cdclk_config->cdclk,
2008 old_cdclk_config->vco, old_waveform);
2009 new_div = cdclk_divider(new_cdclk_config->cdclk,
2010 new_cdclk_config->vco, new_waveform);
2016 if (drm_WARN_ON(display->drm, old_div != new_div))
2023 * - If moving to a higher cdclk, the desired action is squashing.
2025 * - If moving to a lower cdclk, the desired action is crawling.
2026 * The mid cdclk config should have the new vco.
2030 mid_cdclk_config->vco = old_cdclk_config->vco;
2034 mid_cdclk_config->vco = new_cdclk_config->vco;
2039 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
2040 mid_cdclk_config->vco,
2045 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk <
2046 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
2047 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk >
2048 display->cdclk.max_cdclk_freq);
2049 drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) !=
2059 display->platform.dg2) &&
2060 display->cdclk.hw.vco > 0;
2067 int cdclk = cdclk_config->cdclk;
2068 int vco = cdclk_config->vco;
2074 val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) |
2081 if ((display->platform.geminilake || display->platform.broxton) &&
2097 int cdclk = cdclk_config->cdclk;
2098 int vco = cdclk_config->vco;
2100 if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 &&
2101 !cdclk_pll_is_unknown(display->cdclk.hw.vco)) {
2102 if (display->cdclk.hw.vco != vco)
2103 adlp_cdclk_pll_crawl(display, vco);
2109 icl_cdclk_pll_update(display, vco);
2111 bxt_cdclk_pll_update(display, vco);
2130 struct drm_i915_private *dev_priv = to_i915(display->drm);
2132 int cdclk = cdclk_config->cdclk;
2141 if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
2144 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
2153 ret = snb_pcode_write_timeout(&dev_priv->uncore,
2158 drm_err(display->drm,
2164 if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk)
2167 if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw,
2175 if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk)
2180 * NOOP - No Pcode communication needed for
2183 else if (DISPLAY_VER(display) >= 11 && !display->platform.dg2)
2184 ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
2185 cdclk_config->voltage_level);
2193 ret = snb_pcode_write_timeout(&dev_priv->uncore,
2195 cdclk_config->voltage_level,
2199 drm_err(display->drm,
2212 display->cdclk.hw.voltage_level = cdclk_config->voltage_level;
2218 int cdclk, vco;
2221 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
2223 if (display->cdclk.hw.vco == 0 ||
2224 display->cdclk.hw.cdclk == display->cdclk.hw.bypass)
2228 cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk);
2229 if (cdclk != display->cdclk.hw.cdclk)
2232 /* Make sure the VCO is correct for the cdclk */
2233 vco = bxt_calc_cdclk_pll_vco(display, cdclk);
2234 if (vco != display->cdclk.hw.vco)
2243 expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE);
2258 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");
2261 display->cdclk.hw.cdclk = 0;
2264 display->cdclk.hw.vco = ~0;
2273 if (display->cdclk.hw.cdclk != 0 &&
2274 display->cdclk.hw.vco != 0)
2277 cdclk_config = display->cdclk.hw;
2281 * - The initial CDCLK needs to be read from VBT.
2285 cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk);
2294 struct intel_cdclk_config cdclk_config = display->cdclk.hw;
2297 cdclk_config.vco = 0;
2305 * intel_cdclk_init_hw - Initialize CDCLK hardware
2308 * Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and
2315 if (DISPLAY_VER(display) >= 10 || display->platform.broxton)
2322 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
2330 if (DISPLAY_VER(display) >= 10 || display->platform.broxton)
2343 drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco));
2345 if (a->vco == 0 || b->vco == 0)
2351 old_waveform = cdclk_squash_waveform(display, a->cdclk);
2352 new_waveform = cdclk_squash_waveform(display, b->cdclk);
2354 return a->vco != b->vco &&
2368 * The vco and cd2x divider will change independently
2371 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
2372 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
2374 return a->vco != 0 && b->vco != 0 &&
2375 a->vco != b->vco &&
2377 a->ref == b->ref;
2393 return a->cdclk != b->cdclk &&
2394 a->vco != 0 &&
2395 a->vco == b->vco &&
2396 a->ref == b->ref;
2400 * intel_cdclk_clock_changed - Check whether the clock changed
2405 * True if CDCLK changed in a way that requires re-programming and
2411 return a->cdclk != b->cdclk ||
2412 a->vco != b->vco ||
2413 a->ref != b->ref;
2417 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
2432 if (DISPLAY_VER(display) < 10 && !display->platform.broxton)
2444 return a->cdclk != b->cdclk &&
2445 a->vco != 0 &&
2446 a->vco == b->vco &&
2447 a->ref == b->ref;
2451 * intel_cdclk_changed - Determine if two CDCLK configurations are different
2462 a->voltage_level != b->voltage_level;
2469 drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
2470 context, cdclk_config->cdclk, cdclk_config->vco,
2471 cdclk_config->ref, cdclk_config->bypass,
2472 cdclk_config->voltage_level);
2482 struct drm_i915_private *i915 = to_i915(display->drm);
2486 if (!display->platform.dg2)
2497 ret = skl_pcode_request(&i915->uncore, SKL_PCODE_CDCLK_CONTROL,
2503 drm_err(display->drm,
2514 if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config))
2517 if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk))
2522 for_each_intel_encoder_with_psr(display->drm, encoder) {
2535 mutex_lock(&display->gmbus.mutex);
2536 for_each_intel_dp(display->drm, encoder) {
2539 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
2540 &display->gmbus.mutex);
2545 for_each_intel_dp(display->drm, encoder) {
2548 mutex_unlock(&intel_dp->aux.hw_mutex);
2550 mutex_unlock(&display->gmbus.mutex);
2552 for_each_intel_encoder_with_psr(display->drm, encoder) {
2560 if (drm_WARN(display->drm,
2561 intel_cdclk_changed(&display->cdclk.hw, cdclk_config),
2563 intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]");
2578 if (!intel_cdclk_changed(&old_cdclk_state->actual,
2579 &new_cdclk_state->actual) &&
2580 new_cdclk_state->active_pipes ==
2581 old_cdclk_state->active_pipes)
2587 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;
2588 update_pipe_count = hweight8(new_cdclk_state->active_pipes) >
2589 hweight8(old_cdclk_state->active_pipes);
2598 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk);
2607 num_active_pipes = hweight8(new_cdclk_state->active_pipes);
2624 voltage_level = new_cdclk_state->actual.voltage_level;
2626 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;
2627 update_pipe_count = hweight8(new_cdclk_state->active_pipes) <
2628 hweight8(old_cdclk_state->active_pipes);
2635 cdclk = new_cdclk_state->actual.cdclk;
2644 num_active_pipes = hweight8(new_cdclk_state->active_pipes);
2657 return new_cdclk_state && !new_cdclk_state->disable_pipes &&
2658 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk;
2662 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
2679 if (!intel_cdclk_changed(&old_cdclk_state->actual,
2680 &new_cdclk_state->actual))
2683 if (display->platform.dg2)
2686 if (new_cdclk_state->disable_pipes) {
2687 cdclk_config = new_cdclk_state->actual;
2690 if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) {
2691 cdclk_config = new_cdclk_state->actual;
2692 pipe = new_cdclk_state->pipe;
2694 cdclk_config = old_cdclk_state->actual;
2698 cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level,
2699 old_cdclk_state->actual.voltage_level);
2706 cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus;
2708 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
2715 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
2731 if (!intel_cdclk_changed(&old_cdclk_state->actual,
2732 &new_cdclk_state->actual))
2735 if (display->platform.dg2)
2738 if (!new_cdclk_state->disable_pipes &&
2739 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk)
2740 pipe = new_cdclk_state->pipe;
2744 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
2746 intel_set_cdclk(display, &new_cdclk_state->actual, pipe,
2760 display->platform.broadwell || display->platform.haswell)
2762 else if (display->platform.cherryview)
2771 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);
2773 int pixel_rate = crtc_state->pixel_rate;
2780 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2785 for_each_intel_plane_on_crtc(display->drm, crtc, plane)
2786 min_cdclk = max(min_cdclk, crtc_state->min_cdclk[plane->id]);
2795 if (!crtc_state->hw.enable)
2811 struct drm_i915_private *dev_priv = to_i915(display->drm);
2827 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk)
2830 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
2832 ret = intel_atomic_lock_global_state(&cdclk_state->base);
2841 if (cdclk_state->bw_min_cdclk != min_cdclk) {
2844 cdclk_state->bw_min_cdclk = min_cdclk;
2846 ret = intel_atomic_lock_global_state(&cdclk_state->base);
2852 min_cdclk = max(cdclk_state->force_min_cdclk,
2853 cdclk_state->bw_min_cdclk);
2855 min_cdclk = max(min_cdclk, cdclk_state->min_cdclk[pipe]);
2865 if (display->platform.geminilake && cdclk_state->active_pipes &&
2866 !is_power_of_2(cdclk_state->active_pipes))
2869 if (min_cdclk > display->cdclk.max_cdclk_freq) {
2870 drm_dbg_kms(display->drm,
2872 min_cdclk, display->cdclk.max_cdclk_freq);
2873 return -EINVAL;
2906 if (crtc_state->hw.enable)
2907 min_voltage_level = crtc_state->min_voltage_level;
2911 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level)
2914 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level;
2916 ret = intel_atomic_lock_global_state(&cdclk_state->base);
2924 cdclk_state->min_voltage_level[pipe]);
2942 cdclk_state->logical.cdclk = cdclk;
2943 cdclk_state->logical.voltage_level =
2946 if (!cdclk_state->active_pipes) {
2947 cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk);
2949 cdclk_state->actual.cdclk = cdclk;
2950 cdclk_state->actual.voltage_level =
2953 cdclk_state->actual = cdclk_state->logical;
2971 cdclk_state->logical.cdclk = cdclk;
2972 cdclk_state->logical.voltage_level =
2975 if (!cdclk_state->active_pipes) {
2976 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk);
2978 cdclk_state->actual.cdclk = cdclk;
2979 cdclk_state->actual.voltage_level =
2982 cdclk_state->actual = cdclk_state->logical;
2995 int vco, i;
2997 vco = cdclk_state->logical.vco;
2998 if (!vco)
2999 vco = display->cdclk.skl_preferred_vco_freq;
3002 if (!crtc_state->hw.enable)
3009 * DPLL0 VCO may need to be adjusted to get the correct
3012 switch (crtc_state->port_clock / 2) {
3015 vco = 8640000;
3018 vco = 8100000;
3023 return vco;
3030 int min_cdclk, cdclk, vco;
3036 vco = skl_dpll0_vco(state);
3038 cdclk = skl_calc_cdclk(min_cdclk, vco);
3040 cdclk_state->logical.vco = vco;
3041 cdclk_state->logical.cdclk = cdclk;
3042 cdclk_state->logical.voltage_level =
3045 if (!cdclk_state->active_pipes) {
3046 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco);
3048 cdclk_state->actual.vco = vco;
3049 cdclk_state->actual.cdclk = cdclk;
3050 cdclk_state->actual.voltage_level =
3053 cdclk_state->actual = cdclk_state->logical;
3064 int min_cdclk, min_voltage_level, cdclk, vco;
3075 vco = bxt_calc_cdclk_pll_vco(display, cdclk);
3077 cdclk_state->logical.vco = vco;
3078 cdclk_state->logical.cdclk = cdclk;
3079 cdclk_state->logical.voltage_level =
3083 if (!cdclk_state->active_pipes) {
3084 cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk);
3085 vco = bxt_calc_cdclk_pll_vco(display, cdclk);
3087 cdclk_state->actual.vco = vco;
3088 cdclk_state->actual.cdclk = cdclk;
3089 cdclk_state->actual.voltage_level =
3092 cdclk_state->actual = cdclk_state->logical;
3118 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL);
3122 cdclk_state->pipe = INVALID_PIPE;
3123 cdclk_state->disable_pipes = false;
3125 return &cdclk_state->base;
3145 cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj);
3181 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
3195 cdclk_state->actual.joined_mbus = joined_mbus;
3196 cdclk_state->logical.joined_mbus = joined_mbus;
3198 return intel_atomic_lock_global_state(&cdclk_state->base);
3207 return -ENOMEM;
3209 intel_atomic_global_obj_init(display, &display->cdclk.obj,
3210 &cdclk_state->base, &intel_cdclk_funcs);
3219 bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) !=
3220 hweight8(new_cdclk_state->active_pipes);
3221 bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual,
3222 &new_cdclk_state->actual);
3227 return cdclk_changed || (display->platform.dg2 && power_well_cnt_changed);
3244 new_cdclk_state->active_pipes =
3245 intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
3256 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base);
3259 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes ||
3260 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk ||
3261 intel_cdclk_changed(&old_cdclk_state->logical,
3262 &new_cdclk_state->logical)) {
3263 ret = intel_atomic_lock_global_state(&new_cdclk_state->base);
3270 if (is_power_of_2(new_cdclk_state->active_pipes) &&
3272 &old_cdclk_state->actual,
3273 &new_cdclk_state->actual)) {
3277 pipe = ilog2(new_cdclk_state->active_pipes);
3280 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
3289 &old_cdclk_state->actual,
3290 &new_cdclk_state->actual)) {
3291 drm_dbg_kms(display->drm,
3294 &old_cdclk_state->actual,
3295 &new_cdclk_state->actual)) {
3296 drm_dbg_kms(display->drm,
3299 &old_cdclk_state->actual,
3300 &new_cdclk_state->actual)) {
3301 drm_dbg_kms(display->drm,
3304 new_cdclk_state->pipe = pipe;
3306 drm_dbg_kms(display->drm,
3309 } else if (intel_cdclk_clock_changed(&old_cdclk_state->actual,
3310 &new_cdclk_state->actual)) {
3316 new_cdclk_state->disable_pipes = true;
3318 drm_dbg_kms(display->drm,
3322 if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) !=
3323 intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) {
3324 int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual);
3331 drm_dbg_kms(display->drm,
3333 new_cdclk_state->logical.cdclk,
3334 new_cdclk_state->actual.cdclk);
3335 drm_dbg_kms(display->drm,
3337 new_cdclk_state->logical.voltage_level,
3338 new_cdclk_state->actual.voltage_level);
3346 to_intel_cdclk_state(display->cdclk.obj.state);
3349 cdclk_state->active_pipes = 0;
3351 for_each_intel_crtc(display->drm, crtc) {
3353 to_intel_crtc_state(crtc->base.state);
3354 enum pipe pipe = crtc->pipe;
3356 if (crtc_state->hw.active)
3357 cdclk_state->active_pipes |= BIT(pipe);
3359 cdclk_state->min_cdclk[pipe] = intel_crtc_compute_min_cdclk(crtc_state);
3360 cdclk_state->min_voltage_level[pipe] = crtc_state->min_voltage_level;
3375 int max_cdclk_freq = display->cdclk.max_cdclk_freq;
3381 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
3391 display->cdclk.max_cdclk_freq = 691200;
3392 } else if (display->platform.jasperlake || display->platform.elkhartlake) {
3393 if (display->cdclk.hw.ref == 24000)
3394 display->cdclk.max_cdclk_freq = 552000;
3396 display->cdclk.max_cdclk_freq = 556800;
3398 if (display->cdclk.hw.ref == 24000)
3399 display->cdclk.max_cdclk_freq = 648000;
3401 display->cdclk.max_cdclk_freq = 652800;
3402 } else if (display->platform.geminilake) {
3403 display->cdclk.max_cdclk_freq = 316800;
3404 } else if (display->platform.broxton) {
3405 display->cdclk.max_cdclk_freq = 624000;
3408 int max_cdclk, vco;
3410 vco = display->cdclk.skl_preferred_vco_freq;
3411 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);
3414 * Use the lower (vco 8640) cdclk values as a
3416 * if the preferred vco is 8100 instead.
3427 display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
3428 } else if (display->platform.broadwell) {
3436 display->cdclk.max_cdclk_freq = 450000;
3437 else if (display->platform.broadwell_ulx)
3438 display->cdclk.max_cdclk_freq = 450000;
3439 else if (display->platform.broadwell_ult)
3440 display->cdclk.max_cdclk_freq = 540000;
3442 display->cdclk.max_cdclk_freq = 675000;
3443 } else if (display->platform.cherryview) {
3444 display->cdclk.max_cdclk_freq = 320000;
3445 } else if (display->platform.valleyview) {
3446 display->cdclk.max_cdclk_freq = 400000;
3449 display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk;
3452 display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display);
3454 drm_dbg(display->drm, "Max CD clock rate: %d kHz\n",
3455 display->cdclk.max_cdclk_freq);
3457 drm_dbg(display->drm, "Max dotclock rate: %d kHz\n",
3458 display->cdclk.max_dotclk_freq);
3462 * intel_update_cdclk - Determine the current CDCLK frequency
3469 intel_cdclk_get_cdclk(display, &display->cdclk.hw);
3477 if (display->platform.valleyview || display->platform.cherryview)
3479 DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000));
3496 struct drm_i915_private *dev_priv = to_i915(display->drm);
3515 fraction) - 1);
3531 struct drm_i915_private *dev_priv = to_i915(display->drm);
3540 struct drm_i915_private *i915 = to_i915(display->drm);
3547 * intel_read_rawclk - Determine the current RAWCLK frequency
3555 struct drm_i915_private *dev_priv = to_i915(display->drm);
3571 else if (display->platform.valleyview || display->platform.cherryview)
3584 struct intel_display *display = m->private;
3586 seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk);
3587 seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq);
3588 seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq);
3597 struct drm_minor *minor = display->drm->primary;
3599 debugfs_create_file("i915_cdclk_info", 0444, minor->debugfs_root,
3747 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
3753 display->funcs.cdclk = &xe3lpd_cdclk_funcs;
3754 display->cdclk.table = xe3lpd_cdclk_table;
3756 display->funcs.cdclk = &rplu_cdclk_funcs;
3757 display->cdclk.table = xe2lpd_cdclk_table;
3759 display->funcs.cdclk = &rplu_cdclk_funcs;
3760 display->cdclk.table = xe2hpd_cdclk_table;
3762 display->funcs.cdclk = &rplu_cdclk_funcs;
3763 display->cdclk.table = mtl_cdclk_table;
3764 } else if (display->platform.dg2) {
3765 display->funcs.cdclk = &tgl_cdclk_funcs;
3766 display->cdclk.table = dg2_cdclk_table;
3767 } else if (display->platform.alderlake_p) {
3768 /* Wa_22011320316:adl-p[a0] */
3769 if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) {
3770 display->cdclk.table = adlp_a_step_cdclk_table;
3771 display->funcs.cdclk = &tgl_cdclk_funcs;
3772 } else if (display->platform.alderlake_p_raptorlake_u) {
3773 display->cdclk.table = rplu_cdclk_table;
3774 display->funcs.cdclk = &rplu_cdclk_funcs;
3776 display->cdclk.table = adlp_cdclk_table;
3777 display->funcs.cdclk = &tgl_cdclk_funcs;
3779 } else if (display->platform.rocketlake) {
3780 display->funcs.cdclk = &tgl_cdclk_funcs;
3781 display->cdclk.table = rkl_cdclk_table;
3783 display->funcs.cdclk = &tgl_cdclk_funcs;
3784 display->cdclk.table = icl_cdclk_table;
3785 } else if (display->platform.jasperlake || display->platform.elkhartlake) {
3786 display->funcs.cdclk = &ehl_cdclk_funcs;
3787 display->cdclk.table = icl_cdclk_table;
3789 display->funcs.cdclk = &icl_cdclk_funcs;
3790 display->cdclk.table = icl_cdclk_table;
3791 } else if (display->platform.geminilake || display->platform.broxton) {
3792 display->funcs.cdclk = &bxt_cdclk_funcs;
3793 if (display->platform.geminilake)
3794 display->cdclk.table = glk_cdclk_table;
3796 display->cdclk.table = bxt_cdclk_table;
3798 display->funcs.cdclk = &skl_cdclk_funcs;
3799 } else if (display->platform.broadwell) {
3800 display->funcs.cdclk = &bdw_cdclk_funcs;
3801 } else if (display->platform.haswell) {
3802 display->funcs.cdclk = &hsw_cdclk_funcs;
3803 } else if (display->platform.cherryview) {
3804 display->funcs.cdclk = &chv_cdclk_funcs;
3805 } else if (display->platform.valleyview) {
3806 display->funcs.cdclk = &vlv_cdclk_funcs;
3807 } else if (display->platform.sandybridge || display->platform.ivybridge) {
3808 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3809 } else if (display->platform.ironlake) {
3810 display->funcs.cdclk = &ilk_cdclk_funcs;
3811 } else if (display->platform.gm45) {
3812 display->funcs.cdclk = &gm45_cdclk_funcs;
3813 } else if (display->platform.g45) {
3814 display->funcs.cdclk = &g33_cdclk_funcs;
3815 } else if (display->platform.i965gm) {
3816 display->funcs.cdclk = &i965gm_cdclk_funcs;
3817 } else if (display->platform.i965g) {
3818 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3819 } else if (display->platform.pineview) {
3820 display->funcs.cdclk = &pnv_cdclk_funcs;
3821 } else if (display->platform.g33) {
3822 display->funcs.cdclk = &g33_cdclk_funcs;
3823 } else if (display->platform.i945gm) {
3824 display->funcs.cdclk = &i945gm_cdclk_funcs;
3825 } else if (display->platform.i945g) {
3826 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3827 } else if (display->platform.i915gm) {
3828 display->funcs.cdclk = &i915gm_cdclk_funcs;
3829 } else if (display->platform.i915g) {
3830 display->funcs.cdclk = &i915g_cdclk_funcs;
3831 } else if (display->platform.i865g) {
3832 display->funcs.cdclk = &i865g_cdclk_funcs;
3833 } else if (display->platform.i85x) {
3834 display->funcs.cdclk = &i85x_cdclk_funcs;
3835 } else if (display->platform.i845g) {
3836 display->funcs.cdclk = &i845g_cdclk_funcs;
3837 } else if (display->platform.i830) {
3838 display->funcs.cdclk = &i830_cdclk_funcs;
3841 if (drm_WARN(display->drm, !display->funcs.cdclk,
3843 display->funcs.cdclk = &i830_cdclk_funcs;