54  * are two main clocks involved that aren't directly related to the actual
55  * pixel clock or any symbol/bit clock of the actual output port. These
554 		 * Specs are full of misinformation, but testing on actual  in vlv_calc_voltage_level()
2519 	if (!intel_cdclk_changed(&old_cdclk_state->actual,  in intel_cdclk_pcode_pre_notify()
2520 				 &new_cdclk_state->actual) &&  in intel_cdclk_pcode_pre_notify()
2528 	change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;  in intel_cdclk_pcode_pre_notify()
2539 		cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk);  in intel_cdclk_pcode_pre_notify()
2565 	voltage_level = new_cdclk_state->actual.voltage_level;  in intel_cdclk_pcode_post_notify()
2567 	update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;  in intel_cdclk_pcode_post_notify()
2576 		cdclk = new_cdclk_state->actual.cdclk;  in intel_cdclk_pcode_post_notify()
2599 		new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk;  in intel_cdclk_is_decreasing_later()
2620 	if (!intel_cdclk_changed(&old_cdclk_state->actual,  in intel_set_cdclk_pre_plane_update()
2621 				 &new_cdclk_state->actual))  in intel_set_cdclk_pre_plane_update()
2628 		cdclk_config = new_cdclk_state->actual;  in intel_set_cdclk_pre_plane_update()
2631 		if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) {  in intel_set_cdclk_pre_plane_update()
2632 			cdclk_config = new_cdclk_state->actual;  in intel_set_cdclk_pre_plane_update()
2635 			cdclk_config = old_cdclk_state->actual;  in intel_set_cdclk_pre_plane_update()
2639 		cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level,  in intel_set_cdclk_pre_plane_update()
2640 						 old_cdclk_state->actual.voltage_level);  in intel_set_cdclk_pre_plane_update()
2647 	cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus;  in intel_set_cdclk_pre_plane_update()
2672 	if (!intel_cdclk_changed(&old_cdclk_state->actual,  in intel_set_cdclk_post_plane_update()
2673 				 &new_cdclk_state->actual))  in intel_set_cdclk_post_plane_update()
2680 	    new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk)  in intel_set_cdclk_post_plane_update()
2687 	intel_set_cdclk(i915, &new_cdclk_state->actual, pipe,  in intel_set_cdclk_post_plane_update()
2982 		cdclk_state->actual.cdclk = cdclk;  in vlv_modeset_calc_cdclk()
2983 		cdclk_state->actual.voltage_level =  in vlv_modeset_calc_cdclk()
2986 		cdclk_state->actual = cdclk_state->logical;  in vlv_modeset_calc_cdclk()
3011 		cdclk_state->actual.cdclk = cdclk;  in bdw_modeset_calc_cdclk()
3012 		cdclk_state->actual.voltage_level =  in bdw_modeset_calc_cdclk()
3015 		cdclk_state->actual = cdclk_state->logical;  in bdw_modeset_calc_cdclk()
3081 		cdclk_state->actual.vco = vco;  in skl_modeset_calc_cdclk()
3082 		cdclk_state->actual.cdclk = cdclk;  in skl_modeset_calc_cdclk()
3083 		cdclk_state->actual.voltage_level =  in skl_modeset_calc_cdclk()
3086 		cdclk_state->actual = cdclk_state->logical;  in skl_modeset_calc_cdclk()
3120 		cdclk_state->actual.vco = vco;  in bxt_modeset_calc_cdclk()
3121 		cdclk_state->actual.cdclk = cdclk;  in bxt_modeset_calc_cdclk()
3122 		cdclk_state->actual.voltage_level =  in bxt_modeset_calc_cdclk()
3125 		cdclk_state->actual = cdclk_state->logical;  in bxt_modeset_calc_cdclk()
3138 	 * the actual cdclk frequency.  in fixed_modeset_calc_cdclk()
3228 	cdclk_state->actual.joined_mbus = joined_mbus;  in intel_cdclk_state_set_joined_mbus()
3254 	bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual,  in intel_cdclk_need_serialize()
3255 						 &new_cdclk_state->actual);  in intel_cdclk_need_serialize()
3287 		 * if the actual hw needs to be poked.  in intel_modeset_calc_cdclk()
3305 					&old_cdclk_state->actual,  in intel_modeset_calc_cdclk()
3306 					&new_cdclk_state->actual)) {  in intel_modeset_calc_cdclk()
3322 					     &old_cdclk_state->actual,  in intel_modeset_calc_cdclk()
3323 					     &new_cdclk_state->actual)) {  in intel_modeset_calc_cdclk()
3327 					&old_cdclk_state->actual,  in intel_modeset_calc_cdclk()
3328 					&new_cdclk_state->actual)) {  in intel_modeset_calc_cdclk()
3332 					 &old_cdclk_state->actual,  in intel_modeset_calc_cdclk()
3333 					 &new_cdclk_state->actual)) {  in intel_modeset_calc_cdclk()
3342 	} else if (intel_cdclk_clock_changed(&old_cdclk_state->actual,  in intel_modeset_calc_cdclk()
3343 					     &new_cdclk_state->actual)) {  in intel_modeset_calc_cdclk()
3355 	if (intel_mdclk_cdclk_ratio(dev_priv, &old_cdclk_state->actual) !=  in intel_modeset_calc_cdclk()
3356 	    intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual)) {  in intel_modeset_calc_cdclk()
3357 		int ratio = intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual);  in intel_modeset_calc_cdclk()
3365 		    "New cdclk calculated to be logical %u kHz, actual %u kHz\n",  in intel_modeset_calc_cdclk()
3367 		    new_cdclk_state->actual.cdclk);  in intel_modeset_calc_cdclk()
3369 		    "New voltage level calculated to be logical %u, actual %u\n",  in intel_modeset_calc_cdclk()
3371 		    new_cdclk_state->actual.voltage_level);  in intel_modeset_calc_cdclk()