Lines Matching defs:vco
90 * cdclk = vco / cd2x_div / (sq_len / sq_div) / 2
92 * , where vco is the frequency generated by the PLL; cd2x_div
355 unsigned int vco;
375 vco = vco_table[tmp & 0x7];
376 if (vco == 0)
380 drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco);
382 return vco;
397 cdclk_config->vco = intel_hpll_vco(display);
406 switch (cdclk_config->vco) {
423 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
430 cdclk_config->vco, tmp);
479 cdclk_config->vco = intel_hpll_vco(display);
488 switch (cdclk_config->vco) {
502 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
509 cdclk_config->vco, tmp);
520 cdclk_config->vco = intel_hpll_vco(display);
526 switch (cdclk_config->vco) {
538 cdclk_config->vco, tmp);
611 cdclk_config->vco = vlv_get_hpll_vco(display->drm);
614 cdclk_config->vco);
929 static int skl_calc_cdclk(int min_cdclk, int vco)
931 if (vco == 8640000) {
970 cdclk_config->vco = 0;
993 cdclk_config->vco = 8100000;
997 cdclk_config->vco = 8640000;
1014 if (cdclk_config->vco == 0)
1019 if (cdclk_config->vco == 8640000) {
1072 static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco)
1074 bool changed = display->cdclk.skl_preferred_vco_freq != vco;
1076 display->cdclk.skl_preferred_vco_freq = vco;
1082 static u32 skl_dpll0_link_rate(struct intel_display *display, int vco)
1084 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);
1093 * works with vco.
1095 if (vco == 8640000)
1101 static void skl_dpll0_enable(struct intel_display *display, int vco)
1108 skl_dpll0_link_rate(display, vco));
1117 display->cdclk.hw.vco = vco;
1119 /* We'll want to keep using the current vco from now on. */
1120 skl_set_preferred_cdclk_vco(display, vco);
1131 display->cdclk.hw.vco = 0;
1135 int cdclk, int vco)
1141 drm_WARN_ON(display->drm, vco != 0);
1162 int vco = cdclk_config->vco;
1175 display->platform.skylake && vco == 8640000);
1187 freq_select = skl_cdclk_freq_sel(display, cdclk, vco);
1189 if (display->cdclk.hw.vco != 0 &&
1190 display->cdclk.hw.vco != vco)
1195 if (display->cdclk.hw.vco != vco) {
1207 if (display->cdclk.hw.vco != vco)
1208 skl_dpll0_enable(display, vco);
1245 if (display->cdclk.hw.vco == 0 ||
1268 display->cdclk.hw.vco = ~0;
1278 display->cdclk.hw.vco != 0) {
1280 * Use the current vco as our initial
1281 * guess as to what the preferred vco is.
1285 display->cdclk.hw.vco);
1291 cdclk_config.vco = display->cdclk.skl_preferred_vco_freq;
1292 if (cdclk_config.vco == 0)
1293 cdclk_config.vco = 8100000;
1294 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
1305 cdclk_config.vco = 0;
1542 static int cdclk_divider(int cdclk, int vco, u16 waveform)
1545 return DIV_ROUND_CLOSEST(vco * cdclk_squash_divider(waveform),
1711 cdclk_config->vco = 0;
1724 cdclk_config->vco = ratio * cdclk_config->ref;
1743 if (cdclk_config->vco == 0) {
1779 cdclk_config->vco, size * div);
1781 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
1804 display->cdclk.hw.vco = 0;
1807 static void bxt_de_pll_enable(struct intel_display *display, int vco)
1809 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1821 display->cdclk.hw.vco = vco;
1833 display->cdclk.hw.vco = 0;
1836 static void icl_cdclk_pll_enable(struct intel_display *display, int vco)
1838 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1851 display->cdclk.hw.vco = vco;
1854 static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco)
1856 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1875 display->cdclk.hw.vco = vco;
1899 int cdclk, int vco, u16 waveform)
1901 /* cdclk = vco / 2 / div{1,1.5,2,4} */
1902 switch (cdclk_divider(cdclk, vco, waveform)) {
1906 drm_WARN_ON(display->drm, vco != 0);
1939 static void icl_cdclk_pll_update(struct intel_display *display, int vco)
1941 if (display->cdclk.hw.vco != 0 &&
1942 display->cdclk.hw.vco != vco)
1945 if (display->cdclk.hw.vco != vco)
1946 icl_cdclk_pll_enable(display, vco);
1949 static void bxt_cdclk_pll_update(struct intel_display *display, int vco)
1951 if (display->cdclk.hw.vco != 0 &&
1952 display->cdclk.hw.vco != vco)
1955 if (display->cdclk.hw.vco != vco)
1956 bxt_de_pll_enable(display, vco);
1971 static bool cdclk_pll_is_unknown(unsigned int vco)
1975 * case when the vco is set to ~0 in the
1978 return vco == ~0;
1998 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk);
2021 if (cdclk_pll_is_unknown(old_cdclk_config->vco))
2032 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 ||
2033 old_cdclk_config->vco == new_cdclk_config->vco ||
2038 old_cdclk_config->vco, old_waveform);
2040 new_cdclk_config->vco, new_waveform);
2056 * The mid cdclk config should have the new vco.
2060 mid_cdclk_config->vco = old_cdclk_config->vco;
2064 mid_cdclk_config->vco = new_cdclk_config->vco;
2070 mid_cdclk_config->vco,
2090 display->cdclk.hw.vco > 0;
2098 int vco = cdclk_config->vco;
2104 val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) |
2128 int vco = cdclk_config->vco;
2130 if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 &&
2131 !cdclk_pll_is_unknown(display->cdclk.hw.vco)) {
2132 if (display->cdclk.hw.vco != vco)
2133 adlp_cdclk_pll_crawl(display, vco);
2139 icl_cdclk_pll_update(display, vco);
2141 bxt_cdclk_pll_update(display, vco);
2246 int cdclk, vco;
2251 if (display->cdclk.hw.vco == 0 ||
2261 vco = bxt_calc_cdclk_pll_vco(display, cdclk);
2262 if (vco != display->cdclk.hw.vco)
2292 display->cdclk.hw.vco = ~0;
2302 display->cdclk.hw.vco != 0)
2313 cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk);
2325 cdclk_config.vco = 0;
2371 drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco));
2373 if (a->vco == 0 || b->vco == 0)
2382 return a->vco != b->vco &&
2396 * The vco and cd2x divider will change independently
2399 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
2400 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
2402 return a->vco != 0 && b->vco != 0 &&
2403 a->vco != b->vco &&
2422 a->vco != 0 &&
2423 a->vco == b->vco &&
2440 a->vco != b->vco ||
2473 a->vco != 0 &&
2474 a->vco == b->vco &&
2498 context, cdclk_config->cdclk, cdclk_config->vco,
3021 int vco, i;
3023 vco = cdclk_state->logical.vco;
3024 if (!vco)
3025 vco = display->cdclk.skl_preferred_vco_freq;
3041 vco = 8640000;
3044 vco = 8100000;
3049 return vco;
3056 int min_cdclk, cdclk, vco;
3062 vco = skl_dpll0_vco(state);
3064 cdclk = skl_calc_cdclk(min_cdclk, vco);
3066 cdclk_state->logical.vco = vco;
3072 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco);
3074 cdclk_state->actual.vco = vco;
3090 int min_cdclk, min_voltage_level, cdclk, vco;
3101 vco = bxt_calc_cdclk_pll_vco(display, cdclk);
3103 cdclk_state->logical.vco = vco;
3111 vco = bxt_calc_cdclk_pll_vco(display, cdclk);
3113 cdclk_state->actual.vco = vco;
3440 int max_cdclk, vco;
3442 vco = display->cdclk.skl_preferred_vco_freq;
3443 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);
3446 * Use the lower (vco 8640) cdclk values as a
3448 * if the preferred vco is 8100 instead.
3459 display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);