Lines Matching full:display
42 static int dg1_mchbar_read_qgv_point_info(struct intel_display *display, in dg1_mchbar_read_qgv_point_info() argument
46 struct drm_i915_private *i915 = to_i915(display->drm); in dg1_mchbar_read_qgv_point_info()
78 static int icl_pcode_read_qgv_point_info(struct intel_display *display, in icl_pcode_read_qgv_point_info() argument
82 struct drm_i915_private *i915 = to_i915(display->drm); in icl_pcode_read_qgv_point_info()
94 sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(display) >= 12 ? 500 : 0), in icl_pcode_read_qgv_point_info()
107 static int adls_pcode_read_psf_gv_point_info(struct intel_display *display, in adls_pcode_read_psf_gv_point_info() argument
110 struct drm_i915_private *i915 = to_i915(display->drm); in adls_pcode_read_psf_gv_point_info()
128 static u16 icl_qgv_points_mask(struct intel_display *display) in icl_qgv_points_mask() argument
130 unsigned int num_psf_gv_points = display->bw.max[0].num_psf_gv_points; in icl_qgv_points_mask()
131 unsigned int num_qgv_points = display->bw.max[0].num_qgv_points; in icl_qgv_points_mask()
148 static bool is_sagv_enabled(struct intel_display *display, u16 points_mask) in is_sagv_enabled() argument
150 return !is_power_of_2(~points_mask & icl_qgv_points_mask(display) & in is_sagv_enabled()
154 int icl_pcode_restrict_qgv_points(struct intel_display *display, in icl_pcode_restrict_qgv_points() argument
157 struct drm_i915_private *i915 = to_i915(display->drm); in icl_pcode_restrict_qgv_points()
160 if (DISPLAY_VER(display) >= 14) in icl_pcode_restrict_qgv_points()
171 drm_err(display->drm, in icl_pcode_restrict_qgv_points()
177 display->sagv.status = is_sagv_enabled(display, points_mask) ? in icl_pcode_restrict_qgv_points()
183 static int mtl_read_qgv_point_info(struct intel_display *display, in mtl_read_qgv_point_info() argument
186 struct drm_i915_private *i915 = to_i915(display->drm); in mtl_read_qgv_point_info()
208 intel_read_qgv_point_info(struct intel_display *display, in intel_read_qgv_point_info() argument
212 if (DISPLAY_VER(display) >= 14) in intel_read_qgv_point_info()
213 return mtl_read_qgv_point_info(display, sp, point); in intel_read_qgv_point_info()
214 else if (display->platform.dg1) in intel_read_qgv_point_info()
215 return dg1_mchbar_read_qgv_point_info(display, sp, point); in intel_read_qgv_point_info()
217 return icl_pcode_read_qgv_point_info(display, sp, point); in intel_read_qgv_point_info()
220 static int icl_get_qgv_points(struct intel_display *display, in icl_get_qgv_points() argument
224 struct drm_i915_private *i915 = to_i915(display->drm); in icl_get_qgv_points()
231 if (DISPLAY_VER(display) >= 14) { in icl_get_qgv_points()
260 } else if (DISPLAY_VER(display) >= 12) { in icl_get_qgv_points()
275 if (display->platform.rocketlake) { in icl_get_qgv_points()
294 } else if (DISPLAY_VER(display) == 11) { in icl_get_qgv_points()
299 if (drm_WARN_ON(display->drm, in icl_get_qgv_points()
306 ret = intel_read_qgv_point_info(display, sp, i); in icl_get_qgv_points()
308 drm_dbg_kms(display->drm, "Could not read QGV %d info\n", i); in icl_get_qgv_points()
312 drm_dbg_kms(display->drm, in icl_get_qgv_points()
319 ret = adls_pcode_read_psf_gv_point_info(display, qi->psf_points); in icl_get_qgv_points()
321 …drm_err(display->drm, "Failed to read PSF point data; PSF points will not be considered in bandwid… in icl_get_qgv_points()
326 drm_dbg_kms(display->drm, in icl_get_qgv_points()
421 static int icl_get_bw_info(struct intel_display *display, const struct intel_sa_info *sa) in icl_get_bw_info() argument
423 struct drm_i915_private *i915 = to_i915(display->drm); in icl_get_bw_info()
430 int num_groups = ARRAY_SIZE(display->bw.max); in icl_get_bw_info()
433 ret = icl_get_qgv_points(display, &qi, is_y_tile); in icl_get_bw_info()
435 drm_dbg_kms(display->drm, in icl_get_bw_info()
446 struct intel_bw_info *bi = &display->bw.max[i]; in icl_get_bw_info()
473 drm_dbg_kms(display->drm, in icl_get_bw_info()
484 display->sagv.status = I915_SAGV_NOT_CONTROLLED; in icl_get_bw_info()
486 display->sagv.status = I915_SAGV_ENABLED; in icl_get_bw_info()
491 static int tgl_get_bw_info(struct intel_display *display, const struct intel_sa_info *sa) in tgl_get_bw_info() argument
493 struct drm_i915_private *i915 = to_i915(display->drm); in tgl_get_bw_info()
502 int num_groups = ARRAY_SIZE(display->bw.max); in tgl_get_bw_info()
505 ret = icl_get_qgv_points(display, &qi, is_y_tile); in tgl_get_bw_info()
507 drm_dbg_kms(display->drm, in tgl_get_bw_info()
512 if (DISPLAY_VER(display) < 14 && in tgl_get_bw_info()
518 if (num_channels < qi.max_numchannels && DISPLAY_VER(display) >= 12) in tgl_get_bw_info()
521 if (DISPLAY_VER(display) >= 12 && num_channels > qi.max_numchannels) in tgl_get_bw_info()
522 drm_warn(display->drm, "Number of channels exceeds max number of channels."); in tgl_get_bw_info()
539 struct intel_bw_info *bi = &display->bw.max[i]; in tgl_get_bw_info()
547 bi_next = &display->bw.max[i + 1]; in tgl_get_bw_info()
579 drm_dbg_kms(display->drm, in tgl_get_bw_info()
590 drm_dbg_kms(display->drm, in tgl_get_bw_info()
602 display->sagv.status = I915_SAGV_NOT_CONTROLLED; in tgl_get_bw_info()
604 display->sagv.status = I915_SAGV_ENABLED; in tgl_get_bw_info()
609 static void dg2_get_bw_info(struct intel_display *display) in dg2_get_bw_info() argument
611 unsigned int deratedbw = display->platform.dg2_g11 ? 38000 : 50000; in dg2_get_bw_info()
612 int num_groups = ARRAY_SIZE(display->bw.max); in dg2_get_bw_info()
623 struct intel_bw_info *bi = &display->bw.max[i]; in dg2_get_bw_info()
631 display->sagv.status = I915_SAGV_NOT_CONTROLLED; in dg2_get_bw_info()
634 static int xe2_hpd_get_bw_info(struct intel_display *display, in xe2_hpd_get_bw_info() argument
637 struct drm_i915_private *i915 = to_i915(display->drm); in xe2_hpd_get_bw_info()
643 ret = icl_get_qgv_points(display, &qi, true); in xe2_hpd_get_bw_info()
645 drm_dbg_kms(display->drm, in xe2_hpd_get_bw_info()
657 display->bw.max[0].deratedbw[i] = in xe2_hpd_get_bw_info()
659 display->bw.max[0].peakbw[i] = bw; in xe2_hpd_get_bw_info()
661 drm_dbg_kms(display->drm, "QGV %d: deratedbw=%u peakbw: %u\n", in xe2_hpd_get_bw_info()
662 i, display->bw.max[0].deratedbw[i], in xe2_hpd_get_bw_info()
663 display->bw.max[0].peakbw[i]); in xe2_hpd_get_bw_info()
667 display->bw.max[0].num_planes = 1; in xe2_hpd_get_bw_info()
668 display->bw.max[0].num_qgv_points = qi.num_points; in xe2_hpd_get_bw_info()
669 for (i = 1; i < ARRAY_SIZE(display->bw.max); i++) in xe2_hpd_get_bw_info()
670 memcpy(&display->bw.max[i], &display->bw.max[0], in xe2_hpd_get_bw_info()
671 sizeof(display->bw.max[0])); in xe2_hpd_get_bw_info()
677 drm_WARN_ON(display->drm, qi.num_points != 2); in xe2_hpd_get_bw_info()
678 display->sagv.status = I915_SAGV_ENABLED; in xe2_hpd_get_bw_info()
683 static unsigned int icl_max_bw_index(struct intel_display *display, in icl_max_bw_index() argument
693 for (i = 0; i < ARRAY_SIZE(display->bw.max); i++) { in icl_max_bw_index()
695 &display->bw.max[i]; in icl_max_bw_index()
711 static unsigned int tgl_max_bw_index(struct intel_display *display, in tgl_max_bw_index() argument
721 for (i = ARRAY_SIZE(display->bw.max) - 1; i >= 0; i--) { in tgl_max_bw_index()
723 &display->bw.max[i]; in tgl_max_bw_index()
739 static unsigned int adl_psf_bw(struct intel_display *display, in adl_psf_bw() argument
743 &display->bw.max[0]; in adl_psf_bw()
748 static unsigned int icl_qgv_bw(struct intel_display *display, in icl_qgv_bw() argument
753 if (DISPLAY_VER(display) >= 12) in icl_qgv_bw()
754 idx = tgl_max_bw_index(display, num_active_planes, qgv_point); in icl_qgv_bw()
756 idx = icl_max_bw_index(display, num_active_planes, qgv_point); in icl_qgv_bw()
758 if (idx >= ARRAY_SIZE(display->bw.max)) in icl_qgv_bw()
761 return display->bw.max[idx].deratedbw[qgv_point]; in icl_qgv_bw()
764 void intel_bw_init_hw(struct intel_display *display) in intel_bw_init_hw() argument
766 const struct dram_info *dram_info = &to_i915(display->drm)->dram_info; in intel_bw_init_hw()
768 if (!HAS_DISPLAY(display)) in intel_bw_init_hw()
771 if (DISPLAY_VER(display) >= 30) in intel_bw_init_hw()
772 tgl_get_bw_info(display, &xe3lpd_sa_info); in intel_bw_init_hw()
773 else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx && in intel_bw_init_hw()
775 xe2_hpd_get_bw_info(display, &xe2_hpd_ecc_sa_info); in intel_bw_init_hw()
776 else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) in intel_bw_init_hw()
777 xe2_hpd_get_bw_info(display, &xe2_hpd_sa_info); in intel_bw_init_hw()
778 else if (DISPLAY_VER(display) >= 14) in intel_bw_init_hw()
779 tgl_get_bw_info(display, &mtl_sa_info); in intel_bw_init_hw()
780 else if (display->platform.dg2) in intel_bw_init_hw()
781 dg2_get_bw_info(display); in intel_bw_init_hw()
782 else if (display->platform.alderlake_p) in intel_bw_init_hw()
783 tgl_get_bw_info(display, &adlp_sa_info); in intel_bw_init_hw()
784 else if (display->platform.alderlake_s) in intel_bw_init_hw()
785 tgl_get_bw_info(display, &adls_sa_info); in intel_bw_init_hw()
786 else if (display->platform.rocketlake) in intel_bw_init_hw()
787 tgl_get_bw_info(display, &rkl_sa_info); in intel_bw_init_hw()
788 else if (DISPLAY_VER(display) == 12) in intel_bw_init_hw()
789 tgl_get_bw_info(display, &tgl_sa_info); in intel_bw_init_hw()
790 else if (DISPLAY_VER(display) == 11) in intel_bw_init_hw()
791 icl_get_bw_info(display, &icl_sa_info); in intel_bw_init_hw()
805 struct intel_display *display = to_intel_display(crtc_state); in intel_bw_crtc_data_rate() local
820 if (DISPLAY_VER(display) < 11) in intel_bw_crtc_data_rate()
828 static int intel_bw_crtc_min_cdclk(struct intel_display *display, in intel_bw_crtc_min_cdclk() argument
831 if (DISPLAY_VER(display) < 12) in intel_bw_crtc_min_cdclk()
837 static unsigned int intel_bw_num_active_planes(struct intel_display *display, in intel_bw_num_active_planes() argument
843 for_each_pipe(display, pipe) in intel_bw_num_active_planes()
849 static unsigned int intel_bw_data_rate(struct intel_display *display, in intel_bw_data_rate() argument
852 struct drm_i915_private *i915 = to_i915(display->drm); in intel_bw_data_rate()
856 for_each_pipe(display, pipe) in intel_bw_data_rate()
859 if (DISPLAY_VER(display) >= 13 && i915_vtd_active(i915)) in intel_bw_data_rate()
868 struct intel_display *display = to_intel_display(state); in intel_atomic_get_old_bw_state() local
871 bw_state = intel_atomic_get_old_global_obj_state(state, &display->bw.obj); in intel_atomic_get_old_bw_state()
879 struct intel_display *display = to_intel_display(state); in intel_atomic_get_new_bw_state() local
882 bw_state = intel_atomic_get_new_global_obj_state(state, &display->bw.obj); in intel_atomic_get_new_bw_state()
890 struct intel_display *display = to_intel_display(state); in intel_atomic_get_bw_state() local
893 bw_state = intel_atomic_get_global_obj_state(state, &display->bw.obj); in intel_atomic_get_bw_state()
900 static unsigned int icl_max_bw_qgv_point_mask(struct intel_display *display, in icl_max_bw_qgv_point_mask() argument
903 unsigned int num_qgv_points = display->bw.max[0].num_qgv_points; in icl_max_bw_qgv_point_mask()
910 icl_qgv_bw(display, num_active_planes, i); in icl_max_bw_qgv_point_mask()
929 static u16 icl_prepare_qgv_points_mask(struct intel_display *display, in icl_prepare_qgv_points_mask() argument
934 ADLS_PCODE_REQ_PSF_PT(psf_points)) & icl_qgv_points_mask(display); in icl_prepare_qgv_points_mask()
937 static unsigned int icl_max_bw_psf_gv_point_mask(struct intel_display *display) in icl_max_bw_psf_gv_point_mask() argument
939 unsigned int num_psf_gv_points = display->bw.max[0].num_psf_gv_points; in icl_max_bw_psf_gv_point_mask()
945 unsigned int max_data_rate = adl_psf_bw(display, i); in icl_max_bw_psf_gv_point_mask()
958 static void icl_force_disable_sagv(struct intel_display *display, in icl_force_disable_sagv() argument
961 unsigned int qgv_points = icl_max_bw_qgv_point_mask(display, 0); in icl_force_disable_sagv()
962 unsigned int psf_points = icl_max_bw_psf_gv_point_mask(display); in icl_force_disable_sagv()
964 bw_state->qgv_points_mask = icl_prepare_qgv_points_mask(display, in icl_force_disable_sagv()
968 drm_dbg_kms(display->drm, "Forcing SAGV disable: mask 0x%x\n", in icl_force_disable_sagv()
971 icl_pcode_restrict_qgv_points(display, bw_state->qgv_points_mask); in icl_force_disable_sagv()
974 static int mtl_find_qgv_points(struct intel_display *display, in mtl_find_qgv_points() argument
980 unsigned int num_qgv_points = display->bw.max[0].num_qgv_points; in mtl_find_qgv_points()
994 if (!intel_can_enable_sagv(display, new_bw_state)) { in mtl_find_qgv_points()
996 drm_dbg_kms(display->drm, "No SAGV, use UINT_MAX as peak bw."); in mtl_find_qgv_points()
1006 tgl_max_bw_index(display, num_active_planes, i); in mtl_find_qgv_points()
1009 if (bw_index >= ARRAY_SIZE(display->bw.max)) in mtl_find_qgv_points()
1012 max_data_rate = display->bw.max[bw_index].deratedbw[i]; in mtl_find_qgv_points()
1019 qgv_peak_bw = display->bw.max[bw_index].peakbw[i]; in mtl_find_qgv_points()
1022 drm_dbg_kms(display->drm, "QGV point %d: max bw %d required %d qgv_peak_bw: %d\n", in mtl_find_qgv_points()
1026 drm_dbg_kms(display->drm, "Matching peaks QGV bw: %d for required data rate: %d\n", in mtl_find_qgv_points()
1030 * The display configuration cannot be supported if no QGV point in mtl_find_qgv_points()
1034 …drm_dbg_kms(display->drm, "No QGV points for bw %d for display configuration(%d active planes).\n", in mtl_find_qgv_points()
1045 static int icl_find_qgv_points(struct intel_display *display, in icl_find_qgv_points() argument
1051 unsigned int num_psf_gv_points = display->bw.max[0].num_psf_gv_points; in icl_find_qgv_points()
1052 unsigned int num_qgv_points = display->bw.max[0].num_qgv_points; in icl_find_qgv_points()
1063 unsigned int max_data_rate = icl_qgv_bw(display, in icl_find_qgv_points()
1068 drm_dbg_kms(display->drm, "QGV point %d: max bw %d required %d\n", in icl_find_qgv_points()
1073 unsigned int max_data_rate = adl_psf_bw(display, i); in icl_find_qgv_points()
1078 drm_dbg_kms(display->drm, "PSF GV point %d: max bw %d" in icl_find_qgv_points()
1089 drm_dbg_kms(display->drm, "No QGV points provide sufficient memory" in icl_find_qgv_points()
1090 " bandwidth %d for display configuration(%d active planes).\n", in icl_find_qgv_points()
1096 drm_dbg_kms(display->drm, "No PSF GV points provide sufficient memory" in icl_find_qgv_points()
1097 " bandwidth %d for display configuration(%d active planes).\n", in icl_find_qgv_points()
1107 if (!intel_can_enable_sagv(display, new_bw_state)) { in icl_find_qgv_points()
1108 qgv_points = icl_max_bw_qgv_point_mask(display, num_active_planes); in icl_find_qgv_points()
1109 drm_dbg_kms(display->drm, "No SAGV, using single QGV point mask 0x%x\n", in icl_find_qgv_points()
1117 new_bw_state->qgv_points_mask = icl_prepare_qgv_points_mask(display, in icl_find_qgv_points()
1133 static int intel_bw_check_qgv_points(struct intel_display *display, in intel_bw_check_qgv_points() argument
1137 unsigned int data_rate = intel_bw_data_rate(display, new_bw_state); in intel_bw_check_qgv_points()
1139 intel_bw_num_active_planes(display, new_bw_state); in intel_bw_check_qgv_points()
1143 if (DISPLAY_VER(display) >= 14) in intel_bw_check_qgv_points()
1144 return mtl_find_qgv_points(display, data_rate, num_active_planes, in intel_bw_check_qgv_points()
1147 return icl_find_qgv_points(display, data_rate, num_active_planes, in intel_bw_check_qgv_points()
1151 static bool intel_dbuf_bw_changed(struct intel_display *display, in intel_dbuf_bw_changed() argument
1157 for_each_dbuf_slice(display, slice) { in intel_dbuf_bw_changed()
1166 static bool intel_bw_state_changed(struct intel_display *display, in intel_bw_state_changed() argument
1172 for_each_pipe(display, pipe) { in intel_bw_state_changed()
1178 if (intel_dbuf_bw_changed(display, old_dbuf_bw, new_dbuf_bw)) in intel_bw_state_changed()
1181 if (intel_bw_crtc_min_cdclk(display, old_bw_state->data_rate[pipe]) != in intel_bw_state_changed()
1182 intel_bw_crtc_min_cdclk(display, new_bw_state->data_rate[pipe])) in intel_bw_state_changed()
1195 struct intel_display *display = to_intel_display(crtc); in skl_plane_calc_dbuf_bw() local
1196 unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(display, ddb); in skl_plane_calc_dbuf_bw()
1203 for_each_dbuf_slice_in_mask(display, slice, dbuf_mask) { in skl_plane_calc_dbuf_bw()
1212 struct intel_display *display = to_intel_display(crtc_state); in skl_crtc_calc_dbuf_bw() local
1233 if (DISPLAY_VER(display) < 11) in skl_crtc_calc_dbuf_bw()
1242 intel_bw_dbuf_min_cdclk(struct intel_display *display, in intel_bw_dbuf_min_cdclk() argument
1248 for_each_dbuf_slice(display, slice) { in intel_bw_dbuf_min_cdclk()
1257 for_each_pipe(display, pipe) { in intel_bw_dbuf_min_cdclk()
1271 int intel_bw_min_cdclk(struct intel_display *display, in intel_bw_min_cdclk() argument
1277 min_cdclk = intel_bw_dbuf_min_cdclk(display, bw_state); in intel_bw_min_cdclk()
1279 for_each_pipe(display, pipe) in intel_bw_min_cdclk()
1281 intel_bw_crtc_min_cdclk(display, in intel_bw_min_cdclk()
1290 struct intel_display *display = to_intel_display(state); in intel_bw_calc_min_cdclk() local
1300 if (DISPLAY_VER(display) < 9) in intel_bw_calc_min_cdclk()
1310 if (!intel_dbuf_bw_changed(display, &old_dbuf_bw, &new_dbuf_bw)) in intel_bw_calc_min_cdclk()
1325 if (intel_bw_state_changed(display, old_bw_state, new_bw_state)) { in intel_bw_calc_min_cdclk()
1331 old_min_cdclk = intel_bw_min_cdclk(display, old_bw_state); in intel_bw_calc_min_cdclk()
1332 new_min_cdclk = intel_bw_min_cdclk(display, new_bw_state); in intel_bw_calc_min_cdclk()
1340 * display blinking due to constant cdclk changes. in intel_bw_calc_min_cdclk()
1355 * display blinking due to constant cdclk changes. in intel_bw_calc_min_cdclk()
1360 drm_dbg_kms(display->drm, in intel_bw_calc_min_cdclk()
1370 struct intel_display *display = to_intel_display(state); in intel_bw_check_data_rate() local
1404 drm_dbg_kms(display->drm, in intel_bw_check_data_rate()
1416 struct intel_display *display = to_intel_display(state); in intel_bw_modeset_checks() local
1420 if (DISPLAY_VER(display) < 9) in intel_bw_modeset_checks()
1445 struct intel_display *display = to_intel_display(state); in intel_bw_check_sagv_mask() local
1474 if (intel_can_enable_sagv(display, new_bw_state) != in intel_bw_check_sagv_mask()
1475 intel_can_enable_sagv(display, old_bw_state)) { in intel_bw_check_sagv_mask()
1490 struct intel_display *display = to_intel_display(state); in intel_bw_atomic_check() local
1496 if (DISPLAY_VER(display) < 9) in intel_bw_atomic_check()
1510 if (DISPLAY_VER(display) < 11) in intel_bw_atomic_check()
1521 intel_can_enable_sagv(display, old_bw_state) != in intel_bw_atomic_check()
1522 intel_can_enable_sagv(display, new_bw_state)) in intel_bw_atomic_check()
1532 ret = intel_bw_check_qgv_points(display, old_bw_state, new_bw_state); in intel_bw_atomic_check()
1542 struct intel_display *display = to_intel_display(crtc_state); in intel_bw_crtc_update() local
1550 drm_dbg_kms(display->drm, "pipe %c data rate %u num active planes %u\n", in intel_bw_crtc_update()
1556 void intel_bw_update_hw_state(struct intel_display *display) in intel_bw_update_hw_state() argument
1559 to_intel_bw_state(display->bw.obj.state); in intel_bw_update_hw_state()
1562 if (DISPLAY_VER(display) < 9) in intel_bw_update_hw_state()
1568 for_each_intel_crtc(display->drm, crtc) { in intel_bw_update_hw_state()
1576 if (DISPLAY_VER(display) >= 11) in intel_bw_update_hw_state()
1588 struct intel_display *display = to_intel_display(crtc); in intel_bw_crtc_disable_noatomic() local
1590 to_intel_bw_state(display->bw.obj.state); in intel_bw_crtc_disable_noatomic()
1593 if (DISPLAY_VER(display) < 9) in intel_bw_crtc_disable_noatomic()
1624 int intel_bw_init(struct intel_display *display) in intel_bw_init() argument
1632 intel_atomic_global_obj_init(display, &display->bw.obj, in intel_bw_init()
1636 * Limit this only if we have SAGV. And for Display version 14 onwards in intel_bw_init()
1639 if (intel_has_sagv(display) && IS_DISPLAY_VER(display, 11, 13)) in intel_bw_init()
1640 icl_force_disable_sagv(display, state); in intel_bw_init()