Lines Matching +full:display +full:- +full:timings
28 #include <drm/display/drm_dsc_helper.h>
57 static int header_credits_available(struct intel_display *display,
60 return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
64 static int payload_credits_available(struct intel_display *display,
67 return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
71 static bool wait_for_header_credits(struct intel_display *display,
74 if (wait_for_us(header_credits_available(display, dsi_trans) >=
76 drm_err(display->drm, "DSI header credits not released\n");
83 static bool wait_for_payload_credits(struct intel_display *display,
86 if (wait_for_us(payload_credits_available(display, dsi_trans) >=
88 drm_err(display->drm, "DSI payload credits not released\n");
105 struct intel_display *display = to_intel_display(encoder);
113 for_each_dsi_port(port, intel_dsi->ports) {
115 wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT);
116 wait_for_payload_credits(display, dsi_trans, MAX_PLOAD_CREDIT);
120 for_each_dsi_port(port, intel_dsi->ports) {
121 dsi = intel_dsi->dsi_hosts[port]->device;
122 dsi->mode_flags |= MIPI_DSI_MODE_LPM;
123 dsi->channel = 0;
126 drm_err(display->drm,
131 for_each_dsi_port(port, intel_dsi->ports) {
133 wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT);
137 for_each_dsi_port(port, intel_dsi->ports) {
139 if (wait_for_us(!(intel_de_read(display, DSI_LP_MSG(dsi_trans)) &
141 drm_err(display->drm, "LPTX bit not cleared\n");
148 struct intel_dsi *intel_dsi = host->intel_dsi;
149 struct intel_display *display = to_intel_display(&intel_dsi->base);
150 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
151 const u8 *data = packet->payload;
152 u32 len = packet->payload_length;
157 drm_err(display->drm, "payload size exceeds max queue limit\n");
158 return -EINVAL;
164 if (!wait_for_payload_credits(display, dsi_trans, 1))
165 return -EBUSY;
167 for (j = 0; j < min_t(u32, len - i, 4); j++)
170 intel_de_write(display, DSI_CMD_TXPYLD(dsi_trans), tmp);
180 struct intel_dsi *intel_dsi = host->intel_dsi;
181 struct intel_display *display = to_intel_display(&intel_dsi->base);
182 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
185 if (!wait_for_header_credits(display, dsi_trans, 1))
186 return -EBUSY;
188 tmp = intel_de_read(display, DSI_CMD_TXHDR(dsi_trans));
190 if (packet->payload)
203 tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT);
204 tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT);
205 tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT);
206 tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT);
207 intel_de_write(display, DSI_CMD_TXHDR(dsi_trans), tmp);
214 struct intel_display *display = to_intel_display(crtc_state);
218 mode_flags = crtc_state->mode_flags;
232 intel_de_rmw(display, DSI_CMD_FRMCTL(port), 0,
238 struct intel_display *display = to_intel_display(encoder);
244 for_each_dsi_phy(phy, intel_dsi->phys) {
246 * Program voltage swing and pre-emphasis level values as per
252 tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
255 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
256 intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), mask, val);
262 tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));
265 intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);
266 intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), mask, val);
272 intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), mask, val);
276 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),
284 struct intel_display *display = to_intel_display(encoder);
290 if (DISPLAY_VER(display) >= 12) {
291 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
293 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe);
294 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe);
300 dss_ctl1 = intel_de_read(display, dss_ctl1_reg);
303 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
305 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
307 &pipe_config->hw.adjusted_mode;
308 u16 hactive = adjusted_mode->crtc_hdisplay;
312 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
315 drm_err(display->drm,
320 intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
327 intel_de_write(display, dss_ctl1_reg, dss_ctl1);
337 if (crtc_state->dsc.compression_enable)
338 bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);
340 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
342 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count);
348 struct intel_display *display = to_intel_display(encoder);
357 if (display->platform.alderlake_s || display->platform.alderlake_p) {
361 esc_clk_div_m_phy = (act_word_clk - 1) / 2;
366 for_each_dsi_port(port, intel_dsi->ports) {
367 intel_de_write(display, ICL_DSI_ESC_CLK_DIV(port),
369 intel_de_posting_read(display, ICL_DSI_ESC_CLK_DIV(port));
372 for_each_dsi_port(port, intel_dsi->ports) {
373 intel_de_write(display, ICL_DPHY_ESC_CLK_DIV(port),
375 intel_de_posting_read(display, ICL_DPHY_ESC_CLK_DIV(port));
378 if (display->platform.alderlake_s || display->platform.alderlake_p) {
379 for_each_dsi_port(port, intel_dsi->ports) {
380 intel_de_write(display, ADL_MIPIO_DW(port, 8),
382 intel_de_posting_read(display, ADL_MIPIO_DW(port, 8));
389 struct intel_display *display = to_intel_display(&intel_dsi->base);
392 for_each_dsi_port(port, intel_dsi->ports) {
393 drm_WARN_ON(display->drm, intel_dsi->io_wakeref[port]);
394 intel_dsi->io_wakeref[port] =
395 intel_display_power_get(display,
404 struct intel_display *display = to_intel_display(encoder);
408 for_each_dsi_port(port, intel_dsi->ports)
409 intel_de_rmw(display, ICL_DSI_IO_MODECTL(port),
417 struct intel_display *display = to_intel_display(encoder);
421 for_each_dsi_phy(phy, intel_dsi->phys)
422 intel_combo_phy_power_up_lanes(display, phy, true,
423 intel_dsi->lane_count, false);
428 struct intel_display *display = to_intel_display(encoder);
435 for_each_dsi_phy(phy, intel_dsi->phys) {
436 intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy),
439 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),
444 for_each_dsi_phy(phy, intel_dsi->phys) {
445 intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy),
447 tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));
450 intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);
453 if (display->platform.jasperlake || display->platform.elkhartlake ||
454 (DISPLAY_VER(display) >= 12)) {
455 intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy),
458 tmp = intel_de_read(display,
462 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy),
471 struct intel_display *display = to_intel_display(encoder);
477 for_each_dsi_phy(phy, intel_dsi->phys) {
478 tmp = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));
480 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), tmp);
481 intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0);
489 for_each_dsi_phy(phy, intel_dsi->phys)
490 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 0,
494 for_each_dsi_phy(phy, intel_dsi->phys) {
495 tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
497 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
498 intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0);
501 /* Program swing and de-emphasis */
505 for_each_dsi_phy(phy, intel_dsi->phys) {
506 tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
508 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
509 intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN);
515 struct intel_display *display = to_intel_display(encoder);
519 for_each_dsi_port(port, intel_dsi->ports) {
520 intel_de_rmw(display, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);
522 if (wait_for_us(!(intel_de_read(display, DDI_BUF_CTL(port)) &
525 drm_err(display->drm, "DDI port:%c buffer idle\n",
534 struct intel_display *display = to_intel_display(encoder);
539 /* Program DPHY clock lanes timings */
540 for_each_dsi_port(port, intel_dsi->ports)
541 intel_de_write(display, DPHY_CLK_TIMING_PARAM(port),
542 intel_dsi->dphy_reg);
544 /* Program DPHY data lanes timings */
545 for_each_dsi_port(port, intel_dsi->ports)
546 intel_de_write(display, DPHY_DATA_TIMING_PARAM(port),
547 intel_dsi->dphy_data_lane_reg);
555 if (DISPLAY_VER(display) == 11) {
557 for_each_dsi_port(port, intel_dsi->ports)
558 intel_de_rmw(display, DPHY_TA_TIMING_PARAM(port),
564 if (display->platform.jasperlake || display->platform.elkhartlake) {
565 for_each_dsi_phy(phy, intel_dsi->phys)
566 intel_de_rmw(display, ICL_DPHY_CHKN(phy),
575 struct intel_display *display = to_intel_display(encoder);
579 /* Program T-INIT master registers */
580 for_each_dsi_port(port, intel_dsi->ports)
581 intel_de_rmw(display, ICL_DSI_T_INIT_MASTER(port),
582 DSI_T_INIT_MASTER_MASK, intel_dsi->init_count);
584 /* shadow register inside display core */
585 for_each_dsi_port(port, intel_dsi->ports)
586 intel_de_write(display, DSI_CLK_TIMING_PARAM(port),
587 intel_dsi->dphy_reg);
589 /* shadow register inside display core */
590 for_each_dsi_port(port, intel_dsi->ports)
591 intel_de_write(display, DSI_DATA_TIMING_PARAM(port),
592 intel_dsi->dphy_data_lane_reg);
594 /* shadow register inside display core */
595 if (DISPLAY_VER(display) == 11) {
597 for_each_dsi_port(port, intel_dsi->ports) {
598 intel_de_rmw(display, DSI_TA_TIMING_PARAM(port),
608 struct intel_display *display = to_intel_display(encoder);
613 mutex_lock(&display->dpll.lock);
614 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
615 for_each_dsi_phy(phy, intel_dsi->phys)
618 intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp);
619 mutex_unlock(&display->dpll.lock);
624 struct intel_display *display = to_intel_display(encoder);
629 mutex_lock(&display->dpll.lock);
630 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
631 for_each_dsi_phy(phy, intel_dsi->phys)
634 intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp);
635 mutex_unlock(&display->dpll.lock);
640 struct intel_display *display = to_intel_display(encoder);
646 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
648 for_each_dsi_phy(phy, intel_dsi->phys) {
659 struct intel_display *display = to_intel_display(encoder);
661 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
665 mutex_lock(&display->dpll.lock);
667 val = intel_de_read(display, ICL_DPCLKA_CFGCR0);
668 for_each_dsi_phy(phy, intel_dsi->phys) {
670 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
672 intel_de_write(display, ICL_DPCLKA_CFGCR0, val);
674 for_each_dsi_phy(phy, intel_dsi->phys) {
677 intel_de_write(display, ICL_DPCLKA_CFGCR0, val);
679 intel_de_posting_read(display, ICL_DPCLKA_CFGCR0);
681 mutex_unlock(&display->dpll.lock);
688 struct intel_display *display = to_intel_display(encoder);
690 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
691 enum pipe pipe = crtc->pipe;
696 for_each_dsi_port(port, intel_dsi->ports) {
698 tmp = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
700 if (intel_dsi->eotp_pkt)
713 if (intel_dsi->clock_stop)
727 if (intel_dsi->bgr_enabled)
732 if (pipe_config->dsc.compression_enable) {
735 switch (intel_dsi->pixel_format) {
737 MISSING_CASE(intel_dsi->pixel_format);
754 if (DISPLAY_VER(display) >= 12) {
762 switch (intel_dsi->video_mode) {
764 MISSING_CASE(intel_dsi->video_mode);
787 intel_de_write(display, DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
791 if (intel_dsi->dual_link) {
792 for_each_dsi_port(port, intel_dsi->ports) {
794 intel_de_rmw(display,
795 TRANS_DDI_FUNC_CTL2(display, dsi_trans),
803 for_each_dsi_port(port, intel_dsi->ports) {
807 tmp = intel_de_read(display,
808 TRANS_DDI_FUNC_CTL(display, dsi_trans));
810 tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count);
834 intel_de_write(display,
835 TRANS_DDI_FUNC_CTL(display, dsi_trans), tmp);
839 for_each_dsi_port(port, intel_dsi->ports) {
841 if (wait_for_us((intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)) &
843 drm_err(display->drm, "DSI link not ready\n");
851 struct intel_display *display = to_intel_display(encoder);
854 &crtc_state->hw.adjusted_mode;
857 /* horizontal timings */
860 /* vertical timings */
865 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account
869 * non-compressed link speeds, and simplifies down to the ratio between
870 * compressed and non-compressed bpp.
872 if (crtc_state->dsc.compression_enable) {
873 mul = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);
874 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
877 hactive = adjusted_mode->crtc_hdisplay;
880 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
884 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
885 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
886 hsync_size = hsync_end - hsync_start;
887 hback_porch = (adjusted_mode->crtc_htotal -
888 adjusted_mode->crtc_hsync_end);
889 vactive = adjusted_mode->crtc_vdisplay;
892 vtotal = adjusted_mode->crtc_vtotal;
896 if (crtc_state->dsc.compression_enable)
897 bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);
899 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
902 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count);
905 vsync_start = adjusted_mode->crtc_vsync_start;
906 vsync_end = adjusted_mode->crtc_vsync_end;
907 vsync_shift = hsync_start - htotal / 2;
909 if (intel_dsi->dual_link) {
911 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
912 hactive += intel_dsi->pixel_overlap;
917 if (adjusted_mode->crtc_hdisplay < 256)
918 drm_err(display->drm, "hactive is less then 256 pixels\n");
921 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0)
922 drm_err(display->drm,
926 for_each_dsi_port(port, intel_dsi->ports) {
928 intel_de_write(display, TRANS_HTOTAL(display, dsi_trans),
929 HACTIVE(hactive - 1) | HTOTAL(htotal - 1));
934 if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) {
937 drm_err(display->drm,
942 drm_err(display->drm, "hback porch < 16 pixels\n");
944 if (intel_dsi->dual_link) {
949 for_each_dsi_port(port, intel_dsi->ports) {
951 intel_de_write(display,
952 TRANS_HSYNC(display, dsi_trans),
953 HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1));
958 for_each_dsi_port(port, intel_dsi->ports) {
962 * non-interlaced info from VBT is not saved inside
966 intel_de_write(display, TRANS_VTOTAL(display, dsi_trans),
967 VACTIVE(vactive - 1) | VTOTAL(vtotal - 1));
971 drm_err(display->drm, "Invalid vsync_end value\n");
974 drm_err(display->drm, "vsync_start less than vactive\n");
978 for_each_dsi_port(port, intel_dsi->ports) {
980 intel_de_write(display,
981 TRANS_VSYNC(display, dsi_trans),
982 VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1));
993 for_each_dsi_port(port, intel_dsi->ports) {
995 intel_de_write(display,
996 TRANS_VSYNCSHIFT(display, dsi_trans),
1007 if (DISPLAY_VER(display) >= 12) {
1008 for_each_dsi_port(port, intel_dsi->ports) {
1010 intel_de_write(display,
1011 TRANS_VBLANK(display, dsi_trans),
1012 VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1));
1019 struct intel_display *display = to_intel_display(encoder);
1024 for_each_dsi_port(port, intel_dsi->ports) {
1026 intel_de_rmw(display, TRANSCONF(display, dsi_trans), 0,
1030 if (intel_de_wait_for_set(display, TRANSCONF(display, dsi_trans),
1032 drm_err(display->drm,
1040 struct intel_display *display = to_intel_display(encoder);
1055 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
1057 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor);
1058 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor);
1060 for_each_dsi_port(port, intel_dsi->ports) {
1064 intel_de_rmw(display, DSI_HSTX_TO(dsi_trans),
1071 intel_de_rmw(display, DSI_LPRX_HOST_TO(dsi_trans),
1078 intel_de_rmw(display, DSI_TA_TO(dsi_trans),
1087 struct intel_display *display = to_intel_display(encoder);
1096 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B)))
1099 tmp = intel_de_read(display, UTIL_PIN_CTL);
1107 intel_de_write(display, UTIL_PIN_CTL, tmp);
1117 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */
1123 /* setup D-PHY timings */
1145 struct intel_display *display = to_intel_display(encoder);
1154 for_each_dsi_port(port, intel_dsi->ports) {
1161 tmp = intel_de_read(display, DSI_CMD_RXCTL(dsi_trans));
1165 dsi = intel_dsi->dsi_hosts[port]->device;
1168 drm_err(display->drm,
1188 msleep(intel_dsi->panel_on_delay);
1214 /* step6c: configure transcoder timings */
1228 struct intel_display *display = to_intel_display(encoder);
1230 if (DISPLAY_VER(display) == 11 && pipe == PIPE_B)
1231 intel_de_rmw(display, CHICKEN_PAR1_1,
1237 * Wa_16012360555:adl-p
1240 * PPI signaling between the Display engine and the DPHY.
1244 struct intel_display *display = to_intel_display(encoder);
1248 if (DISPLAY_VER(display) == 13) {
1249 for_each_dsi_port(port, intel_dsi->ports)
1250 intel_de_rmw(display, TGL_DSI_CHKN_REG(port),
1262 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1265 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true);
1267 /* Wa_16012360555:adl-p */
1284 struct intel_display *display = to_intel_display(encoder);
1289 for_each_dsi_port(port, intel_dsi->ports) {
1293 intel_de_rmw(display, TRANSCONF(display, dsi_trans),
1297 if (intel_de_wait_for_clear(display, TRANSCONF(display, dsi_trans),
1299 drm_err(display->drm,
1316 struct intel_display *display = to_intel_display(encoder);
1324 for_each_dsi_port(port, intel_dsi->ports)
1325 intel_de_rmw(display, DSI_CMD_FRMCTL(port),
1330 for_each_dsi_port(port, intel_dsi->ports) {
1332 tmp = intel_de_read(display, DSI_LP_MSG(dsi_trans));
1335 intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp);
1337 if (wait_for_us((intel_de_read(display, DSI_LP_MSG(dsi_trans)) &
1340 drm_err(display->drm, "DSI link not in ULPS\n");
1344 for_each_dsi_port(port, intel_dsi->ports) {
1346 intel_de_rmw(display,
1347 TRANS_DDI_FUNC_CTL(display, dsi_trans),
1352 if (intel_dsi->dual_link) {
1353 for_each_dsi_port(port, intel_dsi->ports) {
1355 intel_de_rmw(display,
1356 TRANS_DDI_FUNC_CTL2(display, dsi_trans),
1364 struct intel_display *display = to_intel_display(encoder);
1369 for_each_dsi_port(port, intel_dsi->ports) {
1370 intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
1372 if (wait_for_us((intel_de_read(display, DDI_BUF_CTL(port)) &
1375 drm_err(display->drm,
1384 struct intel_display *display = to_intel_display(encoder);
1388 for_each_dsi_port(port, intel_dsi->ports) {
1391 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]);
1392 intel_display_power_put(display,
1400 for_each_dsi_port(port, intel_dsi->ports)
1401 intel_de_rmw(display, ICL_DSI_IO_MODECTL(port),
1423 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1431 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false);
1452 msleep(intel_dsi->panel_off_delay);
1455 intel_dsi->panel_power_off_time = ktime_get_boottime();
1461 struct intel_display *display = to_intel_display(connector->dev);
1464 status = intel_cpu_transcoder_mode_valid(display, mode);
1477 &pipe_config->hw.adjusted_mode;
1479 if (pipe_config->dsc.compressed_bpp_x16) {
1480 int div = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16);
1481 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1483 adjusted_mode->crtc_htotal =
1484 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
1485 adjusted_mode->crtc_hsync_start =
1486 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
1487 adjusted_mode->crtc_hsync_end =
1488 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
1491 if (intel_dsi->dual_link) {
1492 adjusted_mode->crtc_hdisplay *= 2;
1493 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1494 adjusted_mode->crtc_hdisplay -=
1495 intel_dsi->pixel_overlap;
1496 adjusted_mode->crtc_htotal *= 2;
1498 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1499 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1501 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
1502 if (intel_dsi->dual_link) {
1503 adjusted_mode->crtc_hsync_start *= 2;
1504 adjusted_mode->crtc_hsync_end *= 2;
1507 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1508 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1513 struct intel_display *display = to_intel_display(&intel_dsi->base);
1517 if (intel_dsi->ports == BIT(PORT_B))
1522 val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
1529 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A)))
1530 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 |
1532 else if (intel_dsi->ports == BIT(PORT_B))
1533 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1;
1535 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0;
1541 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1546 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
1547 if (intel_dsi->dual_link)
1548 pipe_config->hw.adjusted_mode.crtc_clock *= 2;
1551 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1552 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc);
1559 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
1565 struct intel_display *display = to_intel_display(encoder);
1572 intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1573 pipe = intel_crtc->pipe;
1576 if (DISPLAY_VER(display) == 11 && pipe == PIPE_B &&
1577 !(intel_de_read(display, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))
1578 drm_dbg_kms(display->drm,
1580 encoder->base.base.id,
1581 encoder->base.name);
1587 struct intel_display *display = to_intel_display(encoder);
1588 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1589 int dsc_max_bpc = DISPLAY_VER(display) >= 12 ? 12 : 10;
1597 if (crtc_state->pipe_bpp < 8 * 3)
1598 return -EINVAL;
1601 if (crtc_state->dsc.slice_count > 1)
1602 crtc_state->dsc.num_streams = 2;
1604 crtc_state->dsc.num_streams = 1;
1607 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1609 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1616 drm_WARN_ON(display->drm, vdsc_cfg->vbr_enable);
1617 drm_WARN_ON(display->drm, vdsc_cfg->simple_422);
1618 drm_WARN_ON(display->drm,
1619 vdsc_cfg->pic_width % vdsc_cfg->slice_width);
1620 drm_WARN_ON(display->drm, vdsc_cfg->slice_height < 8);
1621 drm_WARN_ON(display->drm,
1622 vdsc_cfg->pic_height % vdsc_cfg->slice_height);
1628 crtc_state->dsc.compression_enable = true;
1637 struct intel_display *display = to_intel_display(encoder);
1639 struct intel_connector *intel_connector = intel_dsi->attached_connector;
1641 &pipe_config->hw.adjusted_mode;
1644 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
1645 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1655 adjusted_mode->flags = 0;
1658 if (intel_dsi->ports == BIT(PORT_B))
1659 pipe_config->cpu_transcoder = TRANSCODER_DSI_1;
1661 pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
1663 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
1664 pipe_config->pipe_bpp = 24;
1666 pipe_config->pipe_bpp = 18;
1668 pipe_config->clock_set = true;
1671 drm_dbg_kms(display->drm, "Attempting to use DSC failed\n");
1673 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
1695 struct intel_display *display = to_intel_display(encoder);
1703 wakeref = intel_display_power_get_if_enabled(display,
1704 encoder->power_domain);
1708 for_each_dsi_port(port, intel_dsi->ports) {
1710 tmp = intel_de_read(display,
1711 TRANS_DDI_FUNC_CTL(display, dsi_trans));
1726 drm_err(display->drm, "Invalid PIPE input\n");
1730 tmp = intel_de_read(display, TRANSCONF(display, dsi_trans));
1734 intel_display_power_put(display, encoder->power_domain, wakeref);
1741 if (crtc_state->dsc.compression_enable) {
1742 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n");
1743 crtc_state->uapi.mode_changed = true;
1802 if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1806 if (mipi_dsi_packet_format_is_long(msg->type)) {
1832 struct intel_connector *connector = intel_dsi->attached_connector;
1833 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
1842 * units of 1/4 escape clocks, and all the other timings parameters in
1845 tclk_prepare_esc_clk = DIV_ROUND_UP(mipi_config->tclk_prepare * 4, tlpx_ns);
1848 tclk_zero_esc_clk = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
1849 mipi_config->tclk_prepare, tlpx_ns);
1852 tclk_pre_esc_clk = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
1855 ths_prepare_esc_clk = DIV_ROUND_UP(mipi_config->ths_prepare * 4, tlpx_ns);
1858 ths_zero_esc_clk = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
1859 mipi_config->ths_prepare, tlpx_ns);
1862 ths_exit_esc_clk = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
1865 /* clock lane dphy timings */
1866 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
1873 /* data lanes dphy timings */
1874 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE |
1889 intel_attach_scaling_mode_property(&connector->base);
1891 drm_connector_set_panel_orientation_with_quirk(&connector->base,
1893 fixed_mode->hdisplay,
1894 fixed_mode->vdisplay);
1897 void icl_dsi_init(struct intel_display *display,
1920 encoder = &intel_dsi->base;
1921 intel_dsi->attached_connector = intel_connector;
1922 connector = &intel_connector->base;
1924 encoder->devdata = devdata;
1927 drm_encoder_init(display->drm, &encoder->base,
1931 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable;
1932 encoder->pre_enable = gen11_dsi_pre_enable;
1933 encoder->enable = gen11_dsi_enable;
1934 encoder->disable = gen11_dsi_disable;
1935 encoder->post_disable = gen11_dsi_post_disable;
1936 encoder->port = port;
1937 encoder->get_config = gen11_dsi_get_config;
1938 encoder->sync_state = gen11_dsi_sync_state;
1939 encoder->update_pipe = intel_backlight_update;
1940 encoder->compute_config = gen11_dsi_compute_config;
1941 encoder->get_hw_state = gen11_dsi_get_hw_state;
1942 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check;
1943 encoder->type = INTEL_OUTPUT_DSI;
1944 encoder->cloneable = 0;
1945 encoder->pipe_mask = ~0;
1946 encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1947 encoder->get_power_domains = gen11_dsi_get_power_domains;
1948 encoder->disable_clock = gen11_dsi_gate_clocks;
1949 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled;
1950 encoder->shutdown = intel_dsi_shutdown;
1953 drm_connector_init(display->drm, connector,
1957 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1958 intel_connector->get_hw_state = intel_connector_get_hw_state;
1963 intel_dsi->panel_power_off_time = ktime_get_boottime();
1965 intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata, NULL);
1967 mutex_lock(&display->drm->mode_config.mutex);
1969 mutex_unlock(&display->drm->mode_config.mutex);
1972 drm_err(display->drm, "DSI fixed mode info missing\n");
1980 if (intel_connector->panel.vbt.dsi.config->dual_link)
1981 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
1983 intel_dsi->ports = BIT(port);
1985 if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
1986 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports;
1988 if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
1989 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports;
1991 for_each_dsi_port(port, intel_dsi->ports) {
1998 intel_dsi->dsi_hosts[port] = host;
2002 drm_dbg_kms(display->drm, "no device found\n");
2013 drm_encoder_cleanup(&encoder->base);