Lines Matching defs:latency

91 		const struct cxsr_latency *latency = &cxsr_latency_table[i];
94 		if (is_desktop == latency->is_desktop &&
95 		    i915->is_ddr3 == latency->is_ddr3 &&
96 		    DIV_ROUND_CLOSEST(i915->fsb_freq, 1000) == latency->fsb_freq &&
97 		    DIV_ROUND_CLOSEST(i915->mem_freq, 1000) == latency->mem_freq)
98 			return latency;
102 		    "Could not find CxSR latency for DDR%s, FSB %u kHz, MEM %u kHz\n",
268  * platforms but not overly aggressive on lower latency configs.
447  * @latency: Memory wakeup latency in 0.1us units
478 				     unsigned int latency)
482 	ret = mul_u32_u32(pixel_rate, cpp * latency);
494  * @latency: Memory wakeup latency in 0.1us units
522 				     unsigned int latency)
533 	ret = (latency * pixel_rate) / (htotal * 10000);
546  * @latency_ns: memory latency for the platform
569 	 * latency values.
571 	 * latency is usually a few thousand
648 	const struct cxsr_latency *latency;
652 	latency = pnv_get_cxsr_latency(display);
653 	if (!latency) {
670 					cpp, latency->display_sr);
681 					4, latency->cursor_sr);
689 					cpp, latency->display_hpll_disable);
697 					4, latency->cursor_hpll_disable);
967 	unsigned int latency = display->wm.pri_latency[level] * 10;
970 	if (latency == 0)
994 		wm = intel_wm_method2(pixel_rate, htotal, width, cpp, latency);
997 		wm = intel_wm_method1(pixel_rate, cpp, latency);
1001 		small = intel_wm_method1(pixel_rate, cpp, latency);
1002 		large = intel_wm_method2(pixel_rate, htotal, width, cpp, latency);
1471 /* latency must be in 0.1us units. */
1476 				   unsigned int latency)
1481 			       width, cpp, latency);
2135 		/* self-refresh has much higher latency */
2309 		/* self-refresh has much higher latency */
2383 /* latency must be in 0.1us units. */
2386 				   unsigned int latency)
2390 	ret = intel_wm_method1(pixel_rate, cpp, latency);
2396 /* latency must be in 0.1us units. */
2401 				   unsigned int latency)
2406 			       width, cpp, latency);
2714 	/* WM1+ latency values stored in 0.5us units */
2778 	/* ILK primary LP0 latency is 700 ns */
2786 	/* ILK sprite LP0 latency is 1300 ns */
2793 	/* ILK cursor LP0 latency is 1300 ns */
2817 	 * The BIOS provided WM memory latency values are often
2828 		    "WM latency values increased to avoid potential underruns\n");
3158 /* The value we need to program into the WM_LPx latency field */