Lines Matching refs:plane
29 /* Primary plane formats for gen <= 3 */
37 /* Primary plane formats for ivb (no fp16 due to hw issue) */
47 /* Primary plane formats for gen >= 4, except ivb */
58 /* Primary plane formats for vlv/chv */
142 static bool i9xx_plane_has_windowing(struct intel_plane *plane)
144 struct intel_display *display = to_intel_display(plane);
145 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
233 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
253 "[PLANE:%d:%s] plane too wide (%d) for 64bpp\n",
254 plane->base.base.id, plane->base.name, src_w);
267 * When using an X-tiled surface the plane starts to
278 unsigned int alignment = plane->min_alignment(plane, fb, 0);
285 plane->base.base.id, plane->base.name);
333 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
343 i9xx_plane_has_windowing(plane));
390 * of cdclk when the sprite plane is enabled on the
429 struct intel_plane *plane,
433 struct intel_display *display = to_intel_display(plane);
434 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
458 struct intel_plane *plane,
462 struct intel_display *display = to_intel_display(plane);
463 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
471 if (plane->need_async_flip_toggle_wa &&
472 crtc_state->async_flip_planes & BIT(plane->id))
507 * The control register self-arms if the plane was previously
508 * disabled. Try to make the plane enable atomic by writing
522 struct intel_plane *plane,
532 i9xx_plane_update_noarm(dsb, plane, crtc_state, plane_state);
533 i9xx_plane_update_arm(dsb, plane, crtc_state, plane_state);
537 struct intel_plane *plane,
540 struct intel_display *display = to_intel_display(plane);
541 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
547 * well, so we must configure them even if the plane
565 struct intel_plane *plane,
568 struct intel_display *display = to_intel_display(plane);
569 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
577 struct intel_plane *plane,
580 struct intel_display *display = to_intel_display(plane);
581 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
588 struct intel_plane *plane,
591 struct intel_display *display = to_intel_display(plane);
592 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
600 struct intel_plane *plane,
605 struct intel_display *display = to_intel_display(plane);
608 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
621 struct intel_plane *plane,
626 struct intel_display *display = to_intel_display(plane);
628 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
635 bdw_primary_enable_flip_done(struct intel_plane *plane)
637 struct intel_display *display = to_intel_display(plane);
638 enum pipe pipe = plane->pipe;
646 bdw_primary_disable_flip_done(struct intel_plane *plane)
648 struct intel_display *display = to_intel_display(plane);
649 enum pipe pipe = plane->pipe;
657 ivb_primary_enable_flip_done(struct intel_plane *plane)
659 struct intel_display *display = to_intel_display(plane);
662 ilk_enable_display_irq(display, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
667 ivb_primary_disable_flip_done(struct intel_plane *plane)
669 struct intel_display *display = to_intel_display(plane);
672 ilk_disable_display_irq(display, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
677 ilk_primary_enable_flip_done(struct intel_plane *plane)
679 struct intel_display *display = to_intel_display(plane);
682 ilk_enable_display_irq(display, DE_PLANE_FLIP_DONE(plane->i9xx_plane));
687 ilk_primary_disable_flip_done(struct intel_plane *plane)
689 struct intel_display *display = to_intel_display(plane);
692 ilk_disable_display_irq(display, DE_PLANE_FLIP_DONE(plane->i9xx_plane));
697 vlv_primary_enable_flip_done(struct intel_plane *plane)
699 struct intel_display *display = to_intel_display(plane);
700 enum pipe pipe = plane->pipe;
708 vlv_primary_disable_flip_done(struct intel_plane *plane)
710 struct intel_display *display = to_intel_display(plane);
711 enum pipe pipe = plane->pipe;
723 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
726 struct intel_display *display = to_intel_display(plane);
728 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
738 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
748 *pipe = plane->pipe;
758 hsw_primary_max_stride(struct intel_plane *plane,
770 ilk_primary_max_stride(struct intel_plane *plane,
785 i965_plane_max_stride(struct intel_plane *plane,
800 i915_plane_max_stride(struct intel_plane *plane,
811 i8xx_plane_max_stride(struct intel_plane *plane,
815 if (plane->i9xx_plane == PLANE_C)
821 unsigned int vlv_plane_min_alignment(struct intel_plane *plane,
825 struct intel_display *display = to_intel_display(plane);
827 if (intel_plane_can_async_flip(plane, fb->format->format, fb->modifier))
845 static unsigned int g4x_primary_min_alignment(struct intel_plane *plane,
849 struct intel_display *display = to_intel_display(plane);
851 if (intel_plane_can_async_flip(plane, fb->format->format, fb->modifier))
867 static unsigned int i965_plane_min_alignment(struct intel_plane *plane,
882 static unsigned int i9xx_plane_min_alignment(struct intel_plane *plane,
909 static void i9xx_disable_tiling(struct intel_plane *plane)
911 struct intel_display *display = to_intel_display(plane);
912 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
933 struct intel_plane *plane;
941 plane = intel_plane_alloc();
942 if (IS_ERR(plane))
943 return plane;
945 plane->pipe = pipe;
947 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
948 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
952 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
954 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
955 plane->id = PLANE_PRIMARY;
956 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
958 intel_fbc_add_plane(i9xx_plane_fbc(display, plane->i9xx_plane), plane);
966 * "Workaround : When using the 64-bit format, the plane
970 * multiply the plane output by four."
972 * There is no dedicated plane gamma for the primary plane,
995 plane->min_cdclk = vlv_plane_min_cdclk;
997 plane->min_cdclk = hsw_plane_min_cdclk;
999 plane->min_cdclk = ivb_plane_min_cdclk;
1001 plane->min_cdclk = i9xx_plane_min_cdclk;
1005 plane->max_stride = i965_plane_max_stride;
1007 plane->max_stride = i915_plane_max_stride;
1009 plane->max_stride = i8xx_plane_max_stride;
1012 plane->max_stride = hsw_primary_max_stride;
1014 plane->max_stride = ilk_primary_max_stride;
1018 plane->min_alignment = vlv_plane_min_alignment;
1020 plane->min_alignment = g4x_primary_min_alignment;
1022 plane->min_alignment = i965_plane_min_alignment;
1024 plane->min_alignment = i9xx_plane_min_alignment;
1028 plane->vtd_guard = 128;
1031 plane->update_arm = i830_plane_update_arm;
1033 plane->update_noarm = i9xx_plane_update_noarm;
1034 plane->update_arm = i9xx_plane_update_arm;
1036 plane->disable_arm = i9xx_plane_disable_arm;
1037 plane->get_hw_state = i9xx_plane_get_hw_state;
1038 plane->check_plane = i9xx_plane_check;
1041 plane->capture_error = g4x_primary_capture_error;
1043 plane->capture_error = i965_plane_capture_error;
1045 plane->capture_error = i8xx_plane_capture_error;
1049 plane->async_flip = vlv_primary_async_flip;
1050 plane->enable_flip_done = vlv_primary_enable_flip_done;
1051 plane->disable_flip_done = vlv_primary_disable_flip_done;
1052 plane->can_async_flip = i9xx_plane_can_async_flip;
1054 plane->need_async_flip_toggle_wa = true;
1055 plane->async_flip = g4x_primary_async_flip;
1056 plane->enable_flip_done = bdw_primary_enable_flip_done;
1057 plane->disable_flip_done = bdw_primary_disable_flip_done;
1058 plane->can_async_flip = i9xx_plane_can_async_flip;
1060 plane->async_flip = g4x_primary_async_flip;
1061 plane->enable_flip_done = ivb_primary_enable_flip_done;
1062 plane->disable_flip_done = ivb_primary_disable_flip_done;
1063 plane->can_async_flip = i9xx_plane_can_async_flip;
1065 plane->async_flip = g4x_primary_async_flip;
1066 plane->enable_flip_done = ilk_primary_enable_flip_done;
1067 plane->disable_flip_done = ilk_primary_disable_flip_done;
1068 plane->can_async_flip = i9xx_plane_can_async_flip;
1072 plane->disable_tiling = i9xx_disable_tiling;
1077 ret = drm_universal_plane_init(display->drm, &plane->base,
1084 ret = drm_universal_plane_init(display->drm, &plane->base,
1089 "plane %c",
1090 plane_name(plane->i9xx_plane));
1109 drm_plane_create_rotation_property(&plane->base,
1114 drm_plane_create_zpos_immutable_property(&plane->base, zpos);
1116 intel_plane_helper_add(plane);
1118 return plane;
1121 intel_plane_free(plane);
1164 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1165 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
1173 if (!plane->get_hw_state(plane, &pipe))
1242 plane->base.base.id, plane->base.name,
1253 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1255 to_intel_plane_state(plane->base.state);
1256 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
1266 * part of ggtt, make the plane aware of that.