24 	 * We can only enable IPS after we enable a plane and wait for a vblank  in hsw_ips_enable()
33 	if (i915->display.ips.false_color)  in hsw_ips_enable()
42 		 * value in IPS_CTL bit 31 after enabling IPS through the  in hsw_ips_enable()
57 				"Timed out waiting for IPS enable\n");  in hsw_ips_enable()
74 		 * Wait for PCODE to finish disabling IPS. The BSpec specified  in hsw_ips_disable()
80 				"Timed out waiting for IPS disable\n");  in hsw_ips_disable()
109 	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.  in hsw_ips_need_disable()
111 	 * Disable IPS before we program the LUT.  in hsw_ips_need_disable()
150 	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.  in hsw_ips_need_enable()
152 	 * Re-enable IPS after the LUT has been programmed.  in hsw_ips_need_enable()
160 	 * We can't read out IPS on broadwell, assume the worst and  in hsw_ips_need_enable()
161 	 * forcibly enable IPS on the first fastset.  in hsw_ips_need_enable()
181 /* IPS only exists on ULT machines and is tied to pipe A. */
192 	/* IPS only exists on ULT machines and is tied to pipe A. */  in hsw_crtc_state_ips_capable()
207 	 * Should measure whether using a lower cdclk w/o IPS  in hsw_crtc_state_ips_capable()
229 	 * When IPS gets enabled, the pipe CRC changes. Since IPS gets  in hsw_ips_compute_config()
237 	/* IPS should be fine as long as at least one plane is enabled. */  in hsw_ips_compute_config()
248 		/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */  in hsw_ips_compute_config()
270 		 * We cannot readout IPS state on broadwell, set to  in hsw_ips_get_config()
283 	*val = i915->display.ips.false_color;  in hsw_ips_debugfs_false_color_get()
299 	i915->display.ips.false_color = val;  in hsw_ips_debugfs_false_color_set()