Lines Matching defs:pipe_config
60 struct intel_crtc_state *pipe_config)
83 if (pipe_config->port_clock == divisor[i].dot) {
84 pipe_config->dpll = divisor[i];
85 pipe_config->clock_set = true;
93 const struct intel_crtc_state *pipe_config)
99 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
100 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
103 pipe_config->port_clock,
104 pipe_config->lane_count);
129 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
149 pipe_config->enhanced_framing ?
152 if (display->platform.g4x && pipe_config->limited_color_range)
161 if (pipe_config->enhanced_framing)
196 const struct intel_crtc_state *pipe_config)
199 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
201 assert_transcoder_disabled(display, pipe_config->cpu_transcoder);
206 pipe_config->port_clock);
210 if (pipe_config->port_clock == 162000)
338 struct intel_crtc_state *pipe_config)
345 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
348 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
350 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
354 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
361 pipe_config->enhanced_framing = true;
374 pipe_config->enhanced_framing = true;
387 pipe_config->hw.adjusted_mode.flags |= flags;
390 pipe_config->limited_color_range = true;
392 pipe_config->lane_count =
395 g4x_dp_get_m_n(pipe_config);
399 pipe_config->port_clock = 162000;
401 pipe_config->port_clock = 270000;
404 pipe_config->hw.adjusted_mode.crtc_clock =
405 intel_dotclock_calculate(pipe_config->port_clock,
406 &pipe_config->dp_m_n);
409 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp);
411 intel_audio_codec_get_config(encoder, pipe_config);
676 const struct intel_crtc_state *pipe_config,
689 vlv_pps_port_enable_unlocked(encoder, pipe_config);
691 intel_dp_enable_port(intel_dp, pipe_config);
702 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
708 intel_dp_configure_protocol_converter(intel_dp, pipe_config);
710 intel_dp_pcon_dsc_configure(intel_dp, pipe_config);
711 intel_dp_start_link_train(state, intel_dp, pipe_config);
712 intel_dp_stop_link_train(intel_dp, pipe_config);
717 const struct intel_crtc_state *pipe_config,
720 intel_enable_dp(state, encoder, pipe_config, conn_state);
721 intel_edp_backlight_on(pipe_config, conn_state);
726 const struct intel_crtc_state *pipe_config,
729 intel_edp_backlight_on(pipe_config, conn_state);
734 const struct intel_crtc_state *pipe_config,
740 intel_dp_prepare(encoder, pipe_config);
744 ilk_edp_pll_on(intel_dp, pipe_config);
749 const struct intel_crtc_state *pipe_config,
752 vlv_phy_pre_encoder_enable(encoder, pipe_config);
754 intel_enable_dp(state, encoder, pipe_config, conn_state);
759 const struct intel_crtc_state *pipe_config,
762 intel_dp_prepare(encoder, pipe_config);
764 vlv_phy_pre_pll_enable(encoder, pipe_config);
769 const struct intel_crtc_state *pipe_config,
772 chv_phy_pre_encoder_enable(encoder, pipe_config);
774 intel_enable_dp(state, encoder, pipe_config, conn_state);
782 const struct intel_crtc_state *pipe_config,
785 intel_dp_prepare(encoder, pipe_config);
787 chv_phy_pre_pll_enable(encoder, pipe_config);