Lines Matching +full:write +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <sound/hdmi-codec.h>
26 #include <media/cec-notifier.h>
100 * write a given register, we need to make sure CURPAGE register is set
105 #define REG2ADDR(reg) ((reg) & 0xff)
106 #define REG2PAGE(reg) (((reg) >> 8) & 0xff)
108 #define REG_CURPAGE 0xff /* write */
112 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */
113 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
114 # define MAIN_CNTRL0_SR (1 << 0)
120 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */
121 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
122 # define SOFTRESET_AUDIO (1 << 0)
124 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
125 #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
126 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
127 # define I2C_MASTER_DIS_MM (1 << 0)
130 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
131 # define FEAT_POWERDOWN_PREFILT BIT(0)
134 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
135 #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
136 #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
138 #define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
139 #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
140 #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
141 #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
142 #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
143 #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
147 # define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
148 #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
152 # define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
153 #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
157 # define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
158 #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
159 # define VIP_CNTRL_3_X_TGL (1 << 0)
167 #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
168 # define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
174 #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
175 # define VIP_CNTRL_5_CKCASE (1 << 0)
177 #define REG_MUX_AP REG(0x00, 0x26) /* read/write */
178 # define MUX_AP_SELECT_I2S 0x64
179 # define MUX_AP_SELECT_SPDIF 0x40
180 #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
181 #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
182 # define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
184 #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
185 #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
186 #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
187 #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
188 #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
189 #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
190 #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
191 #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
192 #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
193 #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
194 #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
195 #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
196 #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
197 #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
198 #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
199 #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
200 #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
201 #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
202 #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
203 #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
204 #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
205 #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
206 #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
207 #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
208 #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
209 #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
210 #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
211 #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
212 #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
213 #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
214 #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
215 #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
216 #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
217 #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
218 #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
219 #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
220 #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
221 #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
222 #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
223 #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
224 #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
225 #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
226 # define TBG_CNTRL_0_TOP_TGL (1 << 0)
233 #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
234 # define TBG_CNTRL_1_H_TGL (1 << 0)
241 #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
242 #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
246 # define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
247 #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
248 # define HVF_CNTRL_1_FOR (1 << 0)
253 #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
255 #define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
256 # define I2S_FORMAT_PHILIPS (0 << 0)
257 # define I2S_FORMAT_LEFT_J (2 << 0)
258 # define I2S_FORMAT_RIGHT_J (3 << 0)
259 #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
260 # define AIP_CLKSEL_AIP_SPDIF (0 << 3)
262 # define AIP_CLKSEL_FS_ACLK (0 << 0)
263 # define AIP_CLKSEL_FS_MCLK (1 << 0)
264 # define AIP_CLKSEL_FS_FS64SPDIF (2 << 0)
267 #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
268 # define PLL_SERIAL_1_SRL_FDN (1 << 0)
271 #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
272 # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
273 # define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
274 #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
275 # define PLL_SERIAL_3_SRL_CCIR (1 << 0)
278 #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
279 #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
280 #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
281 #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
282 #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
283 #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
284 #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
285 #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
286 #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
287 # define AUDIO_DIV_SERCLK_1 0
293 #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
294 # define SEL_CLK_SEL_CLK1 (1 << 0)
297 #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
301 #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
303 #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
304 #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
305 #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
306 #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
307 #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
311 #define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
312 #define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
313 #define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
314 #define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
315 #define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
319 #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
320 # define AIP_CNTRL_0_RST_FIFO (1 << 0)
325 #define REG_CA_I2S REG(0x11, 0x01) /* read/write */
326 # define CA_I2S_CA_I2S(x) (((x) & 31) << 0)
328 #define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
329 #define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
330 #define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
331 #define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
332 #define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
333 #define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
334 #define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
335 #define REG_CTS_N REG(0x11, 0x0c) /* read/write */
336 # define CTS_N_K(x) (((x) & 7) << 0)
338 #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
339 # define ENC_CNTRL_RST_ENC (1 << 0)
342 #define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
343 # define DIP_FLAGS_ACR (1 << 0)
345 #define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
351 #define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
355 #define REG_TX3 REG(0x12, 0x9a) /* read/write */
356 #define REG_TX4 REG(0x12, 0x9b) /* read/write */
358 #define REG_TX33 REG(0x12, 0xb8) /* read/write */
368 #define REG_CEC_INTSTATUS 0xee /* read */
369 # define CEC_INTSTATUS_CEC (1 << 0)
371 #define REG_CEC_CAL_XOSC_CTRL1 0xf2
372 # define CEC_CAL_XOSC_CTRL1_ENA_CAL BIT(0)
373 #define REG_CEC_DES_FREQ2 0xf5
375 #define REG_CEC_CLK 0xf6
376 # define CEC_CLK_FRO 0x11
377 #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
381 # define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
382 #define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
383 #define REG_CEC_RXSHPDINT 0xfd /* read */
384 # define CEC_RXSHPDINT_RXSENS BIT(0)
386 #define REG_CEC_RXSHPDLEV 0xfe /* read */
387 # define CEC_RXSHPDLEV_RXSENS (1 << 0)
390 #define REG_CEC_ENAMODS 0xff /* read/write */
396 # define CEC_ENAMODS_EN_CEC (1 << 0)
400 #define TDA9989N2 0x0101
401 #define TDA19989 0x0201
402 #define TDA19989N2 0x0202
403 #define TDA19988 0x0301
410 .addr = priv->cec_addr, in cec_write()
416 ret = i2c_transfer(priv->hdmi->adapter, &msg, 1); in cec_write()
417 if (ret < 0) in cec_write()
418 dev_err(&priv->hdmi->dev, "Error %d writing to cec:0x%x\n", in cec_write()
428 .addr = priv->cec_addr, in cec_read()
432 .addr = priv->cec_addr, in cec_read()
440 ret = i2c_transfer(priv->hdmi->adapter, msg, ARRAY_SIZE(msg)); in cec_read()
441 if (ret < 0) { in cec_read()
442 dev_err(&priv->hdmi->dev, "Error %d reading from cec:0x%x\n", in cec_read()
444 val = 0; in cec_read()
454 if (val < 0) in cec_enamods()
470 cec_write(priv, 0xf3, 0xc0); in tda998x_cec_set_calibration()
471 cec_write(priv, 0xf4, 0xd4); in tda998x_cec_set_calibration()
485 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1, 0); in tda998x_cec_set_calibration()
495 struct gpio_desc *calib = priv->calib; in tda998x_cec_calibration()
497 mutex_lock(&priv->edid_mutex); in tda998x_cec_calibration()
498 if (priv->hdmi->irq > 0) in tda998x_cec_calibration()
499 disable_irq(priv->hdmi->irq); in tda998x_cec_calibration()
504 gpiod_set_value(calib, 0); in tda998x_cec_calibration()
511 if (priv->hdmi->irq > 0) in tda998x_cec_calibration()
512 enable_irq(priv->hdmi->irq); in tda998x_cec_calibration()
513 mutex_unlock(&priv->edid_mutex); in tda998x_cec_calibration()
521 calib = gpiod_get(&priv->hdmi->dev, "nxp,calib", GPIOD_ASIS); in tda998x_cec_hook_init()
523 dev_warn(&priv->hdmi->dev, "failed to get calibration gpio: %ld\n", in tda998x_cec_hook_init()
528 priv->calib = calib; in tda998x_cec_hook_init()
530 return 0; in tda998x_cec_hook_init()
537 gpiod_put(priv->calib); in tda998x_cec_hook_exit()
538 priv->calib = NULL; in tda998x_cec_hook_exit()
548 return 0; in tda998x_cec_hook_open()
561 if (REG2PAGE(reg) != priv->current_page) { in set_page()
562 struct i2c_client *client = priv->hdmi; in set_page()
567 if (ret < 0) { in set_page()
568 dev_err(&client->dev, "%s %04x err %d\n", __func__, in set_page()
573 priv->current_page = REG2PAGE(reg); in set_page()
575 return 0; in set_page()
581 struct i2c_client *client = priv->hdmi; in reg_read_range()
585 mutex_lock(&priv->mutex); in reg_read_range()
587 if (ret < 0) in reg_read_range()
591 if (ret < 0) in reg_read_range()
595 if (ret < 0) in reg_read_range()
601 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg); in reg_read_range()
603 mutex_unlock(&priv->mutex); in reg_read_range()
612 struct i2c_client *client = priv->hdmi; in reg_write_range()
618 dev_err(&client->dev, "Fixed write buffer too small (%d)\n", in reg_write_range()
623 buf[0] = REG2ADDR(reg); in reg_write_range()
626 mutex_lock(&priv->mutex); in reg_write_range()
628 if (ret < 0) in reg_write_range()
632 if (ret < 0) in reg_write_range()
633 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); in reg_write_range()
635 mutex_unlock(&priv->mutex); in reg_write_range()
641 u8 val = 0; in reg_read()
645 if (ret < 0) in reg_read()
653 struct i2c_client *client = priv->hdmi; in reg_write()
657 mutex_lock(&priv->mutex); in reg_write()
659 if (ret < 0) in reg_write()
663 if (ret < 0) in reg_write()
664 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); in reg_write()
666 mutex_unlock(&priv->mutex); in reg_write()
672 struct i2c_client *client = priv->hdmi; in reg_write16()
676 mutex_lock(&priv->mutex); in reg_write16()
678 if (ret < 0) in reg_write16()
682 if (ret < 0) in reg_write16()
683 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); in reg_write16()
685 mutex_unlock(&priv->mutex); in reg_write16()
694 if (old_val >= 0) in reg_set()
704 if (old_val >= 0) in reg_clear()
714 reg_write(priv, REG_SOFTRESET, 0); in tda998x_reset()
722 reg_write(priv, REG_PLL_SERIAL_1, 0x00); in tda998x_reset()
724 reg_write(priv, REG_PLL_SERIAL_3, 0x00); in tda998x_reset()
725 reg_write(priv, REG_SERIALIZER, 0x00); in tda998x_reset()
726 reg_write(priv, REG_BUFFER_OUT, 0x00); in tda998x_reset()
727 reg_write(priv, REG_PLL_SCG1, 0x00); in tda998x_reset()
730 reg_write(priv, REG_PLL_SCGN1, 0xfa); in tda998x_reset()
731 reg_write(priv, REG_PLL_SCGN2, 0x00); in tda998x_reset()
732 reg_write(priv, REG_PLL_SCGR1, 0x5b); in tda998x_reset()
733 reg_write(priv, REG_PLL_SCGR2, 0x00); in tda998x_reset()
734 reg_write(priv, REG_PLL_SCG2, 0x10); in tda998x_reset()
736 /* Write the default value MUX register */ in tda998x_reset()
737 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24); in tda998x_reset()
748 * we have seen a HPD inactive->active transition. This code implements
755 priv->edid_delay_active = false; in tda998x_edid_delay_done()
756 wake_up(&priv->edid_delay_waitq); in tda998x_edid_delay_done()
757 schedule_work(&priv->detect_work); in tda998x_edid_delay_done()
762 priv->edid_delay_active = true; in tda998x_edid_delay_start()
763 mod_timer(&priv->edid_delay_timer, jiffies + HZ/10); in tda998x_edid_delay_start()
768 return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active); in tda998x_edid_delay_wait()
780 struct drm_device *dev = priv->connector.dev; in tda998x_detect_work()
810 schedule_work(&priv->detect_work); in tda998x_irq_thread()
812 priv->cec_notify); in tda998x_irq_thread()
818 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) { in tda998x_irq_thread()
819 priv->wq_edid_wait = 0; in tda998x_irq_thread()
820 wake_up(&priv->wq_edid); in tda998x_irq_thread()
836 if (len < 0) { in tda998x_write_if()
837 dev_err(&priv->hdmi->dev, in tda998x_write_if()
838 "hdmi_infoframe_pack() type=0x%02x failed: %zd\n", in tda998x_write_if()
839 frame->any.type, len); in tda998x_write_if()
864 &priv->connector, mode); in tda998x_write_avi()
866 drm_hdmi_avi_infoframe_quant_range(&frame.avi, &priv->connector, mode, in tda998x_write_avi()
867 priv->rgb_quant_range); in tda998x_write_avi()
878 &priv->connector, in tda998x_write_vsi()
894 .ena_aclk = 0,
905 s->route = &tda998x_audio_route[route]; in tda998x_derive_routing()
906 s->ena_ap = priv->audio_port_enable[route]; in tda998x_derive_routing()
907 if (s->ena_ap == 0) { in tda998x_derive_routing()
908 dev_err(&priv->hdmi->dev, "no audio configuration found\n"); in tda998x_derive_routing()
909 return -EINVAL; in tda998x_derive_routing()
912 return 0; in tda998x_derive_routing()
917 * from SERclk by dividing it by 2^n where 0 <= n <= 5. We don't know what
927 unsigned long ser_clk = priv->tmds_clock * 1000; in tda998x_get_adiv()
930 for (adiv = AUDIO_DIV_SERCLK_32; adiv != AUDIO_DIV_SERCLK_1; adiv--) in tda998x_get_adiv()
934 dev_dbg(&priv->hdmi->dev, in tda998x_get_adiv()
942 * In auto-CTS mode, the TDA998x uses a "measured time stamp" counter to
948 * tmdsclk ----> mts -> /m ---> CTS
950 * sclk -> /k -> /N
959 * When combined with the sink-side equation, and realising that sclk is
971 settings->cts_n = CTS_N_M(3) | CTS_N_K(0); in tda998x_derive_cts_n()
974 settings->cts_n = CTS_N_M(3) | CTS_N_K(1); in tda998x_derive_cts_n()
977 settings->cts_n = CTS_N_M(3) | CTS_N_K(2); in tda998x_derive_cts_n()
980 settings->cts_n = CTS_N_M(3) | CTS_N_K(3); in tda998x_derive_cts_n()
983 settings->cts_n = CTS_N_M(0) | CTS_N_K(0); in tda998x_derive_cts_n()
986 dev_err(&priv->hdmi->dev, "unsupported bclk ratio %ufs\n", in tda998x_derive_cts_n()
988 return -EINVAL; in tda998x_derive_cts_n()
990 return 0; in tda998x_derive_cts_n()
1006 const struct tda998x_audio_settings *settings = &priv->audio; in tda998x_configure_audio()
1011 if (settings->ena_ap == 0) in tda998x_configure_audio()
1014 adiv = tda998x_get_adiv(priv, settings->sample_rate); in tda998x_configure_audio()
1017 reg_write(priv, REG_ENA_AP, settings->ena_ap); in tda998x_configure_audio()
1018 reg_write(priv, REG_ENA_ACLK, settings->route->ena_aclk); in tda998x_configure_audio()
1019 reg_write(priv, REG_MUX_AP, settings->route->mux_ap); in tda998x_configure_audio()
1020 reg_write(priv, REG_I2S_FORMAT, settings->i2s_format); in tda998x_configure_audio()
1021 reg_write(priv, REG_AIP_CLKSEL, settings->route->aip_clksel); in tda998x_configure_audio()
1024 reg_write(priv, REG_CTS_N, settings->cts_n); in tda998x_configure_audio()
1029 * the recommended values for non-coherent clocks. in tda998x_configure_audio()
1031 n = 128 * settings->sample_rate / 1000; in tda998x_configure_audio()
1033 /* Write the CTS and N values */ in tda998x_configure_audio()
1034 buf[0] = 0x44; in tda998x_configure_audio()
1035 buf[1] = 0x42; in tda998x_configure_audio()
1036 buf[2] = 0x01; in tda998x_configure_audio()
1046 /* Write the channel status in tda998x_configure_audio()
1047 * The REG_CH_STAT_B-registers skip IEC958 AES2 byte, because in tda998x_configure_audio()
1050 buf[0] = settings->status[0]; in tda998x_configure_audio()
1051 buf[1] = settings->status[1]; in tda998x_configure_audio()
1052 buf[2] = settings->status[3]; in tda998x_configure_audio()
1053 buf[3] = settings->status[4]; in tda998x_configure_audio()
1054 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4); in tda998x_configure_audio()
1060 tda998x_write_aif(priv, &settings->cea); in tda998x_configure_audio()
1069 bool spdif = daifmt->fmt == HDMI_SPDIF; in tda998x_audio_hw_params()
1072 .sample_rate = params->sample_rate, in tda998x_audio_hw_params()
1073 .cea = params->cea, in tda998x_audio_hw_params()
1076 memcpy(audio.status, params->iec.status, in tda998x_audio_hw_params()
1077 min(sizeof(audio.status), sizeof(params->iec.status))); in tda998x_audio_hw_params()
1079 switch (daifmt->fmt) { in tda998x_audio_hw_params()
1090 audio.i2s_format = 0; in tda998x_audio_hw_params()
1093 dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt); in tda998x_audio_hw_params()
1094 return -EINVAL; in tda998x_audio_hw_params()
1098 (daifmt->bit_clk_inv || daifmt->frame_clk_inv || in tda998x_audio_hw_params()
1099 daifmt->bit_clk_provider || daifmt->frame_clk_provider)) { in tda998x_audio_hw_params()
1101 daifmt->bit_clk_inv, daifmt->frame_clk_inv, in tda998x_audio_hw_params()
1102 daifmt->bit_clk_provider, in tda998x_audio_hw_params()
1103 daifmt->frame_clk_provider); in tda998x_audio_hw_params()
1104 return -EINVAL; in tda998x_audio_hw_params()
1108 if (ret < 0) in tda998x_audio_hw_params()
1111 bclk_ratio = spdif ? 64 : params->sample_width * 2; in tda998x_audio_hw_params()
1113 if (ret < 0) in tda998x_audio_hw_params()
1116 mutex_lock(&priv->audio_mutex); in tda998x_audio_hw_params()
1117 priv->audio = audio; in tda998x_audio_hw_params()
1118 if (priv->supports_infoframes && priv->sink_has_audio) in tda998x_audio_hw_params()
1120 mutex_unlock(&priv->audio_mutex); in tda998x_audio_hw_params()
1122 return 0; in tda998x_audio_hw_params()
1129 mutex_lock(&priv->audio_mutex); in tda998x_audio_shutdown()
1131 reg_write(priv, REG_ENA_AP, 0); in tda998x_audio_shutdown()
1132 priv->audio.ena_ap = 0; in tda998x_audio_shutdown()
1134 mutex_unlock(&priv->audio_mutex); in tda998x_audio_shutdown()
1142 mutex_lock(&priv->audio_mutex); in tda998x_audio_mute_stream()
1146 mutex_unlock(&priv->audio_mutex); in tda998x_audio_mute_stream()
1147 return 0; in tda998x_audio_mute_stream()
1155 mutex_lock(&priv->audio_mutex); in tda998x_audio_get_eld()
1156 memcpy(buf, priv->connector.eld, in tda998x_audio_get_eld()
1157 min(sizeof(priv->connector.eld), len)); in tda998x_audio_get_eld()
1158 mutex_unlock(&priv->audio_mutex); in tda998x_audio_get_eld()
1160 return 0; in tda998x_audio_get_eld()
1181 if (priv->audio_port_enable[AUDIO_ROUTE_I2S]) in tda998x_audio_codec_init()
1183 if (priv->audio_port_enable[AUDIO_ROUTE_SPDIF]) in tda998x_audio_codec_init()
1186 priv->audio_pdev = platform_device_register_data( in tda998x_audio_codec_init()
1190 return PTR_ERR_OR_ZERO(priv->audio_pdev); in tda998x_audio_codec_init()
1225 offset = (blk & 1) ? 128 : 0; in read_edid_block()
1228 mutex_lock(&priv->edid_mutex); in read_edid_block()
1230 reg_write(priv, REG_DDC_ADDR, 0xa0); in read_edid_block()
1232 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60); in read_edid_block()
1236 priv->wq_edid_wait = 1; in read_edid_block()
1237 reg_write(priv, REG_EDID_CTRL, 0x1); in read_edid_block()
1240 reg_write(priv, REG_EDID_CTRL, 0x0); in read_edid_block()
1243 if (priv->hdmi->irq) { in read_edid_block()
1244 i = wait_event_timeout(priv->wq_edid, in read_edid_block()
1245 !priv->wq_edid_wait, in read_edid_block()
1247 if (i < 0) { in read_edid_block()
1248 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i); in read_edid_block()
1253 for (i = 100; i > 0; i--) { in read_edid_block()
1256 if (ret < 0) in read_edid_block()
1263 if (i == 0) { in read_edid_block()
1264 dev_err(&priv->hdmi->dev, "read edid timeout\n"); in read_edid_block()
1265 ret = -ETIMEDOUT; in read_edid_block()
1271 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n", in read_edid_block()
1276 ret = 0; in read_edid_block()
1279 mutex_unlock(&priv->edid_mutex); in read_edid_block()
1295 return 0; in tda998x_connector_get_modes()
1297 if (priv->rev == TDA19988) in tda998x_connector_get_modes()
1302 if (priv->rev == TDA19988) in tda998x_connector_get_modes()
1306 cec_notifier_set_phys_addr(priv->cec_notify, in tda998x_connector_get_modes()
1307 connector->display_info.source_physical_address); in tda998x_connector_get_modes()
1310 dev_warn(&priv->hdmi->dev, "failed to read EDID\n"); in tda998x_connector_get_modes()
1311 return 0; in tda998x_connector_get_modes()
1314 mutex_lock(&priv->audio_mutex); in tda998x_connector_get_modes()
1316 priv->sink_has_audio = connector->display_info.has_audio; in tda998x_connector_get_modes()
1317 mutex_unlock(&priv->audio_mutex); in tda998x_connector_get_modes()
1329 return priv->bridge.encoder; in tda998x_connector_best_encoder()
1341 struct drm_connector *connector = &priv->connector; in tda998x_connector_init()
1344 connector->interlace_allowed = 1; in tda998x_connector_init()
1346 if (priv->hdmi->irq) in tda998x_connector_init()
1347 connector->polled = DRM_CONNECTOR_POLL_HPD; in tda998x_connector_init()
1349 connector->polled = DRM_CONNECTOR_POLL_CONNECT | in tda998x_connector_init()
1358 drm_connector_attach_encoder(&priv->connector, in tda998x_connector_init()
1359 priv->bridge.encoder); in tda998x_connector_init()
1361 return 0; in tda998x_connector_init()
1373 return -EINVAL; in tda998x_bridge_attach()
1376 return tda998x_connector_init(priv, bridge->dev); in tda998x_bridge_attach()
1383 drm_connector_cleanup(&priv->connector); in tda998x_bridge_detach()
1393 if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000)) in tda998x_bridge_mode_valid()
1395 if (mode->htotal >= BIT(13)) in tda998x_bridge_mode_valid()
1397 if (mode->vtotal >= BIT(11)) in tda998x_bridge_mode_valid()
1406 if (!priv->is_on) { in tda998x_bridge_enable()
1408 reg_write(priv, REG_ENA_VP_0, 0xff); in tda998x_bridge_enable()
1409 reg_write(priv, REG_ENA_VP_1, 0xff); in tda998x_bridge_enable()
1410 reg_write(priv, REG_ENA_VP_2, 0xff); in tda998x_bridge_enable()
1412 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0); in tda998x_bridge_enable()
1413 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1); in tda998x_bridge_enable()
1414 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2); in tda998x_bridge_enable()
1416 priv->is_on = true; in tda998x_bridge_enable()
1424 if (priv->is_on) { in tda998x_bridge_disable()
1426 reg_write(priv, REG_ENA_VP_0, 0x00); in tda998x_bridge_disable()
1427 reg_write(priv, REG_ENA_VP_1, 0x00); in tda998x_bridge_disable()
1428 reg_write(priv, REG_ENA_VP_2, 0x00); in tda998x_bridge_disable()
1430 priv->is_on = false; in tda998x_bridge_disable()
1451 * full-range RGB. If the monitor supports full-range, then use in tda998x_bridge_mode_set()
1452 * it, otherwise reduce to limited-range. in tda998x_bridge_mode_set()
1454 priv->rgb_quant_range = in tda998x_bridge_mode_set()
1455 priv->connector.display_info.rgb_quant_range_selectable ? in tda998x_bridge_mode_set()
1460 * Internally TDA998x is using ITU-R BT.656 style sync but in tda998x_bridge_mode_set()
1468 * - HDMI data islands require sync-before-active in tda998x_bridge_mode_set()
1469 * - TDA998x register values must be > 0 to be enabled in tda998x_bridge_mode_set()
1470 * - REFLINE needs an additional offset of +1 in tda998x_bridge_mode_set()
1471 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB in tda998x_bridge_mode_set()
1476 n_pix = mode->htotal; in tda998x_bridge_mode_set()
1477 n_line = mode->vtotal; in tda998x_bridge_mode_set()
1479 hs_pix_e = mode->hsync_end - mode->hdisplay; in tda998x_bridge_mode_set()
1480 hs_pix_s = mode->hsync_start - mode->hdisplay; in tda998x_bridge_mode_set()
1481 de_pix_e = mode->htotal; in tda998x_bridge_mode_set()
1482 de_pix_s = mode->htotal - mode->hdisplay; in tda998x_bridge_mode_set()
1490 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW) in tda998x_bridge_mode_set()
1491 ref_pix += adjusted_mode->hskew; in tda998x_bridge_mode_set()
1493 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) { in tda998x_bridge_mode_set()
1494 ref_line = 1 + mode->vsync_start - mode->vdisplay; in tda998x_bridge_mode_set()
1495 vwin1_line_s = mode->vtotal - mode->vdisplay - 1; in tda998x_bridge_mode_set()
1496 vwin1_line_e = vwin1_line_s + mode->vdisplay; in tda998x_bridge_mode_set()
1498 vs1_line_s = mode->vsync_start - mode->vdisplay; in tda998x_bridge_mode_set()
1500 mode->vsync_end - mode->vsync_start; in tda998x_bridge_mode_set()
1501 vwin2_line_s = vwin2_line_e = 0; in tda998x_bridge_mode_set()
1502 vs2_pix_s = vs2_pix_e = 0; in tda998x_bridge_mode_set()
1503 vs2_line_s = vs2_line_e = 0; in tda998x_bridge_mode_set()
1505 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2; in tda998x_bridge_mode_set()
1506 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2; in tda998x_bridge_mode_set()
1507 vwin1_line_e = vwin1_line_s + mode->vdisplay/2; in tda998x_bridge_mode_set()
1509 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2; in tda998x_bridge_mode_set()
1511 (mode->vsync_end - mode->vsync_start)/2; in tda998x_bridge_mode_set()
1512 vwin2_line_s = vwin1_line_s + mode->vtotal/2; in tda998x_bridge_mode_set()
1513 vwin2_line_e = vwin2_line_s + mode->vdisplay/2; in tda998x_bridge_mode_set()
1514 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2; in tda998x_bridge_mode_set()
1515 vs2_line_s = vs1_line_s + mode->vtotal/2 ; in tda998x_bridge_mode_set()
1517 (mode->vsync_end - mode->vsync_start)/2; in tda998x_bridge_mode_set()
1521 * Select pixel repeat depending on the double-clock flag in tda998x_bridge_mode_set()
1524 rep = mode->flags & DRM_MODE_FLAG_DBLCLK ? 1 : 0; in tda998x_bridge_mode_set()
1526 SEL_CLK_SEL_VRF_CLK(rep ? 2 : 0); in tda998x_bridge_mode_set()
1529 tmds_clock = mode->clock * (1 + rep); in tda998x_bridge_mode_set()
1532 * The divisor is power-of-2. The TDA9983B datasheet gives in tda998x_bridge_mode_set()
1534 * 0 - 800 to 1500 Msample/s in tda998x_bridge_mode_set()
1535 * 1 - 400 to 800 Msample/s in tda998x_bridge_mode_set()
1536 * 2 - 200 to 400 Msample/s in tda998x_bridge_mode_set()
1537 * 3 - as 2 above in tda998x_bridge_mode_set()
1539 for (div = 0; div < 3; div++) in tda998x_bridge_mode_set()
1543 mutex_lock(&priv->audio_mutex); in tda998x_bridge_mode_set()
1545 priv->tmds_clock = tmds_clock; in tda998x_bridge_mode_set()
1553 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0)); in tda998x_bridge_mode_set()
1555 /* no pre-filter or interpolator: */ in tda998x_bridge_mode_set()
1556 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) | in tda998x_bridge_mode_set()
1557 HVF_CNTRL_0_INTPOL(0)); in tda998x_bridge_mode_set()
1559 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); in tda998x_bridge_mode_set()
1560 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) | in tda998x_bridge_mode_set()
1561 VIP_CNTRL_4_BLC(0)); in tda998x_bridge_mode_set()
1566 reg_write(priv, REG_SERIALIZER, 0); in tda998x_bridge_mode_set()
1567 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0)); in tda998x_bridge_mode_set()
1575 if (priv->rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) { in tda998x_bridge_mode_set()
1578 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, in tda998x_bridge_mode_set()
1579 0x03, 0x6f, 0x00, 0x00, 0x00, 0x00, in tda998x_bridge_mode_set()
1580 0x00, 0x00, 0x03, 0x6f, 0x00, 0x00, in tda998x_bridge_mode_set()
1581 0x00, 0x00, 0x00, 0x00, 0x03, 0x6f, in tda998x_bridge_mode_set()
1582 0x00, 0x40, 0x00, 0x40, 0x00, 0x40 in tda998x_bridge_mode_set()
1595 reg_write(priv, REG_ANA_GENERAL, 0x09); in tda998x_bridge_mode_set()
1603 * TDA19988 requires high-active sync at input stage, in tda998x_bridge_mode_set()
1604 * so invert low-active sync provided by master encoder here in tda998x_bridge_mode_set()
1606 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in tda998x_bridge_mode_set()
1608 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in tda998x_bridge_mode_set()
1612 reg_write(priv, REG_VIDFORMAT, 0x00); in tda998x_bridge_mode_set()
1634 if (priv->rev == TDA19988) { in tda998x_bridge_mode_set()
1636 reg_write(priv, REG_ENABLE_SPACE, 0x00); in tda998x_bridge_mode_set()
1644 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in tda998x_bridge_mode_set()
1646 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in tda998x_bridge_mode_set()
1651 reg_write(priv, REG_TBG_CNTRL_0, 0); in tda998x_bridge_mode_set()
1653 /* CEA-861B section 6 says that: in tda998x_bridge_mode_set()
1654 * CEA version 1 (CEA-861) has no support for infoframes. in tda998x_bridge_mode_set()
1655 * CEA version 2 (CEA-861A) supports version 1 AVI infoframes, in tda998x_bridge_mode_set()
1657 * CEA version 3 (CEA-861B) supports version 1 and 2 AVI infoframes, in tda998x_bridge_mode_set()
1662 * CEA-861 source.) in tda998x_bridge_mode_set()
1664 priv->supports_infoframes = priv->connector.display_info.cea_rev >= 3; in tda998x_bridge_mode_set()
1666 if (priv->supports_infoframes) { in tda998x_bridge_mode_set()
1676 if (priv->sink_has_audio) in tda998x_bridge_mode_set()
1680 mutex_unlock(&priv->audio_mutex); in tda998x_bridge_mode_set()
1701 port_data = of_get_property(np, "audio-ports", &size); in tda998x_get_audio_ports()
1703 return 0; in tda998x_get_audio_ports()
1706 if (size > 2 * ARRAY_SIZE(priv->audio_port_enable) || size % 2 != 0) { in tda998x_get_audio_ports()
1707 dev_err(&priv->hdmi->dev, in tda998x_get_audio_ports()
1708 "Bad number of elements in audio-ports dt-property\n"); in tda998x_get_audio_ports()
1709 return -EINVAL; in tda998x_get_audio_ports()
1714 for (i = 0; i < size; i++) { in tda998x_get_audio_ports()
1727 dev_err(&priv->hdmi->dev, in tda998x_get_audio_ports()
1729 return -EINVAL; in tda998x_get_audio_ports()
1733 dev_err(&priv->hdmi->dev, "invalid zero port config\n"); in tda998x_get_audio_ports()
1737 if (priv->audio_port_enable[route]) { in tda998x_get_audio_ports()
1738 dev_err(&priv->hdmi->dev, in tda998x_get_audio_ports()
1741 return -EINVAL; in tda998x_get_audio_ports()
1744 priv->audio_port_enable[route] = ena_ap; in tda998x_get_audio_ports()
1746 return 0; in tda998x_get_audio_ports()
1752 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) | in tda998x_set_config()
1753 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) | in tda998x_set_config()
1754 VIP_CNTRL_0_SWAP_B(p->swap_b) | in tda998x_set_config()
1755 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0); in tda998x_set_config()
1756 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) | in tda998x_set_config()
1757 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) | in tda998x_set_config()
1758 VIP_CNTRL_1_SWAP_D(p->swap_d) | in tda998x_set_config()
1759 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0); in tda998x_set_config()
1760 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) | in tda998x_set_config()
1761 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) | in tda998x_set_config()
1762 VIP_CNTRL_2_SWAP_F(p->swap_f) | in tda998x_set_config()
1763 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0); in tda998x_set_config()
1765 if (p->audio_params.format != AFMT_UNUSED) { in tda998x_set_config()
1767 bool spdif = p->audio_params.format == AFMT_SPDIF; in tda998x_set_config()
1771 priv->audio.route = &tda998x_audio_route[route]; in tda998x_set_config()
1772 priv->audio.cea = p->audio_params.cea; in tda998x_set_config()
1773 priv->audio.sample_rate = p->audio_params.sample_rate; in tda998x_set_config()
1774 memcpy(priv->audio.status, p->audio_params.status, in tda998x_set_config()
1775 min(sizeof(priv->audio.status), in tda998x_set_config()
1776 sizeof(p->audio_params.status))); in tda998x_set_config()
1777 priv->audio.ena_ap = p->audio_params.config; in tda998x_set_config()
1778 priv->audio.i2s_format = I2S_FORMAT_PHILIPS; in tda998x_set_config()
1780 ratio = spdif ? 64 : p->audio_params.sample_width * 2; in tda998x_set_config()
1781 return tda998x_derive_cts_n(priv, &priv->audio, ratio); in tda998x_set_config()
1784 return 0; in tda998x_set_config()
1791 drm_bridge_remove(&priv->bridge); in tda998x_destroy()
1794 cec_write(priv, REG_CEC_RXSHPDINTENA, 0); in tda998x_destroy()
1797 if (priv->audio_pdev) in tda998x_destroy()
1798 platform_device_unregister(priv->audio_pdev); in tda998x_destroy()
1800 if (priv->hdmi->irq) in tda998x_destroy()
1801 free_irq(priv->hdmi->irq, priv); in tda998x_destroy()
1803 del_timer_sync(&priv->edid_delay_timer); in tda998x_destroy()
1804 cancel_work_sync(&priv->detect_work); in tda998x_destroy()
1806 i2c_unregister_device(priv->cec); in tda998x_destroy()
1808 cec_notifier_conn_unregister(priv->cec_notify); in tda998x_destroy()
1814 struct device_node *np = client->dev.of_node; in tda998x_create()
1822 return -ENOMEM; in tda998x_create()
1826 mutex_init(&priv->mutex); /* protect the page access */ in tda998x_create()
1827 mutex_init(&priv->audio_mutex); /* protect access from audio thread */ in tda998x_create()
1828 mutex_init(&priv->edid_mutex); in tda998x_create()
1829 INIT_LIST_HEAD(&priv->bridge.list); in tda998x_create()
1830 init_waitqueue_head(&priv->edid_delay_waitq); in tda998x_create()
1831 timer_setup(&priv->edid_delay_timer, tda998x_edid_delay_done, 0); in tda998x_create()
1832 INIT_WORK(&priv->detect_work, tda998x_detect_work); in tda998x_create()
1834 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3); in tda998x_create()
1835 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1); in tda998x_create()
1836 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5); in tda998x_create()
1839 priv->cec_addr = 0x34 + (client->addr & 0x03); in tda998x_create()
1840 priv->current_page = 0xff; in tda998x_create()
1841 priv->hdmi = client; in tda998x_create()
1851 if (rev_lo < 0) { in tda998x_create()
1857 if (rev_hi < 0) { in tda998x_create()
1862 priv->rev = rev_lo | rev_hi << 8; in tda998x_create()
1865 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */ in tda998x_create()
1867 switch (priv->rev) { in tda998x_create()
1881 dev_err(dev, "found unsupported device: %04x\n", priv->rev); in tda998x_create()
1882 return -ENXIO; in tda998x_create()
1886 reg_write(priv, REG_DDC_DISABLE, 0x00); in tda998x_create()
1891 /* if necessary, disable multi-master: */ in tda998x_create()
1892 if (priv->rev == TDA19989) in tda998x_create()
1899 cec_write(priv, REG_CEC_RXSHPDINTENA, 0); in tda998x_create()
1908 if (client->irq) { in tda998x_create()
1912 init_waitqueue_head(&priv->wq_edid); in tda998x_create()
1915 irqd_get_trigger_type(irq_get_irq_data(client->irq)); in tda998x_create()
1917 priv->cec_glue.irq_flags = irq_flags; in tda998x_create()
1920 ret = request_threaded_irq(client->irq, NULL, in tda998x_create()
1925 client->irq, ret); in tda998x_create()
1933 priv->cec_notify = cec_notifier_conn_register(dev, NULL, NULL); in tda998x_create()
1934 if (!priv->cec_notify) { in tda998x_create()
1935 ret = -ENOMEM; in tda998x_create()
1939 priv->cec_glue.parent = dev; in tda998x_create()
1940 priv->cec_glue.data = priv; in tda998x_create()
1941 priv->cec_glue.init = tda998x_cec_hook_init; in tda998x_create()
1942 priv->cec_glue.exit = tda998x_cec_hook_exit; in tda998x_create()
1943 priv->cec_glue.open = tda998x_cec_hook_open; in tda998x_create()
1944 priv->cec_glue.release = tda998x_cec_hook_release; in tda998x_create()
1954 memset(&cec_info, 0, sizeof(cec_info)); in tda998x_create()
1956 cec_info.addr = priv->cec_addr; in tda998x_create()
1957 cec_info.platform_data = &priv->cec_glue; in tda998x_create()
1958 cec_info.irq = client->irq; in tda998x_create()
1960 priv->cec = i2c_new_client_device(client->adapter, &cec_info); in tda998x_create()
1961 if (IS_ERR(priv->cec)) { in tda998x_create()
1962 ret = PTR_ERR(priv->cec); in tda998x_create()
1971 ret = of_property_read_u32(np, "video-ports", &video); in tda998x_create()
1972 if (ret == 0) { in tda998x_create()
1973 priv->vip_cntrl_0 = video >> 16; in tda998x_create()
1974 priv->vip_cntrl_1 = video >> 8; in tda998x_create()
1975 priv->vip_cntrl_2 = video; in tda998x_create()
1982 if (priv->audio_port_enable[AUDIO_ROUTE_I2S] || in tda998x_create()
1983 priv->audio_port_enable[AUDIO_ROUTE_SPDIF]) in tda998x_create()
1984 tda998x_audio_codec_init(priv, &client->dev); in tda998x_create()
1985 } else if (dev->platform_data) { in tda998x_create()
1986 ret = tda998x_set_config(priv, dev->platform_data); in tda998x_create()
1991 priv->bridge.funcs = &tda998x_bridge_funcs; in tda998x_create()
1993 priv->bridge.of_node = dev->of_node; in tda998x_create()
1996 drm_bridge_add(&priv->bridge); in tda998x_create()
1998 return 0; in tda998x_create()
2011 u32 crtcs = 0; in tda998x_encoder_init()
2014 if (dev->of_node) in tda998x_encoder_init()
2015 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); in tda998x_encoder_init()
2018 if (crtcs == 0) { in tda998x_encoder_init()
2020 crtcs = 1 << 0; in tda998x_encoder_init()
2023 priv->encoder.possible_crtcs = crtcs; in tda998x_encoder_init()
2025 ret = drm_simple_encoder_init(drm, &priv->encoder, in tda998x_encoder_init()
2030 ret = drm_bridge_attach(&priv->encoder, &priv->bridge, NULL, 0); in tda998x_encoder_init()
2034 return 0; in tda998x_encoder_init()
2037 drm_encoder_cleanup(&priv->encoder); in tda998x_encoder_init()
2054 drm_encoder_cleanup(&priv->encoder); in tda998x_unbind()
2067 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { in tda998x_probe()
2068 dev_warn(&client->dev, "adapter does not support I2C\n"); in tda998x_probe()
2069 return -EIO; in tda998x_probe()
2072 ret = tda998x_create(&client->dev); in tda998x_probe()
2076 ret = component_add(&client->dev, &tda998x_ops); in tda998x_probe()
2078 tda998x_destroy(&client->dev); in tda998x_probe()
2084 component_del(&client->dev, &tda998x_ops); in tda998x_remove()
2085 tda998x_destroy(&client->dev); in tda998x_remove()
2097 { "tda998x", 0 },