Lines Matching full:dp
12 static inline int hibmc_dp_get_serdes_rate_cfg(struct hibmc_dp_dev *dp) in hibmc_dp_get_serdes_rate_cfg() argument
14 switch (dp->link.cap.link_rate) { in hibmc_dp_get_serdes_rate_cfg()
28 static int hibmc_dp_link_training_configure(struct hibmc_dp_dev *dp) in hibmc_dp_link_training_configure() argument
33 /* DP 2 lane */ in hibmc_dp_link_training_configure()
34 hibmc_dp_reg_write_field(dp, HIBMC_DP_PHYIF_CTRL0, HIBMC_DP_CFG_LANE_DATA_EN, in hibmc_dp_link_training_configure()
35 dp->link.cap.lanes == 0x2 ? 0x3 : 0x1); in hibmc_dp_link_training_configure()
36 hibmc_dp_reg_write_field(dp, HIBMC_DP_DPTX_GCTL0, HIBMC_DP_CFG_PHY_LANE_NUM, in hibmc_dp_link_training_configure()
37 dp->link.cap.lanes == 0x2 ? 0x1 : 0); in hibmc_dp_link_training_configure()
40 hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CTRL, HIBMC_DP_CFG_STREAM_FRAME_MODE, 0x1); in hibmc_dp_link_training_configure()
43 buf[0] = dp->link.cap.link_rate; in hibmc_dp_link_training_configure()
44 buf[1] = DP_LANE_COUNT_ENHANCED_FRAME_EN | dp->link.cap.lanes; in hibmc_dp_link_training_configure()
45 ret = drm_dp_dpcd_write(dp->aux, DP_LINK_BW_SET, buf, sizeof(buf)); in hibmc_dp_link_training_configure()
47 drm_dbg_dp(dp->dev, "dp aux write link rate and lanes failed, ret: %d\n", ret); in hibmc_dp_link_training_configure()
54 ret = drm_dp_dpcd_write(dp->aux, DP_DOWNSPREAD_CTRL, buf, sizeof(buf)); in hibmc_dp_link_training_configure()
56 drm_dbg_dp(dp->dev, "dp aux write 8b/10b and downspread failed, ret: %d\n", ret); in hibmc_dp_link_training_configure()
63 static int hibmc_dp_link_set_pattern(struct hibmc_dp_dev *dp, int pattern) in hibmc_dp_link_set_pattern() argument
72 hibmc_dp_reg_write_field(dp, HIBMC_DP_PHYIF_CTRL0, HIBMC_DP_CFG_SCRAMBLE_EN, 0x1); in hibmc_dp_link_set_pattern()
74 hibmc_dp_reg_write_field(dp, HIBMC_DP_PHYIF_CTRL0, HIBMC_DP_CFG_SCRAMBLE_EN, 0); in hibmc_dp_link_set_pattern()
97 hibmc_dp_reg_write_field(dp, HIBMC_DP_PHYIF_CTRL0, HIBMC_DP_CFG_PAT_SEL, val); in hibmc_dp_link_set_pattern()
99 ret = drm_dp_dpcd_write(dp->aux, DP_TRAINING_PATTERN_SET, &buf, sizeof(buf)); in hibmc_dp_link_set_pattern()
101 drm_dbg_dp(dp->dev, "dp aux write training pattern set failed\n"); in hibmc_dp_link_set_pattern()
108 static int hibmc_dp_link_training_cr_pre(struct hibmc_dp_dev *dp) in hibmc_dp_link_training_cr_pre() argument
110 u8 *train_set = dp->link.train_set; in hibmc_dp_link_training_cr_pre()
114 ret = hibmc_dp_link_training_configure(dp); in hibmc_dp_link_training_cr_pre()
118 ret = hibmc_dp_link_set_pattern(dp, DP_TRAINING_PATTERN_1); in hibmc_dp_link_training_cr_pre()
122 for (i = 0; i < dp->link.cap.lanes; i++) in hibmc_dp_link_training_cr_pre()
125 ret = hibmc_dp_serdes_set_tx_cfg(dp, dp->link.train_set); in hibmc_dp_link_training_cr_pre()
129 ret = drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET, train_set, dp->link.cap.lanes); in hibmc_dp_link_training_cr_pre()
130 if (ret != dp->link.cap.lanes) { in hibmc_dp_link_training_cr_pre()
131 drm_dbg_dp(dp->dev, "dp aux write training lane set failed\n"); in hibmc_dp_link_training_cr_pre()
138 static bool hibmc_dp_link_get_adjust_train(struct hibmc_dp_dev *dp, in hibmc_dp_link_get_adjust_train() argument
144 for (lane = 0; lane < dp->link.cap.lanes; lane++) in hibmc_dp_link_get_adjust_train()
148 if (memcmp(dp->link.train_set, train_set, HIBMC_DP_LANE_NUM_MAX)) { in hibmc_dp_link_get_adjust_train()
149 memcpy(dp->link.train_set, train_set, HIBMC_DP_LANE_NUM_MAX); in hibmc_dp_link_get_adjust_train()
156 static int hibmc_dp_link_reduce_rate(struct hibmc_dp_dev *dp) in hibmc_dp_link_reduce_rate() argument
160 switch (dp->link.cap.link_rate) { in hibmc_dp_link_reduce_rate()
162 dp->link.cap.link_rate = DP_LINK_BW_1_62; in hibmc_dp_link_reduce_rate()
165 dp->link.cap.link_rate = DP_LINK_BW_2_7; in hibmc_dp_link_reduce_rate()
168 dp->link.cap.link_rate = DP_LINK_BW_5_4; in hibmc_dp_link_reduce_rate()
174 ret = hibmc_dp_get_serdes_rate_cfg(dp); in hibmc_dp_link_reduce_rate()
178 return hibmc_dp_serdes_rate_switch(ret, dp); in hibmc_dp_link_reduce_rate()
181 static inline int hibmc_dp_link_reduce_lane(struct hibmc_dp_dev *dp) in hibmc_dp_link_reduce_lane() argument
183 switch (dp->link.cap.lanes) { in hibmc_dp_link_reduce_lane()
185 dp->link.cap.lanes--; in hibmc_dp_link_reduce_lane()
186 drm_dbg_dp(dp->dev, "dp link training reduce to 1 lane\n"); in hibmc_dp_link_reduce_lane()
189 drm_err(dp->dev, "dp link training reduce lane failed, already reach minimum\n"); in hibmc_dp_link_reduce_lane()
198 static int hibmc_dp_link_training_cr(struct hibmc_dp_dev *dp) in hibmc_dp_link_training_cr() argument
207 * DP 1.4 spec define 10 for maxtries value, for pre DP 1.4 version set a limit of 80 in hibmc_dp_link_training_cr()
213 drm_dp_link_train_clock_recovery_delay(dp->aux, dp->dpcd); in hibmc_dp_link_training_cr()
215 ret = drm_dp_dpcd_read_link_status(dp->aux, lane_status); in hibmc_dp_link_training_cr()
217 drm_err(dp->dev, "Get lane status failed\n"); in hibmc_dp_link_training_cr()
221 if (drm_dp_clock_recovery_ok(lane_status, dp->link.cap.lanes)) { in hibmc_dp_link_training_cr()
222 drm_dbg_dp(dp->dev, "dp link training cr done\n"); in hibmc_dp_link_training_cr()
223 dp->link.status.clock_recovered = true; in hibmc_dp_link_training_cr()
228 drm_dbg_dp(dp->dev, "same voltage tries 5 times\n"); in hibmc_dp_link_training_cr()
229 dp->link.status.clock_recovered = false; in hibmc_dp_link_training_cr()
233 level_changed = hibmc_dp_link_get_adjust_train(dp, lane_status); in hibmc_dp_link_training_cr()
235 ret = hibmc_dp_serdes_set_tx_cfg(dp, dp->link.train_set); in hibmc_dp_link_training_cr()
239 ret = drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET, dp->link.train_set, in hibmc_dp_link_training_cr()
240 dp->link.cap.lanes); in hibmc_dp_link_training_cr()
241 if (ret != dp->link.cap.lanes) { in hibmc_dp_link_training_cr()
242 drm_dbg_dp(dp->dev, "Update link training failed\n"); in hibmc_dp_link_training_cr()
249 drm_err(dp->dev, "dp link training clock recovery 80 times failed\n"); in hibmc_dp_link_training_cr()
250 dp->link.status.clock_recovered = false; in hibmc_dp_link_training_cr()
255 static int hibmc_dp_link_training_channel_eq(struct hibmc_dp_dev *dp) in hibmc_dp_link_training_channel_eq() argument
261 ret = hibmc_dp_link_set_pattern(dp, DP_TRAINING_PATTERN_2); in hibmc_dp_link_training_channel_eq()
266 drm_dp_link_train_channel_eq_delay(dp->aux, dp->dpcd); in hibmc_dp_link_training_channel_eq()
268 ret = drm_dp_dpcd_read_link_status(dp->aux, lane_status); in hibmc_dp_link_training_channel_eq()
270 drm_err(dp->dev, "get lane status failed\n"); in hibmc_dp_link_training_channel_eq()
274 if (!drm_dp_clock_recovery_ok(lane_status, dp->link.cap.lanes)) { in hibmc_dp_link_training_channel_eq()
275 drm_dbg_dp(dp->dev, "clock recovery check failed\n"); in hibmc_dp_link_training_channel_eq()
276 drm_dbg_dp(dp->dev, "cannot continue channel equalization\n"); in hibmc_dp_link_training_channel_eq()
277 dp->link.status.clock_recovered = false; in hibmc_dp_link_training_channel_eq()
281 if (drm_dp_channel_eq_ok(lane_status, dp->link.cap.lanes)) { in hibmc_dp_link_training_channel_eq()
282 dp->link.status.channel_equalized = true; in hibmc_dp_link_training_channel_eq()
283 drm_dbg_dp(dp->dev, "dp link training eq done\n"); in hibmc_dp_link_training_channel_eq()
287 hibmc_dp_link_get_adjust_train(dp, lane_status); in hibmc_dp_link_training_channel_eq()
289 ret = hibmc_dp_serdes_set_tx_cfg(dp, dp->link.train_set); in hibmc_dp_link_training_channel_eq()
293 ret = drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET, in hibmc_dp_link_training_channel_eq()
294 dp->link.train_set, dp->link.cap.lanes); in hibmc_dp_link_training_channel_eq()
295 if (ret != dp->link.cap.lanes) { in hibmc_dp_link_training_channel_eq()
296 drm_dbg_dp(dp->dev, "Update link training failed\n"); in hibmc_dp_link_training_channel_eq()
303 drm_err(dp->dev, "channel equalization failed %u times\n", eq_tries); in hibmc_dp_link_training_channel_eq()
305 hibmc_dp_link_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE); in hibmc_dp_link_training_channel_eq()
310 static int hibmc_dp_link_downgrade_training_cr(struct hibmc_dp_dev *dp) in hibmc_dp_link_downgrade_training_cr() argument
312 if (hibmc_dp_link_reduce_rate(dp)) in hibmc_dp_link_downgrade_training_cr()
313 return hibmc_dp_link_reduce_lane(dp); in hibmc_dp_link_downgrade_training_cr()
318 static int hibmc_dp_link_downgrade_training_eq(struct hibmc_dp_dev *dp) in hibmc_dp_link_downgrade_training_eq() argument
320 if ((dp->link.status.clock_recovered && !dp->link.status.channel_equalized)) { in hibmc_dp_link_downgrade_training_eq()
321 if (!hibmc_dp_link_reduce_lane(dp)) in hibmc_dp_link_downgrade_training_eq()
325 return hibmc_dp_link_reduce_rate(dp); in hibmc_dp_link_downgrade_training_eq()
328 static void hibmc_dp_update_caps(struct hibmc_dp_dev *dp) in hibmc_dp_update_caps() argument
330 dp->link.cap.link_rate = dp->dpcd[DP_MAX_LINK_RATE]; in hibmc_dp_update_caps()
331 if (dp->link.cap.link_rate > DP_LINK_BW_8_1 || !dp->link.cap.link_rate) in hibmc_dp_update_caps()
332 dp->link.cap.link_rate = DP_LINK_BW_8_1; in hibmc_dp_update_caps()
334 dp->link.cap.lanes = dp->dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; in hibmc_dp_update_caps()
335 if (dp->link.cap.lanes > HIBMC_DP_LANE_NUM_MAX) in hibmc_dp_update_caps()
336 dp->link.cap.lanes = HIBMC_DP_LANE_NUM_MAX; in hibmc_dp_update_caps()
339 int hibmc_dp_link_training(struct hibmc_dp_dev *dp) in hibmc_dp_link_training() argument
341 struct hibmc_dp_link *link = &dp->link; in hibmc_dp_link_training()
344 ret = drm_dp_read_dpcd_caps(dp->aux, dp->dpcd); in hibmc_dp_link_training()
346 drm_err(dp->dev, "dp aux read dpcd failed, ret: %d\n", ret); in hibmc_dp_link_training()
348 hibmc_dp_update_caps(dp); in hibmc_dp_link_training()
350 ret = hibmc_dp_get_serdes_rate_cfg(dp); in hibmc_dp_link_training()
354 ret = hibmc_dp_serdes_rate_switch(ret, dp); in hibmc_dp_link_training()
359 ret = hibmc_dp_link_training_cr_pre(dp); in hibmc_dp_link_training()
363 ret = hibmc_dp_link_training_cr(dp); in hibmc_dp_link_training()
368 ret = hibmc_dp_link_downgrade_training_cr(dp); in hibmc_dp_link_training()
374 ret = hibmc_dp_link_training_channel_eq(dp); in hibmc_dp_link_training()
379 ret = hibmc_dp_link_downgrade_training_eq(dp); in hibmc_dp_link_training()
389 hibmc_dp_link_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE); in hibmc_dp_link_training()