14 	switch (dp->link.cap.link_rate) {  in hibmc_dp_get_serdes_rate_cfg()
35 				 dp->link.cap.lanes == 0x2 ? 0x3 : 0x1);  in hibmc_dp_link_training_configure()
37 				 dp->link.cap.lanes == 0x2 ? 0x1 : 0);  in hibmc_dp_link_training_configure()
43 	buf[0] = dp->link.cap.link_rate;  in hibmc_dp_link_training_configure()
44 	buf[1] = DP_LANE_COUNT_ENHANCED_FRAME_EN | dp->link.cap.lanes;  in hibmc_dp_link_training_configure()
47 		drm_dbg_dp(dp->dev, "dp aux write link rate and lanes failed, ret: %d\n", ret);  in hibmc_dp_link_training_configure()
110 	u8 *train_set = dp->link.train_set;  in hibmc_dp_link_training_cr_pre()
122 	for (i = 0; i < dp->link.cap.lanes; i++)  in hibmc_dp_link_training_cr_pre()
125 	ret = hibmc_dp_serdes_set_tx_cfg(dp, dp->link.train_set);  in hibmc_dp_link_training_cr_pre()
129 	ret = drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET, train_set, dp->link.cap.lanes);  in hibmc_dp_link_training_cr_pre()
130 	if (ret != dp->link.cap.lanes) {  in hibmc_dp_link_training_cr_pre()
144 	for (lane = 0; lane < dp->link.cap.lanes; lane++)  in hibmc_dp_link_get_adjust_train()
148 	if (memcmp(dp->link.train_set, train_set, HIBMC_DP_LANE_NUM_MAX)) {  in hibmc_dp_link_get_adjust_train()
149 		memcpy(dp->link.train_set, train_set, HIBMC_DP_LANE_NUM_MAX);  in hibmc_dp_link_get_adjust_train()
160 	switch (dp->link.cap.link_rate) {  in hibmc_dp_link_reduce_rate()
162 		dp->link.cap.link_rate = DP_LINK_BW_1_62;  in hibmc_dp_link_reduce_rate()
165 		dp->link.cap.link_rate = DP_LINK_BW_2_7;  in hibmc_dp_link_reduce_rate()
168 		dp->link.cap.link_rate = DP_LINK_BW_5_4;  in hibmc_dp_link_reduce_rate()
183 	switch (dp->link.cap.lanes) {  in hibmc_dp_link_reduce_lane()
185 		dp->link.cap.lanes--;  in hibmc_dp_link_reduce_lane()
186 		drm_dbg_dp(dp->dev, "dp link training reduce to 1 lane\n");  in hibmc_dp_link_reduce_lane()
189 		drm_err(dp->dev, "dp link training reduce lane failed, already reach minimum\n");  in hibmc_dp_link_reduce_lane()
221 		if (drm_dp_clock_recovery_ok(lane_status, dp->link.cap.lanes)) {  in hibmc_dp_link_training_cr()
222 			drm_dbg_dp(dp->dev, "dp link training cr done\n");  in hibmc_dp_link_training_cr()
223 			dp->link.status.clock_recovered = true;  in hibmc_dp_link_training_cr()
229 			dp->link.status.clock_recovered = false;  in hibmc_dp_link_training_cr()
235 		ret = hibmc_dp_serdes_set_tx_cfg(dp, dp->link.train_set);  in hibmc_dp_link_training_cr()
239 		ret = drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET, dp->link.train_set,  in hibmc_dp_link_training_cr()
240 					dp->link.cap.lanes);  in hibmc_dp_link_training_cr()
241 		if (ret != dp->link.cap.lanes) {  in hibmc_dp_link_training_cr()
242 			drm_dbg_dp(dp->dev, "Update link training failed\n");  in hibmc_dp_link_training_cr()
249 	drm_err(dp->dev, "dp link training clock recovery 80 times failed\n");  in hibmc_dp_link_training_cr()
250 	dp->link.status.clock_recovered = false;  in hibmc_dp_link_training_cr()
274 		if (!drm_dp_clock_recovery_ok(lane_status, dp->link.cap.lanes)) {  in hibmc_dp_link_training_channel_eq()
277 			dp->link.status.clock_recovered = false;  in hibmc_dp_link_training_channel_eq()
281 		if (drm_dp_channel_eq_ok(lane_status, dp->link.cap.lanes)) {  in hibmc_dp_link_training_channel_eq()
282 			dp->link.status.channel_equalized = true;  in hibmc_dp_link_training_channel_eq()
283 			drm_dbg_dp(dp->dev, "dp link training eq done\n");  in hibmc_dp_link_training_channel_eq()
289 		ret = hibmc_dp_serdes_set_tx_cfg(dp, dp->link.train_set);  in hibmc_dp_link_training_channel_eq()
294 					dp->link.train_set, dp->link.cap.lanes);  in hibmc_dp_link_training_channel_eq()
295 		if (ret != dp->link.cap.lanes) {  in hibmc_dp_link_training_channel_eq()
296 			drm_dbg_dp(dp->dev, "Update link training failed\n");  in hibmc_dp_link_training_channel_eq()
320 	if ((dp->link.status.clock_recovered && !dp->link.status.channel_equalized)) {  in hibmc_dp_link_downgrade_training_eq()
330 	dp->link.cap.link_rate = dp->dpcd[DP_MAX_LINK_RATE];  in hibmc_dp_update_caps()
331 	if (dp->link.cap.link_rate > DP_LINK_BW_8_1 || !dp->link.cap.link_rate)  in hibmc_dp_update_caps()
332 		dp->link.cap.link_rate = DP_LINK_BW_8_1;  in hibmc_dp_update_caps()
334 	dp->link.cap.lanes = dp->dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;  in hibmc_dp_update_caps()
335 	if (dp->link.cap.lanes > HIBMC_DP_LANE_NUM_MAX)  in hibmc_dp_update_caps()
336 		dp->link.cap.lanes = HIBMC_DP_LANE_NUM_MAX;  in hibmc_dp_update_caps()
341 	struct hibmc_dp_link *link = &dp->link;  in hibmc_dp_link_training()  local
367 		if (!link->status.clock_recovered) {  in hibmc_dp_link_training()
378 		if (!link->status.channel_equalized) {  in hibmc_dp_link_training()