Lines Matching full:dp
12 static int hibmc_dp_link_training_configure(struct hibmc_dp_dev *dp) in hibmc_dp_link_training_configure() argument
17 /* DP 2 lane */ in hibmc_dp_link_training_configure()
18 hibmc_dp_reg_write_field(dp, HIBMC_DP_PHYIF_CTRL0, HIBMC_DP_CFG_LANE_DATA_EN, in hibmc_dp_link_training_configure()
19 dp->link.cap.lanes == 0x2 ? 0x3 : 0x1); in hibmc_dp_link_training_configure()
20 hibmc_dp_reg_write_field(dp, HIBMC_DP_DPTX_GCTL0, HIBMC_DP_CFG_PHY_LANE_NUM, in hibmc_dp_link_training_configure()
21 dp->link.cap.lanes == 0x2 ? 0x1 : 0); in hibmc_dp_link_training_configure()
24 hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CTRL, HIBMC_DP_CFG_STREAM_FRAME_MODE, 0x1); in hibmc_dp_link_training_configure()
27 buf[0] = dp->link.cap.link_rate; in hibmc_dp_link_training_configure()
28 buf[1] = DP_LANE_COUNT_ENHANCED_FRAME_EN | dp->link.cap.lanes; in hibmc_dp_link_training_configure()
29 ret = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, sizeof(buf)); in hibmc_dp_link_training_configure()
31 drm_dbg_dp(dp->dev, "dp aux write link rate and lanes failed, ret: %d\n", ret); in hibmc_dp_link_training_configure()
38 ret = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, sizeof(buf)); in hibmc_dp_link_training_configure()
40 drm_dbg_dp(dp->dev, "dp aux write 8b/10b and downspread failed, ret: %d\n", ret); in hibmc_dp_link_training_configure()
44 ret = drm_dp_read_dpcd_caps(&dp->aux, dp->dpcd); in hibmc_dp_link_training_configure()
46 drm_err(dp->dev, "dp aux read dpcd failed, ret: %d\n", ret); in hibmc_dp_link_training_configure()
51 static int hibmc_dp_link_set_pattern(struct hibmc_dp_dev *dp, int pattern) in hibmc_dp_link_set_pattern() argument
60 hibmc_dp_reg_write_field(dp, HIBMC_DP_PHYIF_CTRL0, HIBMC_DP_CFG_SCRAMBLE_EN, 0x1); in hibmc_dp_link_set_pattern()
62 hibmc_dp_reg_write_field(dp, HIBMC_DP_PHYIF_CTRL0, HIBMC_DP_CFG_SCRAMBLE_EN, 0); in hibmc_dp_link_set_pattern()
85 hibmc_dp_reg_write_field(dp, HIBMC_DP_PHYIF_CTRL0, HIBMC_DP_CFG_PAT_SEL, val); in hibmc_dp_link_set_pattern()
87 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_PATTERN_SET, &buf, sizeof(buf)); in hibmc_dp_link_set_pattern()
89 drm_dbg_dp(dp->dev, "dp aux write training pattern set failed\n"); in hibmc_dp_link_set_pattern()
96 static int hibmc_dp_link_training_cr_pre(struct hibmc_dp_dev *dp) in hibmc_dp_link_training_cr_pre() argument
98 u8 *train_set = dp->link.train_set; in hibmc_dp_link_training_cr_pre()
102 ret = hibmc_dp_link_training_configure(dp); in hibmc_dp_link_training_cr_pre()
106 ret = hibmc_dp_link_set_pattern(dp, DP_TRAINING_PATTERN_1); in hibmc_dp_link_training_cr_pre()
110 for (i = 0; i < dp->link.cap.lanes; i++) in hibmc_dp_link_training_cr_pre()
113 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, train_set, dp->link.cap.lanes); in hibmc_dp_link_training_cr_pre()
114 if (ret != dp->link.cap.lanes) { in hibmc_dp_link_training_cr_pre()
115 drm_dbg_dp(dp->dev, "dp aux write training lane set failed\n"); in hibmc_dp_link_training_cr_pre()
122 static bool hibmc_dp_link_get_adjust_train(struct hibmc_dp_dev *dp, in hibmc_dp_link_get_adjust_train() argument
128 for (lane = 0; lane < dp->link.cap.lanes; lane++) in hibmc_dp_link_get_adjust_train()
132 if (memcmp(dp->link.train_set, train_set, HIBMC_DP_LANE_NUM_MAX)) { in hibmc_dp_link_get_adjust_train()
133 memcpy(dp->link.train_set, train_set, HIBMC_DP_LANE_NUM_MAX); in hibmc_dp_link_get_adjust_train()
140 static inline int hibmc_dp_link_reduce_rate(struct hibmc_dp_dev *dp) in hibmc_dp_link_reduce_rate() argument
142 switch (dp->link.cap.link_rate) { in hibmc_dp_link_reduce_rate()
144 dp->link.cap.link_rate = DP_LINK_BW_1_62; in hibmc_dp_link_reduce_rate()
147 dp->link.cap.link_rate = DP_LINK_BW_2_7; in hibmc_dp_link_reduce_rate()
150 dp->link.cap.link_rate = DP_LINK_BW_5_4; in hibmc_dp_link_reduce_rate()
157 static inline int hibmc_dp_link_reduce_lane(struct hibmc_dp_dev *dp) in hibmc_dp_link_reduce_lane() argument
159 switch (dp->link.cap.lanes) { in hibmc_dp_link_reduce_lane()
161 dp->link.cap.lanes--; in hibmc_dp_link_reduce_lane()
164 drm_err(dp->dev, "dp link training reduce lane failed, already reach minimum\n"); in hibmc_dp_link_reduce_lane()
173 static int hibmc_dp_link_training_cr(struct hibmc_dp_dev *dp) in hibmc_dp_link_training_cr() argument
182 * DP 1.4 spec define 10 for maxtries value, for pre DP 1.4 version set a limit of 80 in hibmc_dp_link_training_cr()
188 drm_dp_link_train_clock_recovery_delay(&dp->aux, dp->dpcd); in hibmc_dp_link_training_cr()
190 ret = drm_dp_dpcd_read_link_status(&dp->aux, lane_status); in hibmc_dp_link_training_cr()
192 drm_err(dp->dev, "Get lane status failed\n"); in hibmc_dp_link_training_cr()
196 if (drm_dp_clock_recovery_ok(lane_status, dp->link.cap.lanes)) { in hibmc_dp_link_training_cr()
197 drm_dbg_dp(dp->dev, "dp link training cr done\n"); in hibmc_dp_link_training_cr()
198 dp->link.status.clock_recovered = true; in hibmc_dp_link_training_cr()
203 drm_dbg_dp(dp->dev, "same voltage tries 5 times\n"); in hibmc_dp_link_training_cr()
204 dp->link.status.clock_recovered = false; in hibmc_dp_link_training_cr()
208 level_changed = hibmc_dp_link_get_adjust_train(dp, lane_status); in hibmc_dp_link_training_cr()
209 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->link.train_set, in hibmc_dp_link_training_cr()
210 dp->link.cap.lanes); in hibmc_dp_link_training_cr()
211 if (ret != dp->link.cap.lanes) { in hibmc_dp_link_training_cr()
212 drm_dbg_dp(dp->dev, "Update link training failed\n"); in hibmc_dp_link_training_cr()
219 drm_err(dp->dev, "dp link training clock recovery 80 times failed\n"); in hibmc_dp_link_training_cr()
220 dp->link.status.clock_recovered = false; in hibmc_dp_link_training_cr()
225 static int hibmc_dp_link_training_channel_eq(struct hibmc_dp_dev *dp) in hibmc_dp_link_training_channel_eq() argument
231 ret = hibmc_dp_link_set_pattern(dp, DP_TRAINING_PATTERN_2); in hibmc_dp_link_training_channel_eq()
236 drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd); in hibmc_dp_link_training_channel_eq()
238 ret = drm_dp_dpcd_read_link_status(&dp->aux, lane_status); in hibmc_dp_link_training_channel_eq()
240 drm_err(dp->dev, "get lane status failed\n"); in hibmc_dp_link_training_channel_eq()
244 if (!drm_dp_clock_recovery_ok(lane_status, dp->link.cap.lanes)) { in hibmc_dp_link_training_channel_eq()
245 drm_dbg_dp(dp->dev, "clock recovery check failed\n"); in hibmc_dp_link_training_channel_eq()
246 drm_dbg_dp(dp->dev, "cannot continue channel equalization\n"); in hibmc_dp_link_training_channel_eq()
247 dp->link.status.clock_recovered = false; in hibmc_dp_link_training_channel_eq()
251 if (drm_dp_channel_eq_ok(lane_status, dp->link.cap.lanes)) { in hibmc_dp_link_training_channel_eq()
252 dp->link.status.channel_equalized = true; in hibmc_dp_link_training_channel_eq()
253 drm_dbg_dp(dp->dev, "dp link training eq done\n"); in hibmc_dp_link_training_channel_eq()
257 hibmc_dp_link_get_adjust_train(dp, lane_status); in hibmc_dp_link_training_channel_eq()
258 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, in hibmc_dp_link_training_channel_eq()
259 dp->link.train_set, dp->link.cap.lanes); in hibmc_dp_link_training_channel_eq()
260 if (ret != dp->link.cap.lanes) { in hibmc_dp_link_training_channel_eq()
261 drm_dbg_dp(dp->dev, "Update link training failed\n"); in hibmc_dp_link_training_channel_eq()
268 drm_err(dp->dev, "channel equalization failed %u times\n", eq_tries); in hibmc_dp_link_training_channel_eq()
270 hibmc_dp_link_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE); in hibmc_dp_link_training_channel_eq()
275 static int hibmc_dp_link_downgrade_training_cr(struct hibmc_dp_dev *dp) in hibmc_dp_link_downgrade_training_cr() argument
277 if (hibmc_dp_link_reduce_rate(dp)) in hibmc_dp_link_downgrade_training_cr()
278 return hibmc_dp_link_reduce_lane(dp); in hibmc_dp_link_downgrade_training_cr()
283 static int hibmc_dp_link_downgrade_training_eq(struct hibmc_dp_dev *dp) in hibmc_dp_link_downgrade_training_eq() argument
285 if ((dp->link.status.clock_recovered && !dp->link.status.channel_equalized)) { in hibmc_dp_link_downgrade_training_eq()
286 if (!hibmc_dp_link_reduce_lane(dp)) in hibmc_dp_link_downgrade_training_eq()
290 return hibmc_dp_link_reduce_rate(dp); in hibmc_dp_link_downgrade_training_eq()
293 int hibmc_dp_link_training(struct hibmc_dp_dev *dp) in hibmc_dp_link_training() argument
295 struct hibmc_dp_link *link = &dp->link; in hibmc_dp_link_training()
299 ret = hibmc_dp_link_training_cr_pre(dp); in hibmc_dp_link_training()
303 ret = hibmc_dp_link_training_cr(dp); in hibmc_dp_link_training()
308 ret = hibmc_dp_link_downgrade_training_cr(dp); in hibmc_dp_link_training()
314 ret = hibmc_dp_link_training_channel_eq(dp); in hibmc_dp_link_training()
319 ret = hibmc_dp_link_downgrade_training_eq(dp); in hibmc_dp_link_training()
329 hibmc_dp_link_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE); in hibmc_dp_link_training()