Lines Matching refs:mode

11 static void hibmc_dp_set_tu(struct hibmc_dp_dev *dp, struct drm_display_mode *mode)
28 	value = (mode->clock * bpp * 5) / (61 * lane_num * rate_ks);
47 static void hibmc_dp_set_sst(struct hibmc_dp_dev *dp, struct drm_display_mode *mode)
60 	htotal_int = mode->htotal * 9947 / 10000;
61 	htotal_size = htotal_int * fclk / (HIBMC_DP_SYMBOL_PER_FCLK * (mode->clock / 1000));
63 	hblank_int = mode->htotal - mode->hdisplay - mode->hdisplay * 53 / 10000;
65 		      (mode->clock * 10 * HIBMC_DP_SYMBOL_PER_FCLK);
68 		   mode->hdisplay, mode->vdisplay, htotal_size, hblank_size);
69 	drm_dbg_dp(dp->dev, "flink_clock %u pixel_clock %d", fclk, mode->clock / 1000);
80 static void hibmc_dp_link_cfg(struct hibmc_dp_dev *dp, struct drm_display_mode *mode)
87 	vblank = mode->vtotal - mode->vdisplay;
88 	timing_delay = mode->htotal - mode->hsync_start;
89 	hstart = mode->htotal - mode->hsync_start;
90 	vstart = mode->vtotal - mode->vsync_start;
93 				 HIBMC_DP_CFG_TIMING_GEN0_HBLANK, mode->htotal - mode->hdisplay);
95 				 HIBMC_DP_CFG_TIMING_GEN0_HACTIVE, mode->hdisplay);
100 				 HIBMC_DP_CFG_TIMING_GEN0_VACTIVE, mode->vdisplay);
103 				 mode->vsync_start - mode->vdisplay);
106 				 HIBMC_DP_CFG_STREAM_HACTIVE, mode->hdisplay);
108 				 HIBMC_DP_CFG_STREAM_HBLANK, mode->htotal - mode->hdisplay);
111 				 mode->hsync_end - mode->hsync_start);
114 				 HIBMC_DP_CFG_STREAM_VACTIVE, mode->vdisplay);
119 				 mode->vsync_start - mode->vdisplay);
122 				 mode->vsync_end - mode->vsync_start);
130 				 mode->flags & DRM_MODE_FLAG_PVSYNC ? 1 : 0);
132 				 mode->flags & DRM_MODE_FLAG_PHSYNC ? 1 : 0);
138 	hibmc_dp_set_tu(dp, mode);
150 	hibmc_dp_set_sst(dp, mode);
241 int hibmc_dp_mode_set(struct hibmc_dp *dp, struct drm_display_mode *mode)
255 	hibmc_dp_link_cfg(dp_dev, mode);