Lines Matching +full:0 +full:x0a40
13 #define PSB_CR_CLKGATECTL 0x0000
16 #define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20)
18 #define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16)
20 #define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12)
22 #define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8)
24 #define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4)
25 #define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0)
26 #define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0)
27 #define _PSB_C_CLKGATECTL_CLKG_ENABLED (0)
31 #define PSB_CR_CORE_ID 0x0010
33 #define _PSB_CC_ID_ID_MASK (0xFFFF << 16)
34 #define _PSB_CC_ID_CONFIG_SHIFT (0)
35 #define _PSB_CC_ID_CONFIG_MASK (0xFFFF << 0)
37 #define PSB_CR_CORE_REVISION 0x0014
39 #define _PSB_CC_REVISION_DESIGNER_MASK (0xFF << 24)
41 #define _PSB_CC_REVISION_MAJOR_MASK (0xFF << 16)
43 #define _PSB_CC_REVISION_MINOR_MASK (0xFF << 8)
44 #define _PSB_CC_REVISION_MAINTENANCE_SHIFT (0)
45 #define _PSB_CC_REVISION_MAINTENANCE_MASK (0xFF << 0)
47 #define PSB_CR_DESIGNER_REV_FIELD1 0x0018
49 #define PSB_CR_SOFT_RESET 0x0080
56 #define _PSB_CS_RESET_BIF_RESET (1 << 0)
58 #define PSB_CR_DESIGNER_REV_FIELD2 0x001C
60 #define PSB_CR_EVENT_HOST_ENABLE2 0x0110
62 #define PSB_CR_EVENT_STATUS2 0x0118
64 #define PSB_CR_EVENT_HOST_CLEAR2 0x0114
67 #define PSB_CR_EVENT_STATUS 0x012C
69 #define PSB_CR_EVENT_HOST_ENABLE 0x0130
71 #define PSB_CR_EVENT_HOST_CLEAR 0x0134
84 #define _PSB_CE_DPM_3D_MEM_FREE (1 << 0)
87 #define PSB_USE_OFFSET_MASK 0x0007FFFF
89 #define PSB_CR_USE_CODE_BASE0 0x0A0C
90 #define PSB_CR_USE_CODE_BASE1 0x0A10
91 #define PSB_CR_USE_CODE_BASE2 0x0A14
92 #define PSB_CR_USE_CODE_BASE3 0x0A18
93 #define PSB_CR_USE_CODE_BASE4 0x0A1C
94 #define PSB_CR_USE_CODE_BASE5 0x0A20
95 #define PSB_CR_USE_CODE_BASE6 0x0A24
96 #define PSB_CR_USE_CODE_BASE7 0x0A28
97 #define PSB_CR_USE_CODE_BASE8 0x0A2C
98 #define PSB_CR_USE_CODE_BASE9 0x0A30
99 #define PSB_CR_USE_CODE_BASE10 0x0A34
100 #define PSB_CR_USE_CODE_BASE11 0x0A38
101 #define PSB_CR_USE_CODE_BASE12 0x0A3C
102 #define PSB_CR_USE_CODE_BASE13 0x0A40
103 #define PSB_CR_USE_CODE_BASE14 0x0A44
104 #define PSB_CR_USE_CODE_BASE15 0x0A48
105 #define PSB_CR_USE_CODE_BASE(_i) (0x0A0C + ((_i) << 2))
107 #define _PSB_CUC_BASE_DM_MASK (0x3 << 25)
108 #define _PSB_CUC_BASE_ADDR_SHIFT (0) /* 1024-bit aligned address? */
110 #define _PSB_CUC_BASE_ADDR_MASK (0x1FFFFFF << 0)
111 #define _PSB_CUC_DM_VERTEX (0)
116 #define PSB_CR_PDS_EXEC_BASE 0x0AB8
120 #define PSB_CR_EVENT_KICKER 0x0AC4
123 #define PSB_CR_EVENT_KICK 0x0AC8
124 #define _PSB_CE_KICK_NOW (1 << 0)
126 #define PSB_CR_BIF_DIR_LIST_BASE1 0x0C38
128 #define PSB_CR_BIF_CTRL 0x0C00
133 #define PSB_CR_BIF_INT_STAT 0x0C04
135 #define PSB_CR_BIF_FAULT 0x0C08
137 #define _PSB_CBI_STAT_FAULT_SHIFT (0)
138 #define _PSB_CBI_STAT_FAULT_MASK (0x3FFF << 0)
149 #define PSB_CR_BIF_BANK0 0x0C78
150 #define PSB_CR_BIF_BANK1 0x0C7C
151 #define PSB_CR_BIF_DIR_LIST_BASE0 0x0C84
152 #define PSB_CR_BIF_TWOD_REQ_BASE 0x0C88
153 #define PSB_CR_BIF_3D_REQ_BASE 0x0CAC
155 #define PSB_CR_2D_SOCIF 0x0E18
156 #define _PSB_C2_SOCIF_FREESPACE_SHIFT (0)
157 #define _PSB_C2_SOCIF_FREESPACE_MASK (0xFF << 0)
158 #define _PSB_C2_SOCIF_EMPTY (0x80 << 0)
160 #define PSB_CR_2D_BLIT_STATUS 0x0E04
162 #define _PSB_C2B_STATUS_COMPLETE_SHIFT (0)
163 #define _PSB_C2B_STATUS_COMPLETE_MASK (0xFFFFFF << 0)
173 #define PSB_2D_CLIP_BH (0x00000000)
174 #define PSB_2D_PAT_BH (0x10000000)
175 #define PSB_2D_CTRL_BH (0x20000000)
176 #define PSB_2D_SRC_OFF_BH (0x30000000)
177 #define PSB_2D_MASK_OFF_BH (0x40000000)
178 #define PSB_2D_RESERVED1_BH (0x50000000)
179 #define PSB_2D_RESERVED2_BH (0x60000000)
180 #define PSB_2D_FENCE_BH (0x70000000)
181 #define PSB_2D_BLIT_BH (0x80000000)
182 #define PSB_2D_SRC_SURF_BH (0x90000000)
183 #define PSB_2D_DST_SURF_BH (0xA0000000)
184 #define PSB_2D_PAT_SURF_BH (0xB0000000)
185 #define PSB_2D_SRC_PAL_BH (0xC0000000)
186 #define PSB_2D_PAT_PAL_BH (0xD0000000)
187 #define PSB_2D_MASK_SURF_BH (0xE0000000)
188 #define PSB_2D_FLUSH_BH (0xF0000000)
194 #define PSB_2D_CLIPCOUNT_MASK (0x00000000)
195 #define PSB_2D_CLIPCOUNT_CLRMASK (0xFFFFFFFF)
196 #define PSB_2D_CLIPCOUNT_SHIFT (0)
198 #define PSB_2D_CLIP_XMAX_MASK (0x00FFF000)
199 #define PSB_2D_CLIP_XMAX_CLRMASK (0xFF000FFF)
201 #define PSB_2D_CLIP_XMIN_MASK (0x00000FFF)
202 #define PSB_2D_CLIP_XMIN_CLRMASK (0x00FFF000)
203 #define PSB_2D_CLIP_XMIN_SHIFT (0)
205 #define PSB_2D_CLIP_YMAX_MASK (0x00FFF000)
206 #define PSB_2D_CLIP_YMAX_CLRMASK (0xFF000FFF)
208 #define PSB_2D_CLIP_YMIN_MASK (0x00000FFF)
209 #define PSB_2D_CLIP_YMIN_CLRMASK (0x00FFF000)
210 #define PSB_2D_CLIP_YMIN_SHIFT (0)
215 #define PSB_2D_PAT_HEIGHT_MASK (0x0000001F)
216 #define PSB_2D_PAT_HEIGHT_SHIFT (0)
217 #define PSB_2D_PAT_WIDTH_MASK (0x000003E0)
219 #define PSB_2D_PAT_YSTART_MASK (0x00007C00)
221 #define PSB_2D_PAT_XSTART_MASK (0x000F8000)
228 #define PSB_2D_SRCCK_CTRL (0x00000001)
229 #define PSB_2D_DSTCK_CTRL (0x00000002)
230 #define PSB_2D_ALPHA_CTRL (0x00000004)
232 #define PSB_2D_CK_COL_MASK (0xFFFFFFFF)
233 #define PSB_2D_CK_COL_CLRMASK (0x00000000)
234 #define PSB_2D_CK_COL_SHIFT (0)
236 #define PSB_2D_CK_MASK_MASK (0xFFFFFFFF)
237 #define PSB_2D_CK_MASK_CLRMASK (0x00000000)
238 #define PSB_2D_CK_MASK_SHIFT (0)
240 #define PSB_2D_GBLALPHA_MASK (0x000FF000)
241 #define PSB_2D_GBLALPHA_CLRMASK (0xFFF00FFF)
243 #define PSB_2D_SRCALPHA_OP_MASK (0x00700000)
244 #define PSB_2D_SRCALPHA_OP_CLRMASK (0xFF8FFFFF)
246 #define PSB_2D_SRCALPHA_OP_ONE (0x00000000)
247 #define PSB_2D_SRCALPHA_OP_SRC (0x00100000)
248 #define PSB_2D_SRCALPHA_OP_DST (0x00200000)
249 #define PSB_2D_SRCALPHA_OP_SG (0x00300000)
250 #define PSB_2D_SRCALPHA_OP_DG (0x00400000)
251 #define PSB_2D_SRCALPHA_OP_GBL (0x00500000)
252 #define PSB_2D_SRCALPHA_OP_ZERO (0x00600000)
253 #define PSB_2D_SRCALPHA_INVERT (0x00800000)
254 #define PSB_2D_SRCALPHA_INVERT_CLR (0xFF7FFFFF)
255 #define PSB_2D_DSTALPHA_OP_MASK (0x07000000)
256 #define PSB_2D_DSTALPHA_OP_CLRMASK (0xF8FFFFFF)
258 #define PSB_2D_DSTALPHA_OP_ONE (0x00000000)
259 #define PSB_2D_DSTALPHA_OP_SRC (0x01000000)
260 #define PSB_2D_DSTALPHA_OP_DST (0x02000000)
261 #define PSB_2D_DSTALPHA_OP_SG (0x03000000)
262 #define PSB_2D_DSTALPHA_OP_DG (0x04000000)
263 #define PSB_2D_DSTALPHA_OP_GBL (0x05000000)
264 #define PSB_2D_DSTALPHA_OP_ZERO (0x06000000)
265 #define PSB_2D_DSTALPHA_INVERT (0x08000000)
266 #define PSB_2D_DSTALPHA_INVERT_CLR (0xF7FFFFFF)
268 #define PSB_2D_PRE_MULTIPLICATION_ENABLE (0x10000000)
269 #define PSB_2D_PRE_MULTIPLICATION_CLRMASK (0xEFFFFFFF)
270 #define PSB_2D_ZERO_SOURCE_ALPHA_ENABLE (0x20000000)
271 #define PSB_2D_ZERO_SOURCE_ALPHA_CLRMASK (0xDFFFFFFF)
276 #define PSB_2D_SRCOFF_XSTART_MASK ((0x00000FFF) << 12)
278 #define PSB_2D_SRCOFF_YSTART_MASK (0x00000FFF)
279 #define PSB_2D_SRCOFF_YSTART_SHIFT (0)
284 #define PSB_2D_MASKOFF_XSTART_MASK ((0x00000FFF) << 12)
286 #define PSB_2D_MASKOFF_YSTART_MASK (0x00000FFF)
287 #define PSB_2D_MASKOFF_YSTART_SHIFT (0)
290 * 2D Fence (see PSB_2D_FENCE_BH): bits 0:27 are ignored
299 #define PSB_2D_ROT_NONE (0 << 25)
306 #define PSB_2D_COPYORDER_TL2BR (0 << 23)
311 #define PSB_2D_DSTCK_CLRMASK (0xFF9FFFFF)
312 #define PSB_2D_DSTCK_DISABLE (0x00000000)
313 #define PSB_2D_DSTCK_PASS (0x00200000)
314 #define PSB_2D_DSTCK_REJECT (0x00400000)
316 #define PSB_2D_SRCCK_CLRMASK (0xFFE7FFFF)
317 #define PSB_2D_SRCCK_DISABLE (0x00000000)
318 #define PSB_2D_SRCCK_PASS (0x00080000)
319 #define PSB_2D_SRCCK_REJECT (0x00100000)
321 #define PSB_2D_CLIP_ENABLE (0x00040000)
323 #define PSB_2D_ALPHA_ENABLE (0x00020000)
325 #define PSB_2D_PAT_CLRMASK (0xFFFEFFFF)
326 #define PSB_2D_PAT_MASK (0x00010000)
327 #define PSB_2D_USE_PAT (0x00010000)
328 #define PSB_2D_USE_FILL (0x00000000)
335 #define PSB_2D_ROP3B_MASK (0x0000FF00)
336 #define PSB_2D_ROP3B_CLRMASK (0xFFFF00FF)
339 #define PSB_2D_ROP3A_MASK (0x000000FF)
340 #define PSB_2D_ROP3A_CLRMASK (0xFFFFFF00)
341 #define PSB_2D_ROP3A_SHIFT (0)
343 #define PSB_2D_ROP4_MASK (0x0000FFFF)
348 #define PSB_2D_FILLCOLOUR_MASK (0xFFFFFFFF)
349 #define PSB_2D_FILLCOLOUR_SHIFT (0)
355 #define PSB_2D_DST_XSTART_MASK (0x00FFF000)
356 #define PSB_2D_DST_XSTART_CLRMASK (0xFF000FFF)
358 #define PSB_2D_DST_YSTART_MASK (0x00000FFF)
359 #define PSB_2D_DST_YSTART_CLRMASK (0xFFFFF000)
360 #define PSB_2D_DST_YSTART_SHIFT (0)
366 #define PSB_2D_DST_XSIZE_MASK (0x00FFF000)
367 #define PSB_2D_DST_XSIZE_CLRMASK (0xFF000FFF)
369 #define PSB_2D_DST_YSIZE_MASK (0x00000FFF)
370 #define PSB_2D_DST_YSIZE_CLRMASK (0xFFFFF000)
371 #define PSB_2D_DST_YSIZE_SHIFT (0)
377 * WORD 0
380 #define PSB_2D_SRC_FORMAT_MASK (0x00078000)
381 #define PSB_2D_SRC_1_PAL (0x00000000)
382 #define PSB_2D_SRC_2_PAL (0x00008000)
383 #define PSB_2D_SRC_4_PAL (0x00010000)
384 #define PSB_2D_SRC_8_PAL (0x00018000)
385 #define PSB_2D_SRC_8_ALPHA (0x00020000)
386 #define PSB_2D_SRC_4_ALPHA (0x00028000)
387 #define PSB_2D_SRC_332RGB (0x00030000)
388 #define PSB_2D_SRC_4444ARGB (0x00038000)
389 #define PSB_2D_SRC_555RGB (0x00040000)
390 #define PSB_2D_SRC_1555ARGB (0x00048000)
391 #define PSB_2D_SRC_565RGB (0x00050000)
392 #define PSB_2D_SRC_0888ARGB (0x00058000)
393 #define PSB_2D_SRC_8888ARGB (0x00060000)
394 #define PSB_2D_SRC_8888UYVY (0x00068000)
395 #define PSB_2D_SRC_RESERVED (0x00070000)
396 #define PSB_2D_SRC_1555ARGB_LOOKUP (0x00078000)
399 #define PSB_2D_SRC_STRIDE_MASK (0x00007FFF)
400 #define PSB_2D_SRC_STRIDE_CLRMASK (0xFFFF8000)
401 #define PSB_2D_SRC_STRIDE_SHIFT (0)
405 #define PSB_2D_SRC_ADDR_MASK (0x0FFFFFFC)
406 #define PSB_2D_SRC_ADDR_CLRMASK (0x00000003)
414 * WORD 0
417 #define PSB_2D_PAT_FORMAT_MASK (0x00078000)
418 #define PSB_2D_PAT_1_PAL (0x00000000)
419 #define PSB_2D_PAT_2_PAL (0x00008000)
420 #define PSB_2D_PAT_4_PAL (0x00010000)
421 #define PSB_2D_PAT_8_PAL (0x00018000)
422 #define PSB_2D_PAT_8_ALPHA (0x00020000)
423 #define PSB_2D_PAT_4_ALPHA (0x00028000)
424 #define PSB_2D_PAT_332RGB (0x00030000)
425 #define PSB_2D_PAT_4444ARGB (0x00038000)
426 #define PSB_2D_PAT_555RGB (0x00040000)
427 #define PSB_2D_PAT_1555ARGB (0x00048000)
428 #define PSB_2D_PAT_565RGB (0x00050000)
429 #define PSB_2D_PAT_0888ARGB (0x00058000)
430 #define PSB_2D_PAT_8888ARGB (0x00060000)
432 #define PSB_2D_PAT_STRIDE_MASK (0x00007FFF)
433 #define PSB_2D_PAT_STRIDE_CLRMASK (0xFFFF8000)
434 #define PSB_2D_PAT_STRIDE_SHIFT (0)
438 #define PSB_2D_PAT_ADDR_MASK (0x0FFFFFFC)
439 #define PSB_2D_PAT_ADDR_CLRMASK (0x00000003)
447 * WORD 0
450 #define PSB_2D_DST_FORMAT_MASK (0x00078000)
451 #define PSB_2D_DST_332RGB (0x00030000)
452 #define PSB_2D_DST_4444ARGB (0x00038000)
453 #define PSB_2D_DST_555RGB (0x00040000)
454 #define PSB_2D_DST_1555ARGB (0x00048000)
455 #define PSB_2D_DST_565RGB (0x00050000)
456 #define PSB_2D_DST_0888ARGB (0x00058000)
457 #define PSB_2D_DST_8888ARGB (0x00060000)
458 #define PSB_2D_DST_8888AYUV (0x00070000)
460 #define PSB_2D_DST_STRIDE_MASK (0x00007FFF)
461 #define PSB_2D_DST_STRIDE_CLRMASK (0xFFFF8000)
462 #define PSB_2D_DST_STRIDE_SHIFT (0)
466 #define PSB_2D_DST_ADDR_MASK (0x0FFFFFFC)
467 #define PSB_2D_DST_ADDR_CLRMASK (0x00000003)
475 * WORD 0
477 #define PSB_2D_MASK_STRIDE_MASK (0x00007FFF)
478 #define PSB_2D_MASK_STRIDE_CLRMASK (0xFFFF8000)
479 #define PSB_2D_MASK_STRIDE_SHIFT (0)
483 #define PSB_2D_MASK_ADDR_MASK (0x0FFFFFFC)
484 #define PSB_2D_MASK_ADDR_CLRMASK (0x00000003)
492 #define PSB_2D_SRCPAL_ADDR_SHIFT (0)
493 #define PSB_2D_SRCPAL_ADDR_CLRMASK (0xF0000007)
494 #define PSB_2D_SRCPAL_ADDR_MASK (0x0FFFFFF8)
501 #define PSB_2D_PATPAL_ADDR_SHIFT (0)
502 #define PSB_2D_PATPAL_ADDR_CLRMASK (0xF0000007)
503 #define PSB_2D_PATPAL_ADDR_MASK (0x0FFFFFF8)
510 #define PSB_2D_ROP3_SRCCOPY (0xCCCC)
511 #define PSB_2D_ROP3_PATCOPY (0xF0F0)
512 #define PSB_2D_ROP3_WHITENESS (0xFFFF)
513 #define PSB_2D_ROP3_BLACKNESS (0x0000)
514 #define PSB_2D_ROP3_SRC (0xCC)
515 #define PSB_2D_ROP3_PAT (0xF0)
516 #define PSB_2D_ROP3_DST (0xAA)
535 #define PSB_RASTER_BLOCK 0
541 #define PSB_PUNIT_PORT 0x04
542 #define PSB_OSPMBA 0x78
543 #define PSB_APMBA 0x7a
544 #define PSB_APM_CMD 0x0
545 #define PSB_APM_STS 0x04
546 #define PSB_PWRGT_VID_ENC_MASK 0x30
547 #define PSB_PWRGT_VID_DEC_MASK 0xc
548 #define PSB_PWRGT_GL3_MASK 0xc0
550 #define PSB_PM_SSC 0x20
551 #define PSB_PM_SSS 0x30
552 #define PSB_PWRGT_DISPLAY_MASK 0xc /*on a different BA than video/gfx*/
554 #define PSB_PWRGT_GFX_MASK 0x3
555 #define PSB_PWRGT_GFX_MASK_B0 0xc3