Lines Matching +full:lvds +full:- +full:encoder
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
48 /* The single-channel range is 25-112Mhz, and dual-channel
49 * is 80-224Mhz. Prefer single channel as much as possible.
70 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); in psb_intel_clock()
71 clock->p = clock->p1 * clock->p2; in psb_intel_clock()
72 clock->vco = refclk * clock->m / (clock->n + 2); in psb_intel_clock()
73 clock->dot = clock->vco / clock->p; in psb_intel_clock()
78 * or -1 if the panel fitter is not present or not in use
88 return -1; in psb_intel_panel_fitter_pipe()
99 struct drm_device *dev = crtc->dev; in psb_intel_crtc_mode_set()
102 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; in psb_intel_crtc_mode_set()
103 int pipe = gma_crtc->pipe; in psb_intel_crtc_mode_set()
104 const struct psb_offset *map = &dev_priv->regmap[pipe]; in psb_intel_crtc_mode_set()
115 if (crtc->primary->fb == NULL) { in psb_intel_crtc_mode_set()
116 crtc_funcs->mode_set_base(crtc, x, y, old_fb); in psb_intel_crtc_mode_set()
124 if (!connector->encoder in psb_intel_crtc_mode_set()
125 || connector->encoder->crtc != crtc) in psb_intel_crtc_mode_set()
128 switch (gma_encoder->type) { in psb_intel_crtc_mode_set()
146 limit = gma_crtc->clock_funcs->limit(crtc, refclk); in psb_intel_crtc_mode_set()
148 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, in psb_intel_crtc_mode_set()
152 adjusted_mode->clock, clock.dot); in psb_intel_crtc_mode_set()
166 adjusted_mode->clock / mode->clock; in psb_intel_crtc_mode_set()
169 (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; in psb_intel_crtc_mode_set()
173 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
197 pipeconf = REG_READ(map->conf); in psb_intel_crtc_mode_set()
219 REG_WRITE(map->fp0, fp); in psb_intel_crtc_mode_set()
220 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); in psb_intel_crtc_mode_set()
221 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
225 /* The LVDS pin pair needs to be on before the DPLLs are enabled. in psb_intel_crtc_mode_set()
230 u32 lvds = REG_READ(LVDS); in psb_intel_crtc_mode_set() local
232 lvds &= ~LVDS_PIPEB_SELECT; in psb_intel_crtc_mode_set()
234 lvds |= LVDS_PIPEB_SELECT; in psb_intel_crtc_mode_set()
236 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; in psb_intel_crtc_mode_set()
237 /* Set the B0-B3 data pairs corresponding to in psb_intel_crtc_mode_set()
239 * set the DPLLs for dual-channel mode or not. in psb_intel_crtc_mode_set()
241 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); in psb_intel_crtc_mode_set()
243 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; in psb_intel_crtc_mode_set()
245 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) in psb_intel_crtc_mode_set()
250 REG_WRITE(LVDS, lvds); in psb_intel_crtc_mode_set()
251 REG_READ(LVDS); in psb_intel_crtc_mode_set()
254 REG_WRITE(map->fp0, fp); in psb_intel_crtc_mode_set()
255 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set()
256 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
260 /* write it again -- the BIOS does, after all */ in psb_intel_crtc_mode_set()
261 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set()
263 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
267 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | in psb_intel_crtc_mode_set()
268 ((adjusted_mode->crtc_htotal - 1) << 16)); in psb_intel_crtc_mode_set()
269 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | in psb_intel_crtc_mode_set()
270 ((adjusted_mode->crtc_hblank_end - 1) << 16)); in psb_intel_crtc_mode_set()
271 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | in psb_intel_crtc_mode_set()
272 ((adjusted_mode->crtc_hsync_end - 1) << 16)); in psb_intel_crtc_mode_set()
273 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | in psb_intel_crtc_mode_set()
274 ((adjusted_mode->crtc_vtotal - 1) << 16)); in psb_intel_crtc_mode_set()
275 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | in psb_intel_crtc_mode_set()
276 ((adjusted_mode->crtc_vblank_end - 1) << 16)); in psb_intel_crtc_mode_set()
277 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | in psb_intel_crtc_mode_set()
278 ((adjusted_mode->crtc_vsync_end - 1) << 16)); in psb_intel_crtc_mode_set()
282 REG_WRITE(map->size, in psb_intel_crtc_mode_set()
283 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); in psb_intel_crtc_mode_set()
284 REG_WRITE(map->pos, 0); in psb_intel_crtc_mode_set()
285 REG_WRITE(map->src, in psb_intel_crtc_mode_set()
286 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); in psb_intel_crtc_mode_set()
287 REG_WRITE(map->conf, pipeconf); in psb_intel_crtc_mode_set()
288 REG_READ(map->conf); in psb_intel_crtc_mode_set()
292 REG_WRITE(map->cntr, dspcntr); in psb_intel_crtc_mode_set()
295 crtc_funcs->mode_set_base(crtc, x, y, old_fb); in psb_intel_crtc_mode_set()
308 int pipe = gma_crtc->pipe; in psb_intel_crtc_clock_get()
309 const struct psb_offset *map = &dev_priv->regmap[pipe]; in psb_intel_crtc_clock_get()
314 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; in psb_intel_crtc_clock_get()
317 dpll = REG_READ(map->dpll); in psb_intel_crtc_clock_get()
319 fp = REG_READ(map->fp0); in psb_intel_crtc_clock_get()
321 fp = REG_READ(map->fp1); in psb_intel_crtc_clock_get()
322 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); in psb_intel_crtc_clock_get()
325 dpll = p->dpll; in psb_intel_crtc_clock_get()
328 fp = p->fp0; in psb_intel_crtc_clock_get()
330 fp = p->fp1; in psb_intel_crtc_clock_get()
332 is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS & in psb_intel_crtc_clock_get()
383 int pipe = gma_crtc->pipe; in psb_intel_crtc_mode_get()
390 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; in psb_intel_crtc_mode_get()
391 const struct psb_offset *map = &dev_priv->regmap[pipe]; in psb_intel_crtc_mode_get()
394 htot = REG_READ(map->htotal); in psb_intel_crtc_mode_get()
395 hsync = REG_READ(map->hsync); in psb_intel_crtc_mode_get()
396 vtot = REG_READ(map->vtotal); in psb_intel_crtc_mode_get()
397 vsync = REG_READ(map->vsync); in psb_intel_crtc_mode_get()
400 htot = p->htotal; in psb_intel_crtc_mode_get()
401 hsync = p->hsync; in psb_intel_crtc_mode_get()
402 vtot = p->vtotal; in psb_intel_crtc_mode_get()
403 vsync = p->vsync; in psb_intel_crtc_mode_get()
410 mode->clock = psb_intel_crtc_clock_get(dev, crtc); in psb_intel_crtc_mode_get()
411 mode->hdisplay = (htot & 0xffff) + 1; in psb_intel_crtc_mode_get()
412 mode->htotal = ((htot & 0xffff0000) >> 16) + 1; in psb_intel_crtc_mode_get()
413 mode->hsync_start = (hsync & 0xffff) + 1; in psb_intel_crtc_mode_get()
414 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; in psb_intel_crtc_mode_get()
415 mode->vdisplay = (vtot & 0xffff) + 1; in psb_intel_crtc_mode_get()
416 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; in psb_intel_crtc_mode_get()
417 mode->vsync_start = (vsync & 0xffff) + 1; in psb_intel_crtc_mode_get()
418 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; in psb_intel_crtc_mode_get()
453 if (dev_priv->ops->cursor_needs_phys) { in psb_intel_cursor_init()
459 gma_crtc->cursor_pobj = NULL; in psb_intel_cursor_init()
462 gma_crtc->cursor_pobj = cursor_pobj; in psb_intel_cursor_init()
463 gma_crtc->cursor_addr = dev_priv->stolen_base + cursor_pobj->offset; in psb_intel_cursor_init()
465 gma_crtc->cursor_pobj = NULL; in psb_intel_cursor_init()
469 REG_WRITE(control[gma_crtc->pipe], 0); in psb_intel_cursor_init()
470 REG_WRITE(base[gma_crtc->pipe], 0); in psb_intel_cursor_init()
488 gma_crtc->crtc_state = in psb_intel_crtc_init()
490 if (!gma_crtc->crtc_state) { in psb_intel_crtc_init()
491 dev_err(dev->dev, "Crtc state error: No memory\n"); in psb_intel_crtc_init()
496 drm_crtc_init(dev, &gma_crtc->base, &gma_crtc_funcs); in psb_intel_crtc_init()
499 gma_crtc->clock_funcs = dev_priv->ops->clock_funcs; in psb_intel_crtc_init()
501 drm_mode_crtc_set_gamma_size(&gma_crtc->base, 256); in psb_intel_crtc_init()
502 gma_crtc->pipe = pipe; in psb_intel_crtc_init()
503 gma_crtc->plane = pipe; in psb_intel_crtc_init()
506 gma_crtc->lut_adj[i] = 0; in psb_intel_crtc_init()
508 gma_crtc->mode_dev = mode_dev; in psb_intel_crtc_init()
509 gma_crtc->cursor_addr = 0; in psb_intel_crtc_init()
511 drm_crtc_helper_add(&gma_crtc->base, in psb_intel_crtc_init()
512 dev_priv->ops->crtc_helper); in psb_intel_crtc_init()
515 gma_crtc->mode_set.crtc = &gma_crtc->base; in psb_intel_crtc_init()
516 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || in psb_intel_crtc_init()
517 dev_priv->plane_to_crtc_mapping[gma_crtc->plane] != NULL); in psb_intel_crtc_init()
518 dev_priv->plane_to_crtc_mapping[gma_crtc->plane] = &gma_crtc->base; in psb_intel_crtc_init()
519 dev_priv->pipe_to_crtc_mapping[gma_crtc->pipe] = &gma_crtc->base; in psb_intel_crtc_init()
520 gma_crtc->mode_set.connectors = (struct drm_connector **)(gma_crtc + 1); in psb_intel_crtc_init()
521 gma_crtc->mode_set.num_connectors = 0; in psb_intel_crtc_init()
525 gma_crtc->active = true; in psb_intel_crtc_init()
532 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { in psb_intel_get_crtc_from_pipe()
535 if (gma_crtc->pipe == pipe) in psb_intel_get_crtc_from_pipe()
551 if (type_mask & (1 << gma_encoder->type)) in gma_connector_clones()