Lines Matching +full:lvds +full:- +full:4 +full:bits

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * Copyright (c) 2007-2011, Intel Corporation.
37 #define IS_PSB(drm) ((to_pci_dev((drm)->dev)->device & 0xfffe) == 0x8108)
38 #define IS_MRST(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x4100)
39 #define IS_CDV(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x0be0)
86 /* VDC registers and bits */
95 #define _PSB_DPST_PIPEB_FLAG      (1<<4)
96 #define _MDFLD_PIPEB_EVENT_FLAG   (1<<4)
128 #define GPIO_CLOCK_VAL_IN		(1 << 4)
142 #define PSB_COMM_2D (PSB_ENGINE_2D << 4)
143 #define PSB_COMM_3D (PSB_ENGINE_3D << 4)
144 #define PSB_COMM_TA (PSB_ENGINE_TA << 4)
145 #define PSB_COMM_HP (PSB_ENGINE_HP << 4)
153 #define PSB_UIRQ_FIRE_RASTER_REPLY     4
456 	/* LVDS info */
463 	struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
466 	/* Feature bits from the VBIOS */
503 	 * xrandr -- consider removing and using HAL instead
551 	int lvds_mask;		/* Mask of LVDS CRTCs */
651 	return ioread32(dev_priv->vdc_reg + reg);  in REGISTER_READ()
657 	return ioread32(dev_priv->aux_reg + reg);  in REGISTER_READ_AUX()
683 	iowrite32((val), dev_priv->vdc_reg + (reg));  in REGISTER_WRITE()
690 	iowrite32((val), dev_priv->aux_reg + (reg));  in REGISTER_WRITE_AUX()
711 	iowrite16((val), dev_priv->vdc_reg + (reg));  in REGISTER_WRITE16()
720 	iowrite8((val), dev_priv->vdc_reg + (reg));  in REGISTER_WRITE8()
725 #define PSB_WVDC32(_val, _offs)		iowrite32(_val, dev_priv->vdc_reg + (_offs))
726 #define PSB_RVDC32(_offs)		ioread32(dev_priv->vdc_reg + (_offs))
728 #define PSB_RSGX32(_offs)		ioread32(dev_priv->sgx_reg + (_offs))
729 #define PSB_WSGX32(_val, _offs)		iowrite32(_val, dev_priv->sgx_reg + (_offs))
731 #define PSB_WMSVDX32(_val, _offs)	iowrite32(_val, dev_priv->msvdx_reg + (_offs))
732 #define PSB_RMSVDX32(_offs)		ioread32(dev_priv->msvdx_reg + (_offs))