Lines Matching +full:no +full:- +full:temp +full:- +full:support
1 // SPDX-License-Identifier: GPL-2.0-only
87 struct drm_device *dev = crtc->dev;
92 switch (dev_priv->core_freq) {
107 dev_err(dev->dev, "mrst_limit Wrong display type.\n");
116 clock->dot = (refclk * clock->m) / (14 * clock->p1);
122 clock->dot, clock->m, clock->m1, clock->m2, clock->n,
123 clock->p1, clock->p2);
137 for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) {
138 for (clock.n = limit->n.min; clock.n <= limit->n.max;
140 for (clock.p1 = limit->p1.min;
141 clock.p1 <= limit->p1.max; clock.p1++) {
143 clock.p = clock.p1 * limit->p2.p2_slow;
147 if (target_vco > limit->vco.max)
150 if (target_vco < limit->vco.min)
155 freq_error = 10000 -
158 if (freq_error < -min_error) {
165 freq_error = -freq_error;
194 for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) {
195 for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max;
201 this_err = abs(clock.dot - target);
214 * This code should probably grow support for turning the cursor off and back
219 struct drm_device *dev = crtc->dev;
222 int pipe = gma_crtc->pipe;
223 const struct psb_offset *map = &dev_priv->regmap[pipe];
224 u32 temp;
245 temp = REG_READ_WITH_AUX(map->dpll, i);
246 if ((temp & DPLL_VCO_ENABLE) == 0) {
247 REG_WRITE_WITH_AUX(map->dpll, temp, i);
248 REG_READ_WITH_AUX(map->dpll, i);
251 REG_WRITE_WITH_AUX(map->dpll,
252 temp | DPLL_VCO_ENABLE, i);
253 REG_READ_WITH_AUX(map->dpll, i);
256 REG_WRITE_WITH_AUX(map->dpll,
257 temp | DPLL_VCO_ENABLE, i);
258 REG_READ_WITH_AUX(map->dpll, i);
264 temp = REG_READ_WITH_AUX(map->conf, i);
265 if ((temp & PIPEACONF_ENABLE) == 0) {
266 REG_WRITE_WITH_AUX(map->conf,
267 temp | PIPEACONF_ENABLE, i);
271 temp = REG_READ_WITH_AUX(map->cntr, i);
272 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
273 REG_WRITE_WITH_AUX(map->cntr,
274 temp | DISPLAY_PLANE_ENABLE,
277 REG_WRITE_WITH_AUX(map->base,
278 REG_READ_WITH_AUX(map->base, i), i);
297 temp = REG_READ_WITH_AUX(map->cntr, i);
298 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
299 REG_WRITE_WITH_AUX(map->cntr,
300 temp & ~DISPLAY_PLANE_ENABLE, i);
302 REG_WRITE_WITH_AUX(map->base,
303 REG_READ(map->base), i);
304 REG_READ_WITH_AUX(map->base, i);
308 temp = REG_READ_WITH_AUX(map->conf, i);
309 if ((temp & PIPEACONF_ENABLE) != 0) {
310 REG_WRITE_WITH_AUX(map->conf,
311 temp & ~PIPEACONF_ENABLE, i);
312 REG_READ_WITH_AUX(map->conf, i);
317 temp = REG_READ_WITH_AUX(map->dpll, i);
318 if ((temp & DPLL_VCO_ENABLE) != 0) {
319 REG_WRITE_WITH_AUX(map->dpll,
320 temp & ~DPLL_VCO_ENABLE, i);
321 REG_READ_WITH_AUX(map->dpll, i);
345 * or -1 if the panel fitter is not present or not in use
355 return -1;
365 struct drm_device *dev = crtc->dev;
368 int pipe = gma_crtc->pipe;
369 const struct psb_offset *map = &dev_priv->regmap[pipe];
390 drm_mode_copy(&gma_crtc->saved_mode, mode);
391 drm_mode_copy(&gma_crtc->saved_adjusted_mode, adjusted_mode);
395 if (!connector->encoder || connector->encoder->crtc != crtc)
400 switch (gma_encoder->type) {
416 drm_object_property_get_value(&connector->base,
417 dev->mode_config.scaling_mode_property, &scalingType);
430 REG_WRITE_WITH_AUX(map->src, ((mode->crtc_hdisplay - 1) << 16) |
431 (mode->crtc_vdisplay - 1), i);
435 /* Moorestown doesn't have register support for centering so
440 offsetX = (adjusted_mode->crtc_hdisplay -
441 mode->crtc_hdisplay) / 2;
442 offsetY = (adjusted_mode->crtc_vdisplay -
443 mode->crtc_vdisplay) / 2;
446 REG_WRITE_WITH_AUX(map->htotal, (mode->crtc_hdisplay - 1) |
447 ((adjusted_mode->crtc_htotal - 1) << 16), i);
448 REG_WRITE_WITH_AUX(map->vtotal, (mode->crtc_vdisplay - 1) |
449 ((adjusted_mode->crtc_vtotal - 1) << 16), i);
450 REG_WRITE_WITH_AUX(map->hblank,
451 (adjusted_mode->crtc_hblank_start - offsetX - 1) |
452 ((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16), i);
453 REG_WRITE_WITH_AUX(map->hsync,
454 (adjusted_mode->crtc_hsync_start - offsetX - 1) |
455 ((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16), i);
456 REG_WRITE_WITH_AUX(map->vblank,
457 (adjusted_mode->crtc_vblank_start - offsetY - 1) |
458 ((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16), i);
459 REG_WRITE_WITH_AUX(map->vsync,
460 (adjusted_mode->crtc_vsync_start - offsetY - 1) |
461 ((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16), i);
465 REG_WRITE_WITH_AUX(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
466 ((adjusted_mode->crtc_htotal - 1) << 16), i);
467 REG_WRITE_WITH_AUX(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
468 ((adjusted_mode->crtc_vtotal - 1) << 16), i);
469 REG_WRITE_WITH_AUX(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
470 ((adjusted_mode->crtc_hblank_end - 1) << 16), i);
471 REG_WRITE_WITH_AUX(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
472 ((adjusted_mode->crtc_hsync_end - 1) << 16), i);
473 REG_WRITE_WITH_AUX(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
474 ((adjusted_mode->crtc_vblank_end - 1) << 16), i);
475 REG_WRITE_WITH_AUX(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
476 ((adjusted_mode->crtc_vsync_end - 1) << 16), i);
483 crtc->helper_private;
484 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
488 pipeconf = REG_READ(map->conf);
491 dspcntr = REG_READ(map->cntr);
505 refclk = is_sdvo ? 96000 : dev_priv->core_freq * 1000;
507 ok = limit->find_pll(limit, crtc, adjusted_mode->clock,
512 clock.p1 = (1L << (clock.p1 - 1));
513 clock.m -= 2;
514 clock.n = (1L << (clock.n - 1));
525 fp = oaktrail_m_converts[(clock.m - MRST_M_MIN)] << 8;
539 adjusted_mode->clock / mode->clock;
543 (sdvo_pixel_multiply -
550 dpll |= clock.p1 << 16; // dpll |= (1 << (clock.p1 - 1)) << 16;
552 dpll |= (1 << (clock.p1 - 2)) << 17;
558 REG_WRITE_WITH_AUX(map->fp0, fp, i);
559 REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i);
560 REG_READ_WITH_AUX(map->dpll, i);
567 REG_WRITE_WITH_AUX(map->fp0, fp, i);
568 REG_WRITE_WITH_AUX(map->dpll, dpll, i);
569 REG_READ_WITH_AUX(map->dpll, i);
573 /* write it again -- the BIOS does, after all */
574 REG_WRITE_WITH_AUX(map->dpll, dpll, i);
575 REG_READ_WITH_AUX(map->dpll, i);
579 REG_WRITE_WITH_AUX(map->conf, pipeconf, i);
580 REG_READ_WITH_AUX(map->conf, i);
583 REG_WRITE_WITH_AUX(map->cntr, dspcntr, i);
595 struct drm_device *dev = crtc->dev;
598 struct drm_framebuffer *fb = crtc->primary->fb;
599 int pipe = gma_crtc->pipe;
600 const struct psb_offset *map = &dev_priv->regmap[pipe];
606 /* no fb bound */
608 dev_dbg(dev->dev, "No FB bound\n");
615 start = to_psb_gem_object(fb->obj[0])->offset;
616 offset = y * fb->pitches[0] + x * fb->format->cpp[0];
618 REG_WRITE(map->stride, fb->pitches[0]);
620 dspcntr = REG_READ(map->cntr);
623 switch (fb->format->cpp[0] * 8) {
628 if (fb->format->depth == 15)
638 dev_err(dev->dev, "Unknown color depth\n");
639 ret = -EINVAL;
642 REG_WRITE(map->cntr, dspcntr);
644 REG_WRITE(map->base, offset);
645 REG_READ(map->base);
646 REG_WRITE(map->surf, start);
647 REG_READ(map->surf);