23 #define MRST_LIMIT_LVDS_83	1
51 	 .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1},
57 	 .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_0},
63 	 .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1},
70 	 .p1 = {.min = 1, .max = 2},
116 	clock->dot = (refclk * clock->m) / (14 * clock->p1);  in mrst_lvds_clock()
121 	DRM_DEBUG_DRIVER("dotclock=%d,  m=%d, m1=%d, m2=%d, n=%d, p1=%d, p2=%d\n",  in mrst_print_pll()
123 			 clock->p1, clock->p2);  in mrst_print_pll()
140 			for (clock.p1 = limit->p1.min;  in mrst_sdvo_find_best_pll()
141 			     clock.p1 <= limit->p1.max; clock.p1++) {  in mrst_sdvo_find_best_pll()
143 				clock.p = clock.p1 * limit->p2.p2_slow;  in mrst_sdvo_find_best_pll()
195 		for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max;  in mrst_lvds_find_best_pll()
196 		     clock.p1++) {  in mrst_lvds_find_best_pll()
226 	int need_aux = gma_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ? 1 : 0;  in oaktrail_crtc_dpms()
345  * or -1 if the panel fitter is not present or not in use
355 		return -1;  in oaktrail_panel_fitter_pipe()
382 	int need_aux = gma_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ? 1 : 0;  in oaktrail_crtc_mode_set()
430 		REG_WRITE_WITH_AUX(map->src, ((mode->crtc_hdisplay - 1) << 16) |  in oaktrail_crtc_mode_set()
431 					     (mode->crtc_vdisplay - 1), i);  in oaktrail_crtc_mode_set()
446 			REG_WRITE_WITH_AUX(map->htotal, (mode->crtc_hdisplay - 1) |  in oaktrail_crtc_mode_set()
447 				((adjusted_mode->crtc_htotal - 1) << 16), i);  in oaktrail_crtc_mode_set()
448 			REG_WRITE_WITH_AUX(map->vtotal, (mode->crtc_vdisplay - 1) |  in oaktrail_crtc_mode_set()
449 				((adjusted_mode->crtc_vtotal - 1) << 16), i);  in oaktrail_crtc_mode_set()
451 				(adjusted_mode->crtc_hblank_start - offsetX - 1) |  in oaktrail_crtc_mode_set()
452 				((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16), i);  in oaktrail_crtc_mode_set()
454 				(adjusted_mode->crtc_hsync_start - offsetX - 1) |  in oaktrail_crtc_mode_set()
455 				((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16), i);  in oaktrail_crtc_mode_set()
457 				(adjusted_mode->crtc_vblank_start - offsetY - 1) |  in oaktrail_crtc_mode_set()
458 				((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16), i);  in oaktrail_crtc_mode_set()
460 				(adjusted_mode->crtc_vsync_start - offsetY - 1) |  in oaktrail_crtc_mode_set()
461 				((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16), i);  in oaktrail_crtc_mode_set()
465 			REG_WRITE_WITH_AUX(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |  in oaktrail_crtc_mode_set()
466 				((adjusted_mode->crtc_htotal - 1) << 16), i);  in oaktrail_crtc_mode_set()
467 			REG_WRITE_WITH_AUX(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |  in oaktrail_crtc_mode_set()
468 				((adjusted_mode->crtc_vtotal - 1) << 16), i);  in oaktrail_crtc_mode_set()
469 			REG_WRITE_WITH_AUX(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |  in oaktrail_crtc_mode_set()
470 				((adjusted_mode->crtc_hblank_end - 1) << 16), i);  in oaktrail_crtc_mode_set()
471 			REG_WRITE_WITH_AUX(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |  in oaktrail_crtc_mode_set()
472 				((adjusted_mode->crtc_hsync_end - 1) << 16), i);  in oaktrail_crtc_mode_set()
473 			REG_WRITE_WITH_AUX(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |  in oaktrail_crtc_mode_set()
474 				((adjusted_mode->crtc_vblank_end - 1) << 16), i);  in oaktrail_crtc_mode_set()
475 			REG_WRITE_WITH_AUX(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |  in oaktrail_crtc_mode_set()
476 				((adjusted_mode->crtc_vsync_end - 1) << 16), i);  in oaktrail_crtc_mode_set()
512 		clock.p1 = (1L << (clock.p1 - 1));  in oaktrail_crtc_mode_set()
514 		clock.n = (1L << (clock.n - 1));  in oaktrail_crtc_mode_set()
544 		     1) << SDVO_MULTIPLIER_SHIFT_HIRES;  in oaktrail_crtc_mode_set()
548 	/* compute bitmask from p1 value */  in oaktrail_crtc_mode_set()
550 		dpll |= clock.p1 << 16; // dpll |= (1 << (clock.p1 - 1)) << 16;  in oaktrail_crtc_mode_set()
552 		dpll |= (1 << (clock.p1 - 2)) << 17;  in oaktrail_crtc_mode_set()