Lines Matching +full:single +full:- +full:lane
45 * struct i2c_algo_dp_aux_data - driver interface structure for i2c over dp
50 * @aux_ch: driver callback to transfer a single byte of the i2c payload
60 /* Run a single AUX_CH I2C transaction, writing/reading data as necessary */
65 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
68 ret = (*algo_data->aux_ch)(adapter, mode,
85 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
92 algo_data->address = address;
93 algo_data->running = true;
104 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
111 if (algo_data->running) {
113 algo_data->running = false;
118 * Write a single byte to the current I2C address, the
119 * I2C link must be running or this returns -EIO
124 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
126 if (!algo_data->running)
127 return -EIO;
133 * Read a single byte from the current I2C address, the
134 * I2C link must be running or this returns -EIO
139 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
141 if (!algo_data->running)
142 return -EIO;
211 adapter->algo = &i2c_dp_aux_algo;
212 adapter->retries = 3;
238 ret__ = -ETIMEDOUT; \
304 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
312 return encoder->type == INTEL_OUTPUT_EDP;
323 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
326 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
327 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
341 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
342 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
378 struct drm_device *dev = intel_encoder->base.dev;
379 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
382 if (intel_dp->panel_on) {
393 msleep(intel_dp->panel_power_up_delay);
398 struct drm_device *dev = intel_encoder->base.dev;
413 struct drm_device *dev = intel_encoder->base.dev;
414 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
417 if (intel_dp->panel_on)
430 intel_dp->panel_on = false;
432 intel_dp->panel_on = true;
433 msleep(intel_dp->panel_power_up_delay);
440 struct drm_device *dev = intel_encoder->base.dev;
442 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
451 intel_dp->panel_on = false;
466 msleep(intel_dp->panel_power_cycle_delay);
472 struct drm_device *dev = intel_encoder->base.dev;
492 struct drm_device *dev = intel_encoder->base.dev;
493 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
503 msleep(intel_dp->backlight_off_delay);
511 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
514 struct drm_psb_private *dev_priv = to_drm_psb_private(connector->dev);
516 if (is_edp(encoder) && intel_dp->panel_fixed_mode) {
517 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
519 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
526 (cdv_intel_dp_link_required(mode->clock, dev_priv->edp.bpp)
531 if (cdv_intel_dp_link_required(mode->clock, 24)
536 if (mode->clock < 10000)
551 v |= ((uint32_t) src[i]) << ((3-i) * 8);
562 dst[i] = src >> ((3-i) * 8);
570 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
571 uint32_t output_reg = intel_dp->output_reg;
572 struct drm_device *dev = encoder->base.dev;
596 return -EBUSY;
604 pack_aux(send + i, send_bytes - i));
635 return -EBUSY;
643 return -EIO;
647 * "normal" -- don't fill the kernel log with these */
650 return -ETIMEDOUT;
661 recv + i, recv_bytes - i);
677 return -1;
681 msg[3] = send_bytes - 1;
694 return -EIO;
699 /* Write a single byte to the aux channel in native mode */
722 msg[3] = recv_bytes - 1;
731 return -EPROTO;
736 memcpy(recv, reply + 1, ret - 1);
737 return ret - 1;
742 return -EIO;
750 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
754 struct gma_encoder *encoder = intel_dp->encoder;
755 uint16_t address = algo_data->address;
804 /* I2C-over-AUX Reply field is only valid
810 return -EREMOTEIO;
817 return -EREMOTEIO;
825 return reply_bytes - 1;
828 return -EREMOTEIO;
835 return -EREMOTEIO;
840 return -EREMOTEIO;
847 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
852 intel_dp->algo.running = false;
853 intel_dp->algo.address = 0;
854 intel_dp->algo.aux_ch = cdv_intel_dp_i2c_aux_ch;
856 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
857 intel_dp->adapter.owner = THIS_MODULE;
858 strscpy(intel_dp->adapter.name, name);
859 intel_dp->adapter.algo_data = &intel_dp->algo;
860 intel_dp->adapter.dev.parent = connector->base.kdev;
864 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
874 adjusted_mode->hdisplay = fixed_mode->hdisplay;
875 adjusted_mode->hsync_start = fixed_mode->hsync_start;
876 adjusted_mode->hsync_end = fixed_mode->hsync_end;
877 adjusted_mode->htotal = fixed_mode->htotal;
879 adjusted_mode->vdisplay = fixed_mode->vdisplay;
880 adjusted_mode->vsync_start = fixed_mode->vsync_start;
881 adjusted_mode->vsync_end = fixed_mode->vsync_end;
882 adjusted_mode->vtotal = fixed_mode->vtotal;
884 adjusted_mode->clock = fixed_mode->clock;
893 struct drm_psb_private *dev_priv = to_drm_psb_private(encoder->dev);
895 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
900 int refclock = mode->clock;
903 if (is_edp(intel_encoder) && intel_dp->panel_fixed_mode) {
904 cdv_intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
905 refclock = intel_dp->panel_fixed_mode->clock;
906 bpp = dev_priv->edp.bpp;
910 for (clock = max_clock; clock >= 0; clock--) {
914 intel_dp->link_bw = bws[clock];
915 intel_dp->lane_count = lane_count;
916 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw);
917 DRM_DEBUG_KMS("Display port link bw %02x lane "
919 intel_dp->link_bw, intel_dp->lane_count,
920 adjusted_mode->clock);
927 intel_dp->lane_count = max_lane_count;
928 intel_dp->link_bw = bws[max_clock];
929 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw);
930 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
932 intel_dp->link_bw, intel_dp->lane_count,
933 adjusted_mode->clock);
971 m_n->tu = 64;
972 m_n->gmch_m = (pixel_clock * bpp + 7) >> 3;
973 m_n->gmch_n = link_clock * nlanes;
974 cdv_intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
975 m_n->link_m = pixel_clock;
976 m_n->link_n = link_clock;
977 cdv_intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
984 struct drm_device *dev = crtc->dev;
986 struct drm_mode_config *mode_config = &dev->mode_config;
991 int pipe = gma_crtc->pipe;
994 * Find the lane count in the intel_encoder private
996 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1000 if (encoder->crtc != crtc)
1004 intel_dp = intel_encoder->dev_priv;
1005 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1006 lane_count = intel_dp->lane_count;
1009 lane_count = intel_dp->lane_count;
1010 bpp = dev_priv->edp.bpp;
1017 * the number of bytes_per_pixel post-LUT, which we always
1018 * set up for 8-bits of R/G/B, or 3 bytes total.
1021 mode->clock, adjusted_mode->clock, &m_n);
1025 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
1038 struct drm_crtc *crtc = encoder->crtc;
1040 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
1041 struct drm_device *dev = encoder->dev;
1043 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1044 intel_dp->DP |= intel_dp->color_range;
1046 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1047 intel_dp->DP |= DP_SYNC_HS_HIGH;
1048 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1049 intel_dp->DP |= DP_SYNC_VS_HIGH;
1051 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1053 switch (intel_dp->lane_count) {
1055 intel_dp->DP |= DP_PORT_WIDTH_1;
1058 intel_dp->DP |= DP_PORT_WIDTH_2;
1061 intel_dp->DP |= DP_PORT_WIDTH_4;
1064 if (intel_dp->has_audio)
1065 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1067 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
1068 intel_dp->link_configuration[0] = intel_dp->link_bw;
1069 intel_dp->link_configuration[1] = intel_dp->lane_count;
1074 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
1075 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
1076 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
1077 intel_dp->DP |= DP_ENHANCED_FRAMING;
1081 if (gma_crtc->pipe == 1)
1082 intel_dp->DP |= DP_PIPEB_SELECT;
1084 REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN));
1085 DRM_DEBUG_KMS("DP expected reg is %x\n", intel_dp->DP);
1090 if (mode->hdisplay != adjusted_mode->hdisplay ||
1091 mode->vdisplay != adjusted_mode->vdisplay)
1096 pfit_control |= gma_crtc->pipe << PFIT_PIPE_SHIFT;
1106 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1110 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1168 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
1169 struct drm_device *dev = encoder->dev;
1170 uint32_t dp_reg = REG_READ(intel_dp->output_reg);
1223 * Fetch AUX CH registers 0x202 - 0x207 which contain
1229 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1232 intel_dp->link_status,
1240 return link_status[r - DP_LANE0_1_STATUS];
1245 int lane)
1247 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1248 int s = ((lane & 1) ?
1258 int lane)
1260 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1261 int s = ((lane & 1) ?
1274 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1277 int lane;
1279 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1280 uint8_t this_v = cdv_intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1281 uint8_t this_p = cdv_intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1295 for (lane = 0; lane < 4; lane++)
1296 intel_dp->train_set[lane] = v | p;
1302 int lane)
1304 int i = DP_LANE0_1_STATUS + (lane >> 1);
1305 int s = (lane & 1) * 4;
1315 int lane;
1318 for (lane = 0; lane < lane_count; lane++) {
1319 lane_status = cdv_intel_get_lane_status(link_status, lane);
1333 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1336 int lane;
1338 lane_align = cdv_intel_dp_link_status(intel_dp->link_status,
1342 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1343 lane_status = cdv_intel_get_lane_status(intel_dp->link_status, lane);
1355 struct drm_device *dev = encoder->base.dev;
1357 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1359 REG_WRITE(intel_dp->output_reg, dp_reg_value);
1360 REG_READ(intel_dp->output_reg);
1381 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1385 intel_dp->train_set,
1386 intel_dp->lane_count);
1388 if (ret != intel_dp->lane_count) {
1390 intel_dp->train_set[0], intel_dp->lane_count);
1399 struct drm_device *dev = encoder->base.dev;
1400 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1404 if (intel_dp->output_reg == DP_B)
1423 cdv_sb_write(dev, ddi_reg->VSwing5, 0x0505313A);
1426 cdv_sb_write(dev, ddi_reg->VSwing1, 0x43406055);
1433 cdv_sb_write(dev, ddi_reg->VSwing2, 0x055738954);
1435 cdv_sb_write(dev, ddi_reg->VSwing2, dp_vswing_premph_table[index]);
1439 cdv_sb_write(dev, ddi_reg->VSwing3, 0x70802040);
1441 cdv_sb_write(dev, ddi_reg->VSwing3, 0x40802040);
1444 /* cdv_sb_write(dev, ddi_reg->VSwing4, 0x2b405555); */
1447 cdv_sb_write(dev, ddi_reg->VSwing1, 0xc3406055);
1452 cdv_sb_write(dev, ddi_reg->PreEmph1, 0x1f030040);
1456 cdv_sb_write(dev, ddi_reg->PreEmph2, dp_vswing_premph_table[index]);
1465 struct drm_device *dev = encoder->base.dev;
1466 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1472 uint32_t DP = intel_dp->DP;
1480 REG_WRITE(intel_dp->output_reg, reg);
1481 REG_READ(intel_dp->output_reg);
1487 intel_dp->link_configuration,
1490 memset(intel_dp->train_set, 0, 4);
1499 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1501 intel_dp->train_set[0],
1502 intel_dp->link_configuration[0],
1503 intel_dp->link_configuration[1]);
1506 DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 1\n");
1508 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]);
1518 intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2],
1519 intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]);
1521 if (cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1528 for (i = 0; i < intel_dp->lane_count; i++)
1529 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1531 if (i == intel_dp->lane_count)
1535 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1541 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1543 /* Compute new intel_dp->train_set as requested by target */
1549 DRM_DEBUG_KMS("failure in DP pattern 1 training, train set %x\n", intel_dp->train_set[0]);
1552 intel_dp->DP = DP;
1558 struct drm_device *dev = encoder->base.dev;
1559 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1562 uint32_t DP = intel_dp->DP;
1574 intel_dp->train_set[0],
1575 intel_dp->link_configuration[0],
1576 intel_dp->link_configuration[1]);
1581 DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 2\n");
1583 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1591 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]);
1600 intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2],
1601 intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]);
1604 if (!cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1624 /* Compute new intel_dp->train_set as requested by target */
1632 REG_WRITE(intel_dp->output_reg, reg);
1633 REG_READ(intel_dp->output_reg);
1641 struct drm_device *dev = encoder->base.dev;
1642 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1643 uint32_t DP = intel_dp->DP;
1645 if ((REG_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1653 REG_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1655 REG_READ(intel_dp->output_reg);
1659 REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1660 REG_READ(intel_dp->output_reg);
1665 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1669 if (cdv_intel_dp_aux_native_read(encoder, 0x000, intel_dp->dpcd,
1670 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1672 if (intel_dp->dpcd[DP_DPCD_REV] != 0)
1677 intel_dp->dpcd[0], intel_dp->dpcd[1],
1678 intel_dp->dpcd[2], intel_dp->dpcd[3]);
1692 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1697 intel_dp->has_audio = false;
1708 if (intel_dp->force_audio) {
1709 intel_dp->has_audio = intel_dp->force_audio > 0;
1711 edid = drm_get_edid(connector, &intel_dp->adapter);
1713 intel_dp->has_audio = drm_detect_monitor_audio(edid);
1726 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
1732 edid = drm_get_edid(connector, &intel_dp->adapter);
1740 struct drm_device *dev = connector->dev;
1745 if (edp && !intel_dp->panel_fixed_mode) {
1747 list_for_each_entry(newmode, &connector->probed_modes,
1749 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1750 intel_dp->panel_fixed_mode =
1759 if (!intel_dp->panel_fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
1760 intel_dp->panel_fixed_mode =
1761 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1762 if (intel_dp->panel_fixed_mode) {
1763 intel_dp->panel_fixed_mode->type |=
1767 if (intel_dp->panel_fixed_mode != NULL) {
1769 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
1782 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1790 edid = drm_get_edid(connector, &intel_dp->adapter);
1806 struct drm_psb_private *dev_priv = to_drm_psb_private(connector->dev);
1808 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1811 ret = drm_object_property_set_value(&connector->base, property, val);
1815 if (property == dev_priv->force_audio_property) {
1819 if (i == intel_dp->force_audio)
1822 intel_dp->force_audio = i;
1829 if (has_audio == intel_dp->has_audio)
1832 intel_dp->has_audio = has_audio;
1836 if (property == dev_priv->broadcast_rgb_property) {
1837 if (val == !!intel_dp->color_range)
1840 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
1844 return -EINVAL;
1847 if (encoder->base.crtc) {
1848 struct drm_crtc *crtc = encoder->base.crtc;
1849 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1850 crtc->x, crtc->y,
1851 crtc->primary->fb);
1862 struct cdv_intel_dp *intel_dp = gma_encoder->dev_priv;
1865 /* cdv_intel_panel_destroy_backlight(connector->dev); */
1866 kfree(intel_dp->panel_fixed_mode);
1867 intel_dp->panel_fixed_mode = NULL;
1869 i2c_del_adapter(&intel_dp->adapter);
1902 /* check the VBT to see whether the eDP is on DP-D port */
1909 if (!dev_priv->child_dev_num)
1912 for (i = 0; i < dev_priv->child_dev_num; i++) {
1913 p_child = dev_priv->child_dev + i;
1915 if (p_child->dvo_port == PORT_IDPC &&
1916 p_child->device_type == DEVICE_TYPE_eDP)
1925 DP/eDP. TODO - investigate if we can turn it back to normality
1968 connector = &gma_connector->base;
1969 encoder = &gma_encoder->base;
1977 gma_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1979 gma_encoder->type = INTEL_OUTPUT_EDP;
1982 gma_encoder->dev_priv=intel_dp;
1983 intel_dp->encoder = gma_encoder;
1984 intel_dp->output_reg = output_reg;
1989 connector->polled = DRM_CONNECTOR_POLL_HPD;
1990 connector->interlace_allowed = false;
1991 connector->doublescan_allowed = false;
1996 name = "DPDDC-B";
1997 gma_encoder->ddi_select = (DP_MASK | DDI0_SELECT);
2000 name = "DPDDC-C";
2001 gma_encoder->ddi_select = (DP_MASK | DDI1_SELECT);
2051 intel_dp->panel_power_up_delay = cur.t1_t3 / 10;
2052 intel_dp->backlight_on_delay = cur.t8 / 10;
2053 intel_dp->backlight_off_delay = cur.t9 / 10;
2054 intel_dp->panel_power_down_delay = cur.t10 / 10;
2055 intel_dp->panel_power_cycle_delay = (cur.t11_t12 - 1) * 100;
2058 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2059 intel_dp->panel_power_cycle_delay);
2062 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2067 intel_dp->dpcd,
2068 sizeof(intel_dp->dpcd));
2078 intel_dp->dpcd[0], intel_dp->dpcd[1],
2079 intel_dp->dpcd[2], intel_dp->dpcd[3]);