Lines Matching defs:DP
256 uint32_t DP;
307 * If a CPU or PCH DP output is attached to an eDP panel, this function
599 /* Must try at least 3 times according to DP spec */
1043 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1044 intel_dp->DP |= intel_dp->color_range;
1047 intel_dp->DP |= DP_SYNC_HS_HIGH;
1049 intel_dp->DP |= DP_SYNC_VS_HIGH;
1051 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1055 intel_dp->DP |= DP_PORT_WIDTH_1;
1058 intel_dp->DP |= DP_PORT_WIDTH_2;
1061 intel_dp->DP |= DP_PORT_WIDTH_4;
1065 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1077 intel_dp->DP |= DP_ENHANCED_FRAMING;
1080 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
1082 intel_dp->DP |= DP_PIPEB_SELECT;
1084 REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN));
1085 DRM_DEBUG_KMS("DP expected reg is %x\n", intel_dp->DP);
1472 uint32_t DP = intel_dp->DP;
1474 DP |= DP_PORT_EN;
1475 DP &= ~DP_LINK_TRAIN_MASK;
1477 reg = DP;
1496 reg = DP | DP_LINK_TRAIN_PAT_1;
1500 DRM_DEBUG_KMS("DP Link Train Set %x, Link_config %x, %x\n",
1517 DRM_DEBUG_KMS("DP Link status %x, %x, %x, %x, %x, %x\n",
1549 DRM_DEBUG_KMS("failure in DP pattern 1 training, train set %x\n", intel_dp->train_set[0]);
1552 intel_dp->DP = DP;
1562 uint32_t DP = intel_dp->DP;
1569 reg = DP | DP_LINK_TRAIN_PAT_2;
1573 DRM_DEBUG_KMS("DP Link Train Set %x, Link_config %x, %x\n",
1586 DRM_ERROR("failed to train DP, aborting\n");
1599 DRM_DEBUG_KMS("DP Link status %x, %x, %x, %x, %x, %x\n",
1630 reg = DP | DP_LINK_TRAIN_OFF;
1643 uint32_t DP = intel_dp->DP;
1652 DP &= ~DP_LINK_TRAIN_MASK;
1653 REG_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1659 REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1683 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1685 * \return true if DP port is connected.
1686 * \return false if DP port is disconnected.
1902 /* check the VBT to see whether the eDP is on DP-D port */
1925 DP/eDP. TODO - investigate if we can turn it back to normality