Lines Matching defs:mic
109 static void mic_set_path(struct exynos_mic *mic, bool enable)
114 ret = regmap_read(mic->sysreg, DSD_CFG_MUX, &val);
116 DRM_DEV_ERROR(mic->dev,
117 "mic: Failed to read system register\n");
122 if (mic->i80_mode)
131 ret = regmap_write(mic->sysreg, DSD_CFG_MUX, val);
133 DRM_DEV_ERROR(mic->dev,
134 "mic: Failed to read system register\n");
137 static int mic_sw_reset(struct exynos_mic *mic)
142 writel(MIC_SW_RST, mic->reg + MIC_OP);
145 ret = readl(mic->reg + MIC_OP);
155 static void mic_set_porch_timing(struct exynos_mic *mic)
157 struct videomode vm = mic->vm;
163 writel(reg, mic->reg + MIC_V_TIMING_0);
167 writel(reg, mic->reg + MIC_V_TIMING_1);
172 writel(reg, mic->reg + MIC_INPUT_TIMING_0);
176 writel(reg, mic->reg + MIC_INPUT_TIMING_1);
179 static void mic_set_img_size(struct exynos_mic *mic)
181 struct videomode *vm = &mic->vm;
187 writel(reg, mic->reg + MIC_IMG_SIZE);
190 static void mic_set_output_timing(struct exynos_mic *mic)
192 struct videomode vm = mic->vm;
195 DRM_DEV_DEBUG(mic->dev, "w: %u, h: %u\n", vm.hactive, vm.vactive);
198 writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_2);
200 if (!mic->i80_mode) {
204 writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_0);
208 writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_1);
212 static void mic_set_reg_on(struct exynos_mic *mic, bool enable)
214 u32 reg = readl(mic->reg + MIC_OP);
221 if (mic->i80_mode)
228 writel(reg, mic->reg + MIC_OP);
233 struct exynos_mic *mic = bridge->driver_private;
236 if (!mic->enabled)
239 mic_set_path(mic, 0);
241 pm_runtime_put(mic->dev);
242 mic->enabled = 0;
252 struct exynos_mic *mic = bridge->driver_private;
255 drm_display_mode_to_videomode(mode, &mic->vm);
256 mic->i80_mode = to_exynos_crtc(bridge->encoder->crtc)->i80_mode;
262 struct exynos_mic *mic = bridge->driver_private;
266 if (mic->enabled)
269 ret = pm_runtime_resume_and_get(mic->dev);
273 mic_set_path(mic, 1);
275 ret = mic_sw_reset(mic);
277 DRM_DEV_ERROR(mic->dev, "Failed to reset\n");
281 if (!mic->i80_mode)
282 mic_set_porch_timing(mic);
283 mic_set_img_size(mic);
284 mic_set_output_timing(mic);
285 mic_set_reg_on(mic, 1);
286 mic->enabled = 1;
292 pm_runtime_put(mic->dev);
306 struct exynos_mic *mic = dev_get_drvdata(dev);
318 mic->bridge.driver_private = mic;
320 return drm_bridge_attach(encoder, &mic->bridge, NULL, 0);
326 struct exynos_mic *mic = dev_get_drvdata(dev);
329 if (!mic->enabled)
332 pm_runtime_put(mic->dev);
345 struct exynos_mic *mic = dev_get_drvdata(dev);
349 clk_disable_unprepare(mic->clks[i]);
356 struct exynos_mic *mic = dev_get_drvdata(dev);
360 ret = clk_prepare_enable(mic->clks[i]);
365 clk_disable_unprepare(mic->clks[i]);
378 struct exynos_mic *mic;
382 mic = devm_drm_bridge_alloc(dev, struct exynos_mic, bridge, &mic_bridge_funcs);
383 if (IS_ERR(mic)) {
385 "mic: Failed to allocate memory for MIC object\n");
386 ret = PTR_ERR(mic);
390 mic->dev = dev;
394 DRM_DEV_ERROR(dev, "mic: Failed to get mem region for MIC\n");
397 mic->reg = devm_ioremap(dev, res.start, resource_size(&res));
398 if (!mic->reg) {
399 DRM_DEV_ERROR(dev, "mic: Failed to remap for MIC\n");
404 mic->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
406 if (IS_ERR(mic->sysreg)) {
407 DRM_DEV_ERROR(dev, "mic: Failed to get system register.\n");
408 ret = PTR_ERR(mic->sysreg);
413 mic->clks[i] = devm_clk_get(dev, clk_names[i]);
414 if (IS_ERR(mic->clks[i])) {
415 DRM_DEV_ERROR(dev, "mic: Failed to get clock (%s)\n",
417 ret = PTR_ERR(mic->clks[i]);
422 platform_set_drvdata(pdev, mic);
424 mic->bridge.of_node = dev->of_node;
426 drm_bridge_add(&mic->bridge);
446 struct exynos_mic *mic = platform_get_drvdata(pdev);
451 drm_bridge_remove(&mic->bridge);
455 { .compatible = "samsung,exynos5433-mic" },
464 .name = "exynos-mic",