Lines Matching +full:invert +full:- +full:vden
1 // SPDX-License-Identifier: GPL-2.0-or-later
63 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
65 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
202 { .compatible = "samsung,s3c6400-fimd",
204 { .compatible = "samsung,s5pv210-fimd",
206 { .compatible = "samsung,exynos3250-fimd",
208 { .compatible = "samsung,exynos4210-fimd",
210 { .compatible = "samsung,exynos5250-fimd",
212 { .compatible = "samsung,exynos5420-fimd",
257 val = (val & mask) | (readl(ctx->regs + reg) & ~mask); in fimd_set_bits()
258 writel(val, ctx->regs + reg); in fimd_set_bits()
263 struct fimd_context *ctx = crtc->ctx; in fimd_enable_vblank()
266 if (ctx->suspended) in fimd_enable_vblank()
267 return -EPERM; in fimd_enable_vblank()
269 if (!test_and_set_bit(0, &ctx->irq_flags)) { in fimd_enable_vblank()
270 val = readl(ctx->regs + VIDINTCON0); in fimd_enable_vblank()
274 if (ctx->i80_if) { in fimd_enable_vblank()
287 writel(val, ctx->regs + VIDINTCON0); in fimd_enable_vblank()
295 struct fimd_context *ctx = crtc->ctx; in fimd_disable_vblank()
298 if (ctx->suspended) in fimd_disable_vblank()
301 if (test_and_clear_bit(0, &ctx->irq_flags)) { in fimd_disable_vblank()
302 val = readl(ctx->regs + VIDINTCON0); in fimd_disable_vblank()
306 if (ctx->i80_if) { in fimd_disable_vblank()
313 writel(val, ctx->regs + VIDINTCON0); in fimd_disable_vblank()
319 struct fimd_context *ctx = crtc->ctx; in fimd_wait_for_vblank()
321 if (ctx->suspended) in fimd_wait_for_vblank()
324 atomic_set(&ctx->wait_vsync_event, 1); in fimd_wait_for_vblank()
330 if (!wait_event_timeout(ctx->wait_vsync_queue, in fimd_wait_for_vblank()
331 !atomic_read(&ctx->wait_vsync_event), in fimd_wait_for_vblank()
333 DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n"); in fimd_wait_for_vblank()
339 u32 val = readl(ctx->regs + WINCON(win)); in fimd_enable_video_output()
346 writel(val, ctx->regs + WINCON(win)); in fimd_enable_video_output()
353 u32 val = readl(ctx->regs + SHADOWCON); in fimd_enable_shadow_channel_path()
360 writel(val, ctx->regs + SHADOWCON); in fimd_enable_shadow_channel_path()
365 struct fimd_context *ctx = crtc->ctx; in fimd_clear_channels()
370 ret = pm_runtime_resume_and_get(ctx->dev); in fimd_clear_channels()
372 dev_err(ctx->dev, "failed to enable FIMD device.\n"); in fimd_clear_channels()
376 clk_prepare_enable(ctx->bus_clk); in fimd_clear_channels()
377 clk_prepare_enable(ctx->lcd_clk); in fimd_clear_channels()
381 u32 val = readl(ctx->regs + WINCON(win)); in fimd_clear_channels()
386 if (ctx->driver_data->has_shadowcon) in fimd_clear_channels()
396 ctx->suspended = false; in fimd_clear_channels()
398 fimd_enable_vblank(ctx->crtc); in fimd_clear_channels()
399 fimd_wait_for_vblank(ctx->crtc); in fimd_clear_channels()
400 fimd_disable_vblank(ctx->crtc); in fimd_clear_channels()
402 ctx->suspended = true; in fimd_clear_channels()
405 clk_disable_unprepare(ctx->lcd_clk); in fimd_clear_channels()
406 clk_disable_unprepare(ctx->bus_clk); in fimd_clear_channels()
408 pm_runtime_put(ctx->dev); in fimd_clear_channels()
417 struct drm_display_mode *mode = &state->adjusted_mode; in fimd_atomic_check()
418 struct fimd_context *ctx = crtc->ctx; in fimd_atomic_check()
422 if (mode->clock == 0) { in fimd_atomic_check()
423 DRM_DEV_ERROR(ctx->dev, "Mode has zero clock value.\n"); in fimd_atomic_check()
424 return -EINVAL; in fimd_atomic_check()
427 ideal_clk = mode->clock * 1000; in fimd_atomic_check()
429 if (ctx->i80_if) { in fimd_atomic_check()
437 lcd_rate = clk_get_rate(ctx->lcd_clk); in fimd_atomic_check()
439 DRM_DEV_ERROR(ctx->dev, in fimd_atomic_check()
442 return -EINVAL; in fimd_atomic_check()
448 DRM_DEV_ERROR(ctx->dev, "requested pixel clock(%lu) too low\n", in fimd_atomic_check()
450 return -EINVAL; in fimd_atomic_check()
453 ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff; in fimd_atomic_check()
460 void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base; in fimd_setup_trigger()
461 u32 trg_type = ctx->driver_data->trg_type; in fimd_setup_trigger()
467 if (ctx->driver_data->has_hw_trigger) in fimd_setup_trigger()
469 if (ctx->driver_data->has_trigger_per_te) in fimd_setup_trigger()
480 struct fimd_context *ctx = crtc->ctx; in fimd_commit()
481 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; in fimd_commit()
482 const struct fimd_driver_data *driver_data = ctx->driver_data; in fimd_commit()
483 void __iomem *timing_base = ctx->regs + driver_data->timing_base; in fimd_commit()
486 if (ctx->suspended) in fimd_commit()
490 if (mode->htotal == 0 || mode->vtotal == 0) in fimd_commit()
493 if (ctx->i80_if) { in fimd_commit()
494 val = ctx->i80ifcon | I80IFEN_ENABLE; in fimd_commit()
501 if (driver_data->has_vtsel && ctx->sysreg && in fimd_commit()
502 regmap_update_bits(ctx->sysreg, in fimd_commit()
503 driver_data->lcdblk_offset, in fimd_commit()
504 0x3 << driver_data->lcdblk_vt_shift, in fimd_commit()
505 0x1 << driver_data->lcdblk_vt_shift)) { in fimd_commit()
506 DRM_DEV_ERROR(ctx->dev, in fimd_commit()
515 vidcon1 = ctx->vidcon1; in fimd_commit()
516 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in fimd_commit()
518 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in fimd_commit()
520 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); in fimd_commit()
523 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; in fimd_commit()
524 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; in fimd_commit()
525 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; in fimd_commit()
527 val = VIDTCON0_VBPD(vbpd - 1) | in fimd_commit()
528 VIDTCON0_VFPD(vfpd - 1) | in fimd_commit()
529 VIDTCON0_VSPW(vsync_len - 1); in fimd_commit()
530 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); in fimd_commit()
533 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; in fimd_commit()
534 hbpd = mode->crtc_htotal - mode->crtc_hsync_end; in fimd_commit()
535 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; in fimd_commit()
537 val = VIDTCON1_HBPD(hbpd - 1) | in fimd_commit()
538 VIDTCON1_HFPD(hfpd - 1) | in fimd_commit()
539 VIDTCON1_HSPW(hsync_len - 1); in fimd_commit()
540 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); in fimd_commit()
543 if (driver_data->has_vidoutcon) in fimd_commit()
544 writel(ctx->vidout_con, timing_base + VIDOUT_CON); in fimd_commit()
547 if (ctx->sysreg && regmap_update_bits(ctx->sysreg, in fimd_commit()
548 driver_data->lcdblk_offset, in fimd_commit()
549 0x1 << driver_data->lcdblk_bypass_shift, in fimd_commit()
550 0x1 << driver_data->lcdblk_bypass_shift)) { in fimd_commit()
551 DRM_DEV_ERROR(ctx->dev, in fimd_commit()
559 if (driver_data->has_mic_bypass && ctx->sysreg && in fimd_commit()
560 regmap_update_bits(ctx->sysreg, in fimd_commit()
561 driver_data->lcdblk_offset, in fimd_commit()
562 0x1 << driver_data->lcdblk_mic_bypass_shift, in fimd_commit()
563 0x1 << driver_data->lcdblk_mic_bypass_shift)) { in fimd_commit()
564 DRM_DEV_ERROR(ctx->dev, in fimd_commit()
570 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | in fimd_commit()
571 VIDTCON2_HOZVAL(mode->hdisplay - 1) | in fimd_commit()
572 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) | in fimd_commit()
573 VIDTCON2_HOZVAL_E(mode->hdisplay - 1); in fimd_commit()
574 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); in fimd_commit()
582 val = ctx->vidcon0; in fimd_commit()
585 if (ctx->driver_data->has_clksel) in fimd_commit()
588 if (ctx->clkdiv > 1) in fimd_commit()
589 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR; in fimd_commit()
591 writel(val, ctx->regs + VIDCON0); in fimd_commit()
647 writel(val, ctx->regs + VIDOSD_C(win)); in fimd_win_set_bldmod()
651 writel(val, ctx->regs + VIDWnALPHA0(win)); in fimd_win_set_bldmod()
655 writel(val, ctx->regs + VIDWnALPHA1(win)); in fimd_win_set_bldmod()
664 struct exynos_drm_plane *plane = &ctx->planes[win]; in fimd_win_set_pixfmt()
666 to_exynos_plane_state(plane->base.state); in fimd_win_set_pixfmt()
667 uint32_t pixel_format = fb->format->format; in fimd_win_set_pixfmt()
668 unsigned int alpha = state->base.alpha; in fimd_win_set_pixfmt()
672 if (fb->format->has_alpha) in fimd_win_set_pixfmt()
673 pixel_alpha = state->base.pixel_blend_mode; in fimd_win_set_pixfmt()
681 if (ctx->driver_data->has_limited_fmt && !win) { in fimd_win_set_pixfmt()
724 writel(WIN_RGB_ORDER_REVERSE, ctx->regs + WIN_RGB_ORDER(win)); in fimd_win_set_pixfmt()
727 writel(WIN_RGB_ORDER_FORWARD, ctx->regs + WIN_RGB_ORDER(win)); in fimd_win_set_pixfmt()
732 * Setting dma-burst to 16Word causes permanent tearing for very small in fimd_win_set_pixfmt()
736 * still better to change dma-burst than displaying garbage. in fimd_win_set_pixfmt()
761 writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); in fimd_win_set_colkey()
762 writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); in fimd_win_set_colkey()
766 * fimd_shadow_protect_win() - disable updating values from shadow registers at vsync
787 if (ctx->driver_data->has_shadowcon) { in fimd_shadow_protect_win()
795 val = readl(ctx->regs + reg); in fimd_shadow_protect_win()
800 writel(val, ctx->regs + reg); in fimd_shadow_protect_win()
805 struct fimd_context *ctx = crtc->ctx; in fimd_atomic_begin()
808 if (ctx->suspended) in fimd_atomic_begin()
817 struct fimd_context *ctx = crtc->ctx; in fimd_atomic_flush()
820 if (ctx->suspended) in fimd_atomic_flush()
833 to_exynos_plane_state(plane->base.state); in fimd_update_plane()
834 struct fimd_context *ctx = crtc->ctx; in fimd_update_plane()
835 struct drm_framebuffer *fb = state->base.fb; in fimd_update_plane()
839 unsigned int win = plane->index; in fimd_update_plane()
840 unsigned int cpp = fb->format->cpp[0]; in fimd_update_plane()
841 unsigned int pitch = fb->pitches[0]; in fimd_update_plane()
843 if (ctx->suspended) in fimd_update_plane()
846 offset = state->src.x * cpp; in fimd_update_plane()
847 offset += state->src.y * pitch; in fimd_update_plane()
852 writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); in fimd_update_plane()
855 size = pitch * state->crtc.h; in fimd_update_plane()
857 writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); in fimd_update_plane()
859 DRM_DEV_DEBUG_KMS(ctx->dev, in fimd_update_plane()
862 DRM_DEV_DEBUG_KMS(ctx->dev, "ovl_width = %d, ovl_height = %d\n", in fimd_update_plane()
863 state->crtc.w, state->crtc.h); in fimd_update_plane()
866 buf_offsize = pitch - (state->crtc.w * cpp); in fimd_update_plane()
867 line_size = state->crtc.w * cpp; in fimd_update_plane()
872 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); in fimd_update_plane()
875 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) | in fimd_update_plane()
876 VIDOSDxA_TOPLEFT_Y(state->crtc.y) | in fimd_update_plane()
877 VIDOSDxA_TOPLEFT_X_E(state->crtc.x) | in fimd_update_plane()
878 VIDOSDxA_TOPLEFT_Y_E(state->crtc.y); in fimd_update_plane()
879 writel(val, ctx->regs + VIDOSD_A(win)); in fimd_update_plane()
881 last_x = state->crtc.x + state->crtc.w; in fimd_update_plane()
883 last_x--; in fimd_update_plane()
884 last_y = state->crtc.y + state->crtc.h; in fimd_update_plane()
886 last_y--; in fimd_update_plane()
891 writel(val, ctx->regs + VIDOSD_B(win)); in fimd_update_plane()
893 DRM_DEV_DEBUG_KMS(ctx->dev, in fimd_update_plane()
895 state->crtc.x, state->crtc.y, last_x, last_y); in fimd_update_plane()
902 val = state->crtc.w * state->crtc.h; in fimd_update_plane()
903 writel(val, ctx->regs + offset); in fimd_update_plane()
905 DRM_DEV_DEBUG_KMS(ctx->dev, "osd size = 0x%x\n", in fimd_update_plane()
909 fimd_win_set_pixfmt(ctx, win, fb, state->src.w); in fimd_update_plane()
917 if (ctx->driver_data->has_shadowcon) in fimd_update_plane()
920 if (ctx->i80_if) in fimd_update_plane()
921 atomic_set(&ctx->win_updated, 1); in fimd_update_plane()
927 struct fimd_context *ctx = crtc->ctx; in fimd_disable_plane()
928 unsigned int win = plane->index; in fimd_disable_plane()
930 if (ctx->suspended) in fimd_disable_plane()
935 if (ctx->driver_data->has_shadowcon) in fimd_disable_plane()
941 struct fimd_context *ctx = crtc->ctx; in fimd_atomic_enable()
943 if (!ctx->suspended) in fimd_atomic_enable()
946 ctx->suspended = false; in fimd_atomic_enable()
948 if (pm_runtime_resume_and_get(ctx->dev) < 0) { in fimd_atomic_enable()
949 dev_warn(ctx->dev, "failed to enable FIMD device.\n"); in fimd_atomic_enable()
954 if (test_and_clear_bit(0, &ctx->irq_flags)) in fimd_atomic_enable()
955 fimd_enable_vblank(ctx->crtc); in fimd_atomic_enable()
957 fimd_commit(ctx->crtc); in fimd_atomic_enable()
962 struct fimd_context *ctx = crtc->ctx; in fimd_atomic_disable()
965 if (ctx->suspended) in fimd_atomic_disable()
974 fimd_disable_plane(crtc, &ctx->planes[i]); in fimd_atomic_disable()
980 writel(0, ctx->regs + VIDCON0); in fimd_atomic_disable()
982 pm_runtime_put_sync(ctx->dev); in fimd_atomic_disable()
983 ctx->suspended = true; in fimd_atomic_disable()
989 const struct fimd_driver_data *driver_data = ctx->driver_data; in fimd_trigger()
990 void *timing_base = ctx->regs + driver_data->timing_base; in fimd_trigger()
997 if (atomic_read(&ctx->triggering)) in fimd_trigger()
1001 atomic_set(&ctx->triggering, 1); in fimd_trigger()
1011 if (!test_bit(0, &ctx->irq_flags)) in fimd_trigger()
1012 atomic_set(&ctx->triggering, 0); in fimd_trigger()
1017 struct fimd_context *ctx = crtc->ctx; in fimd_te_handler()
1018 u32 trg_type = ctx->driver_data->trg_type; in fimd_te_handler()
1021 if (!ctx->drm_dev) in fimd_te_handler()
1031 if (atomic_add_unless(&ctx->win_updated, -1, 0)) in fimd_te_handler()
1032 fimd_trigger(ctx->dev); in fimd_te_handler()
1036 if (atomic_read(&ctx->wait_vsync_event)) { in fimd_te_handler()
1037 atomic_set(&ctx->wait_vsync_event, 0); in fimd_te_handler()
1038 wake_up(&ctx->wait_vsync_queue); in fimd_te_handler()
1041 if (test_bit(0, &ctx->irq_flags)) in fimd_te_handler()
1042 drm_crtc_handle_vblank(&ctx->crtc->base); in fimd_te_handler()
1050 writel(val, ctx->regs + DP_MIE_CLKCON); in fimd_dp_clock_enable()
1071 val = readl(ctx->regs + VIDINTCON1); in fimd_irq_handler()
1073 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; in fimd_irq_handler()
1075 writel(clear_bit, ctx->regs + VIDINTCON1); in fimd_irq_handler()
1078 if (!ctx->drm_dev) in fimd_irq_handler()
1081 if (!ctx->i80_if) in fimd_irq_handler()
1082 drm_crtc_handle_vblank(&ctx->crtc->base); in fimd_irq_handler()
1084 if (ctx->i80_if) { in fimd_irq_handler()
1086 atomic_set(&ctx->triggering, 0); in fimd_irq_handler()
1089 if (atomic_read(&ctx->wait_vsync_event)) { in fimd_irq_handler()
1090 atomic_set(&ctx->wait_vsync_event, 0); in fimd_irq_handler()
1091 wake_up(&ctx->wait_vsync_queue); in fimd_irq_handler()
1107 ctx->drm_dev = drm_dev; in fimd_bind()
1110 if (ctx->driver_data->has_bgr_support) { in fimd_bind()
1111 ctx->configs[i].pixel_formats = fimd_extended_formats; in fimd_bind()
1112 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_extended_formats); in fimd_bind()
1114 ctx->configs[i].pixel_formats = fimd_formats; in fimd_bind()
1115 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats); in fimd_bind()
1118 ctx->configs[i].zpos = i; in fimd_bind()
1119 ctx->configs[i].type = fimd_win_types[i]; in fimd_bind()
1120 ctx->configs[i].capabilities = capabilities[i]; in fimd_bind()
1121 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, in fimd_bind()
1122 &ctx->configs[i]); in fimd_bind()
1127 exynos_plane = &ctx->planes[DEFAULT_WIN]; in fimd_bind()
1128 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, in fimd_bind()
1130 if (IS_ERR(ctx->crtc)) in fimd_bind()
1131 return PTR_ERR(ctx->crtc); in fimd_bind()
1133 if (ctx->driver_data->has_dp_clk) { in fimd_bind()
1134 ctx->dp_clk.enable = fimd_dp_clock_enable; in fimd_bind()
1135 ctx->crtc->pipe_clk = &ctx->dp_clk; in fimd_bind()
1138 if (ctx->encoder) in fimd_bind()
1139 exynos_dpi_bind(drm_dev, ctx->encoder); in fimd_bind()
1144 ret = fimd_clear_channels(ctx->crtc); in fimd_bind()
1149 return exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv); in fimd_bind()
1157 fimd_atomic_disable(ctx->crtc); in fimd_unbind()
1159 exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv); in fimd_unbind()
1161 if (ctx->encoder) in fimd_unbind()
1162 exynos_dpi_remove(ctx->encoder); in fimd_unbind()
1172 struct device *dev = &pdev->dev; in fimd_probe()
1177 if (!dev->of_node) in fimd_probe()
1178 return -ENODEV; in fimd_probe()
1182 return -ENOMEM; in fimd_probe()
1184 ctx->dev = dev; in fimd_probe()
1185 ctx->suspended = true; in fimd_probe()
1186 ctx->driver_data = of_device_get_match_data(dev); in fimd_probe()
1188 if (of_property_read_bool(dev->of_node, "samsung,invert-vden")) in fimd_probe()
1189 ctx->vidcon1 |= VIDCON1_INV_VDEN; in fimd_probe()
1190 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk")) in fimd_probe()
1191 ctx->vidcon1 |= VIDCON1_INV_VCLK; in fimd_probe()
1193 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); in fimd_probe()
1197 ctx->i80_if = true; in fimd_probe()
1199 if (ctx->driver_data->has_vidoutcon) in fimd_probe()
1200 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0; in fimd_probe()
1202 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0; in fimd_probe()
1205 * to enable I80 24-bit data interface. in fimd_probe()
1207 ctx->vidcon0 |= VIDCON0_DSI_EN; in fimd_probe()
1209 if (of_property_read_u32(i80_if_timings, "cs-setup", &val)) in fimd_probe()
1211 ctx->i80ifcon = LCD_CS_SETUP(val); in fimd_probe()
1212 if (of_property_read_u32(i80_if_timings, "wr-setup", &val)) in fimd_probe()
1214 ctx->i80ifcon |= LCD_WR_SETUP(val); in fimd_probe()
1215 if (of_property_read_u32(i80_if_timings, "wr-active", &val)) in fimd_probe()
1217 ctx->i80ifcon |= LCD_WR_ACTIVE(val); in fimd_probe()
1218 if (of_property_read_u32(i80_if_timings, "wr-hold", &val)) in fimd_probe()
1220 ctx->i80ifcon |= LCD_WR_HOLD(val); in fimd_probe()
1224 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, in fimd_probe()
1226 if (IS_ERR(ctx->sysreg)) { in fimd_probe()
1228 ctx->sysreg = NULL; in fimd_probe()
1231 ctx->bus_clk = devm_clk_get(dev, "fimd"); in fimd_probe()
1232 if (IS_ERR(ctx->bus_clk)) { in fimd_probe()
1234 return PTR_ERR(ctx->bus_clk); in fimd_probe()
1237 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); in fimd_probe()
1238 if (IS_ERR(ctx->lcd_clk)) { in fimd_probe()
1240 return PTR_ERR(ctx->lcd_clk); in fimd_probe()
1243 ctx->regs = devm_platform_ioremap_resource(pdev, 0); in fimd_probe()
1244 if (IS_ERR(ctx->regs)) in fimd_probe()
1245 return PTR_ERR(ctx->regs); in fimd_probe()
1247 ret = platform_get_irq_byname(pdev, ctx->i80_if ? "lcd_sys" : "vsync"); in fimd_probe()
1257 init_waitqueue_head(&ctx->wait_vsync_queue); in fimd_probe()
1258 atomic_set(&ctx->wait_vsync_event, 0); in fimd_probe()
1262 ctx->encoder = exynos_dpi_probe(dev); in fimd_probe()
1263 if (IS_ERR(ctx->encoder)) in fimd_probe()
1264 return PTR_ERR(ctx->encoder); in fimd_probe()
1282 pm_runtime_disable(&pdev->dev); in fimd_remove()
1284 component_del(&pdev->dev, &fimd_component_ops); in fimd_remove()
1291 clk_disable_unprepare(ctx->lcd_clk); in exynos_fimd_suspend()
1292 clk_disable_unprepare(ctx->bus_clk); in exynos_fimd_suspend()
1302 ret = clk_prepare_enable(ctx->bus_clk); in exynos_fimd_resume()
1310 ret = clk_prepare_enable(ctx->lcd_clk); in exynos_fimd_resume()
1328 .name = "exynos4-fb",