153 			*value = ~0ULL;  in etnaviv_gpu_get_param()
173 	return 0;  in etnaviv_gpu_get_param()
196 	return 0;  in etnaviv_gpu_reset_deassert()
215 		specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);  in etnaviv_hw_specs()
220 		gpu->identity.stream_count = etnaviv_field(specs[0],  in etnaviv_hw_specs()
222 		gpu->identity.register_max = etnaviv_field(specs[0],  in etnaviv_hw_specs()
224 		gpu->identity.thread_count = etnaviv_field(specs[0],  in etnaviv_hw_specs()
226 		gpu->identity.vertex_cache_size = etnaviv_field(specs[0],  in etnaviv_hw_specs()
228 		gpu->identity.shader_core_count = etnaviv_field(specs[0],  in etnaviv_hw_specs()
230 		gpu->identity.pixel_pipes = etnaviv_field(specs[0],  in etnaviv_hw_specs()
233 			etnaviv_field(specs[0],  in etnaviv_hw_specs()
254 	if (gpu->identity.stream_count == 0) {  in etnaviv_hw_specs()
255 		if (gpu->identity.model >= 0x1000)  in etnaviv_hw_specs()
280 	if (gpu->identity.vertex_cache_size == 0)  in etnaviv_hw_specs()
283 	if (gpu->identity.shader_core_count == 0) {  in etnaviv_hw_specs()
284 		if (gpu->identity.model >= 0x1000)  in etnaviv_hw_specs()
290 	if (gpu->identity.pixel_pipes == 0)  in etnaviv_hw_specs()
298 		if (gpu->identity.revision < 0x4000)  in etnaviv_hw_specs()
300 		else if (gpu->identity.revision < 0x4200)  in etnaviv_hw_specs()
309 	case 0:  in etnaviv_hw_specs()
310 		if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||  in etnaviv_hw_specs()
330 	if (gpu->identity.num_constants == 0)  in etnaviv_hw_specs()
333 	if (gpu->identity.varyings_count == 0) {  in etnaviv_hw_specs()
344 	if (etnaviv_is_model_rev(gpu, 0x5000, 0x5434) ||  in etnaviv_hw_specs()
345 	    etnaviv_is_model_rev(gpu, 0x4000, 0x5222) ||  in etnaviv_hw_specs()
346 	    etnaviv_is_model_rev(gpu, 0x4000, 0x5245) ||  in etnaviv_hw_specs()
347 	    etnaviv_is_model_rev(gpu, 0x4000, 0x5208) ||  in etnaviv_hw_specs()
348 	    etnaviv_is_model_rev(gpu, 0x3000, 0x5435) ||  in etnaviv_hw_specs()
349 	    etnaviv_is_model_rev(gpu, 0x2200, 0x5244) ||  in etnaviv_hw_specs()
350 	    etnaviv_is_model_rev(gpu, 0x2100, 0x5108) ||  in etnaviv_hw_specs()
351 	    etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||  in etnaviv_hw_specs()
352 	    etnaviv_is_model_rev(gpu, 0x1500, 0x5246) ||  in etnaviv_hw_specs()
353 	    etnaviv_is_model_rev(gpu, 0x880, 0x5107) ||  in etnaviv_hw_specs()
354 	    etnaviv_is_model_rev(gpu, 0x880, 0x5106))  in etnaviv_hw_specs()
365 	if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {  in etnaviv_hw_identify()
377 		 * Reading these two registers on GC600 rev 0x19 result in a  in etnaviv_hw_identify()
380 		if (!etnaviv_is_model_rev(gpu, 0x600, 0x19)) {  in etnaviv_hw_identify()
391 		if ((gpu->identity.model & 0xff00) == 0x0400 &&  in etnaviv_hw_identify()
393 			gpu->identity.model = gpu->identity.model & 0x0400;  in etnaviv_hw_identify()
397 		if (etnaviv_is_model_rev(gpu, 0x300, 0x2201)) {  in etnaviv_hw_identify()
400 			if (chipDate == 0x20080814 && chipTime == 0x12051100) {  in etnaviv_hw_identify()
405 				gpu->identity.revision = 0x1051;  in etnaviv_hw_identify()
416 		if (etnaviv_is_model_rev(gpu, 0x2000, 0xffff5450)) {  in etnaviv_hw_identify()
418 			gpu->identity.revision &= 0xffff;  in etnaviv_hw_identify()
421 		if (etnaviv_is_model_rev(gpu, 0x1000, 0x5037) && (chipDate == 0x20120617))  in etnaviv_hw_identify()
424 		if (etnaviv_is_model_rev(gpu, 0x320, 0x5303) && (chipDate == 0x20140511))  in etnaviv_hw_identify()
454 	     gpu->identity.revision < 0x2000)) {  in etnaviv_hw_identify()
460 		gpu->identity.minor_features0 = 0;  in etnaviv_hw_identify()
461 		gpu->identity.minor_features1 = 0;  in etnaviv_hw_identify()
462 		gpu->identity.minor_features2 = 0;  in etnaviv_hw_identify()
463 		gpu->identity.minor_features3 = 0;  in etnaviv_hw_identify()
464 		gpu->identity.minor_features4 = 0;  in etnaviv_hw_identify()
465 		gpu->identity.minor_features5 = 0;  in etnaviv_hw_identify()
529 				   200UL, 0xffffUL);  in etnaviv_gpu_update_clock()
543 		u32 pulse_eater = 0x01590880;  in etnaviv_hw_reset()
546 		gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, 0x0);  in etnaviv_hw_reset()
551 		pulse_eater |= BIT(0);  in etnaviv_hw_reset()
586 		if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {  in etnaviv_hw_reset()
595 		if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||  in etnaviv_hw_reset()
596 		    ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {  in etnaviv_hw_reset()
630 	return 0;  in etnaviv_hw_reset()
642 	if (gpu->identity.revision == 0x4301 ||  in etnaviv_gpu_enable_mlcg()
643 	    gpu->identity.revision == 0x4302)  in etnaviv_gpu_enable_mlcg()
660 	if (gpu->identity.revision < 0x5000 &&  in etnaviv_gpu_enable_mlcg()
666 	if (gpu->identity.revision < 0x5422)  in etnaviv_gpu_enable_mlcg()
670 	if (etnaviv_is_model_rev(gpu, 0x4000, 0x5222) ||  in etnaviv_gpu_enable_mlcg()
671 	    etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||  in etnaviv_gpu_enable_mlcg()
672 	    etnaviv_is_model_rev(gpu, 0x7000, 0x6202) ||  in etnaviv_gpu_enable_mlcg()
673 	    etnaviv_is_model_rev(gpu, 0x7000, 0x6203))  in etnaviv_gpu_enable_mlcg()
677 	if (etnaviv_is_model_rev(gpu, 0x7000, 0x6202))  in etnaviv_gpu_enable_mlcg()
682 	if (etnaviv_is_model_rev(gpu, 0x8000, 0x7200) ||  in etnaviv_gpu_enable_mlcg()
683 	    etnaviv_is_model_rev(gpu, 0x8000, 0x8002) ||  in etnaviv_gpu_enable_mlcg()
684 	    etnaviv_is_model_rev(gpu, 0x9200, 0x6304))  in etnaviv_gpu_enable_mlcg()
734 	u32 pulse_eater = 0x01590880;  in etnaviv_gpu_setup_pulse_eater()
736 	if (etnaviv_is_model_rev(gpu, 0x4000, 0x5208) ||  in etnaviv_gpu_setup_pulse_eater()
737 	    etnaviv_is_model_rev(gpu, 0x4000, 0x5222)) {  in etnaviv_gpu_setup_pulse_eater()
742 	if (etnaviv_is_model_rev(gpu, 0x1000, 0x5039) ||  in etnaviv_gpu_setup_pulse_eater()
743 	    etnaviv_is_model_rev(gpu, 0x1000, 0x5040)) {  in etnaviv_gpu_setup_pulse_eater()
748 	if ((gpu->identity.revision > 0x5420) &&  in etnaviv_gpu_setup_pulse_eater()
764 	if ((etnaviv_is_model_rev(gpu, 0x320, 0x5007) ||  in etnaviv_gpu_hw_init()
765 	     etnaviv_is_model_rev(gpu, 0x320, 0x5220)) &&  in etnaviv_gpu_hw_init()
766 	    gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {  in etnaviv_gpu_hw_init()
769 		mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;  in etnaviv_gpu_hw_init()
771 		if (gpu->identity.revision == 0x5007)  in etnaviv_gpu_hw_init()
772 			mc_memory_debug |= 0x0c;  in etnaviv_gpu_hw_init()
774 			mc_memory_debug |= 0x08;  in etnaviv_gpu_hw_init()
791 	if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108)) {  in etnaviv_gpu_hw_init()
796 			      VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);  in etnaviv_gpu_hw_init()
809 	gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);  in etnaviv_gpu_hw_init()
821 	if (ret < 0) {  in etnaviv_gpu_init()
834 	if (gpu->identity.model == 0) {  in etnaviv_gpu_init()
840 	if (gpu->identity.nn_core_count > 0)  in etnaviv_gpu_init()
844 	/* Exclude VG cores with FE2.0 */  in etnaviv_gpu_init()
847 		dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");  in etnaviv_gpu_init()
885 	 * On MC1.0 cores the linear window offset is ignored by the TS engine,  in etnaviv_gpu_init()
902 			 "Need to move linear window on MC1.0, disabling TS\n");  in etnaviv_gpu_init()
911 	for (i = 0; i < ARRAY_SIZE(gpu->event); i++)  in etnaviv_gpu_init()
922 	return 0;  in etnaviv_gpu_init()
942 	debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);  in verify_dma()
943 	debug->state[0]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);  in verify_dma()
945 	for (i = 0; i < 500; i++) {  in verify_dma()
949 		if (debug->address[0] != debug->address[1])  in verify_dma()
952 		if (debug->state[0] != debug->state[1])  in verify_dma()
966 	if (ret < 0)  in etnaviv_gpu_debugfs()
977 	seq_printf(m, "\t model: 0x%x\n", gpu->identity.model);  in etnaviv_gpu_debugfs()
978 	seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision);  in etnaviv_gpu_debugfs()
979 	seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id);  in etnaviv_gpu_debugfs()
980 	seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id);  in etnaviv_gpu_debugfs()
981 	seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id);  in etnaviv_gpu_debugfs()
984 	seq_printf(m, "\t major_features: 0x%08x\n",  in etnaviv_gpu_debugfs()
986 	seq_printf(m, "\t minor_features0: 0x%08x\n",  in etnaviv_gpu_debugfs()
988 	seq_printf(m, "\t minor_features1: 0x%08x\n",  in etnaviv_gpu_debugfs()
990 	seq_printf(m, "\t minor_features2: 0x%08x\n",  in etnaviv_gpu_debugfs()
992 	seq_printf(m, "\t minor_features3: 0x%08x\n",  in etnaviv_gpu_debugfs()
994 	seq_printf(m, "\t minor_features4: 0x%08x\n",  in etnaviv_gpu_debugfs()
996 	seq_printf(m, "\t minor_features5: 0x%08x\n",  in etnaviv_gpu_debugfs()
998 	seq_printf(m, "\t minor_features6: 0x%08x\n",  in etnaviv_gpu_debugfs()
1000 	seq_printf(m, "\t minor_features7: 0x%08x\n",  in etnaviv_gpu_debugfs()
1002 	seq_printf(m, "\t minor_features8: 0x%08x\n",  in etnaviv_gpu_debugfs()
1004 	seq_printf(m, "\t minor_features9: 0x%08x\n",  in etnaviv_gpu_debugfs()
1006 	seq_printf(m, "\t minor_features10: 0x%08x\n",  in etnaviv_gpu_debugfs()
1008 	seq_printf(m, "\t minor_features11: 0x%08x\n",  in etnaviv_gpu_debugfs()
1037 	seq_printf(m, "\taxi: 0x%08x\n", axi);  in etnaviv_gpu_debugfs()
1038 	seq_printf(m, "\tidle: 0x%08x\n", idle);  in etnaviv_gpu_debugfs()
1040 	if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)  in etnaviv_gpu_debugfs()
1042 	if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)  in etnaviv_gpu_debugfs()
1044 	if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)  in etnaviv_gpu_debugfs()
1046 	if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)  in etnaviv_gpu_debugfs()
1048 	if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)  in etnaviv_gpu_debugfs()
1050 	if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)  in etnaviv_gpu_debugfs()
1052 	if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)  in etnaviv_gpu_debugfs()
1054 	if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)  in etnaviv_gpu_debugfs()
1056 	if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)  in etnaviv_gpu_debugfs()
1058 	if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)  in etnaviv_gpu_debugfs()
1060 	if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)  in etnaviv_gpu_debugfs()
1062 	if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)  in etnaviv_gpu_debugfs()
1064 	if ((idle & VIVS_HI_IDLE_STATE_BL) == 0)  in etnaviv_gpu_debugfs()
1066 	if ((idle & VIVS_HI_IDLE_STATE_ASYNCFE) == 0)  in etnaviv_gpu_debugfs()
1068 	if ((idle & VIVS_HI_IDLE_STATE_MC) == 0)  in etnaviv_gpu_debugfs()
1070 	if ((idle & VIVS_HI_IDLE_STATE_PPA) == 0)  in etnaviv_gpu_debugfs()
1072 	if ((idle & VIVS_HI_IDLE_STATE_WD) == 0)  in etnaviv_gpu_debugfs()
1074 	if ((idle & VIVS_HI_IDLE_STATE_NN) == 0)  in etnaviv_gpu_debugfs()
1076 	if ((idle & VIVS_HI_IDLE_STATE_TP) == 0)  in etnaviv_gpu_debugfs()
1087 		seq_printf(m, "\t read0: 0x%08x\n", read0);  in etnaviv_gpu_debugfs()
1088 		seq_printf(m, "\t read1: 0x%08x\n", read1);  in etnaviv_gpu_debugfs()
1089 		seq_printf(m, "\t write: 0x%08x\n", write);  in etnaviv_gpu_debugfs()
1094 	if (debug.address[0] == debug.address[1] &&  in etnaviv_gpu_debugfs()
1095 	    debug.state[0] == debug.state[1]) {  in etnaviv_gpu_debugfs()
1097 	} else if (debug.address[0] == debug.address[1]) {  in etnaviv_gpu_debugfs()
1103 	seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);  in etnaviv_gpu_debugfs()
1104 	seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);  in etnaviv_gpu_debugfs()
1105 	seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);  in etnaviv_gpu_debugfs()
1106 	seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);  in etnaviv_gpu_debugfs()
1107 	seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",  in etnaviv_gpu_debugfs()
1110 	ret = 0;  in etnaviv_gpu_debugfs()
1147 	return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0;  in etnaviv_fence_signaled()
1189 	return (s32)(a - b) > 0;  in fence_after()
1200 	unsigned i, acquired = 0, rpm_count = 0;  in event_alloc()
1203 	for (i = 0; i < nr_events; i++) {  in event_alloc()
1220 	for (i = 0; i < nr_events; i++) {  in event_alloc()
1224 		memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));  in event_alloc()
1230 	for (i = 0; i < nr_events; i++) {  in event_alloc()
1237 	return 0;  in event_alloc()
1240 	for (i = 0; i < rpm_count; i++)  in event_alloc()
1243 	for (i = 0; i < acquired; i++)  in event_alloc()
1283 		return 0;  in etnaviv_gpu_wait_fence_interruptible()
1287 		ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;  in etnaviv_gpu_wait_fence_interruptible()
1292 		if (ret == 0)  in etnaviv_gpu_wait_fence_interruptible()
1295 			ret = 0;  in etnaviv_gpu_wait_fence_interruptible()
1320 		return !is_active(etnaviv_obj) ? 0 : -EBUSY;  in etnaviv_gpu_wait_obj_inactive()
1327 	if (ret > 0)  in etnaviv_gpu_wait_obj_inactive()
1328 		return 0;  in etnaviv_gpu_wait_obj_inactive()
1341 	for (i = 0; i < submit->nr_pmrs; i++) {  in sync_point_perfmon_sample()
1384 	for (i = 0; i < submit->nr_pmrs; i++) {  in sync_point_perfmon_sample_post()
1421 		for (i = 0; i < nr_events; i++)  in etnaviv_gpu_submit()
1441 	gpu->event[event[0]].fence = gpu_fence;  in etnaviv_gpu_submit()
1444 			     event[0], &submit->cmdbuf);  in etnaviv_gpu_submit()
1496 	if (pm_runtime_get_sync(gpu->dev) < 0)  in etnaviv_gpu_recover_hang()
1537 	dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);  in dump_mmu_fault()
1539 	for (i = 0; i < 4; i++) {  in dump_mmu_fault()
1557 				    "MMU %d fault (%s) addr 0x%08x\n",  in dump_mmu_fault()
1569 	if (intr != 0) {  in irq_handler()
1575 		dev_dbg(gpu->dev, "intr 0x%08x\n", intr);  in irq_handler()
1589 		while ((event = ffs(intr)) != 0) {  in irq_handler()
1611 			 * - allocate and queue event 0  in irq_handler()
1613 			 * - event 0 completes, we process it  in irq_handler()
1614 			 * - allocate and queue event 0  in irq_handler()
1615 			 * - event 1 and event 0 complete  in irq_handler()
1616 			 * we can end up processing event 0 first, then 1.  in irq_handler()
1651 	return 0;  in etnaviv_gpu_clk_enable()
1670 	return 0;  in etnaviv_gpu_clk_disable()
1681 			return 0;  in etnaviv_gpu_wait_idle()
1685 				 "timed out waiting for idle: idle=0x%x\n",  in etnaviv_gpu_wait_idle()
1728 	return 0;  in etnaviv_gpu_hw_resume()
1737 	return 0;  in etnaviv_gpu_cooling_get_max_state()
1748 	return 0;  in etnaviv_gpu_cooling_get_cur_state()
1763 	return 0;  in etnaviv_gpu_cooling_set_cur_state()
1787 	gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0);  in etnaviv_gpu_bind()
1799 		if (ret < 0)  in etnaviv_gpu_bind()
1813 	return 0;  in etnaviv_gpu_bind()
1889 	gpu->mmio = devm_platform_ioremap_resource(pdev, 0);  in etnaviv_gpu_platform_probe()
1905 	gpu->irq = platform_get_irq(pdev, 0);  in etnaviv_gpu_platform_probe()
1906 	if (gpu->irq < 0)  in etnaviv_gpu_platform_probe()
1909 	err = devm_request_irq(dev, gpu->irq, irq_handler, 0,  in etnaviv_gpu_platform_probe()
1952 	if (err < 0) {  in etnaviv_gpu_platform_probe()
1957 	return 0;  in etnaviv_gpu_platform_probe()
1985 		dev_warn_ratelimited(dev, "GPU not yet idle, mask: 0x%08x\n",  in etnaviv_gpu_rpm_suspend()
2015 	return 0;  in etnaviv_gpu_rpm_resume()