Lines Matching refs:dpcd
286 static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in __read_delay()
302 if (cr && dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) in __read_delay()
328 rd_interval = dpcd[offset]; in __read_delay()
341 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_clock_recovery_delay()
344 return __read_delay(aux, dpcd, dp_phy, uhbr, true); in drm_dp_read_clock_recovery_delay()
348 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_channel_eq_delay()
351 return __read_delay(aux, dpcd, dp_phy, uhbr, false); in drm_dp_read_channel_eq_delay()
376 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_link_train_clock_recovery_delay()
378 u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & in drm_dp_link_train_clock_recovery_delay()
382 if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) in drm_dp_link_train_clock_recovery_delay()
400 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_link_train_channel_eq_delay()
403 dpcd[DP_TRAINING_AUX_RD_INTERVAL] & in drm_dp_link_train_channel_eq_delay()
986 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_is_type()
989 return drm_dp_is_branch(dpcd) && in drm_dp_downstream_is_type()
990 dpcd[DP_DPCD_REV] >= 0x11 && in drm_dp_downstream_is_type()
1003 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_is_tmds()
1007 if (dpcd[DP_DPCD_REV] < 0x11) { in drm_dp_downstream_is_tmds()
1008 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { in drm_dp_downstream_is_tmds()
1090 static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_downstream_port_count()
1092 u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK; in drm_dp_downstream_port_count()
1094 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4) in drm_dp_downstream_port_count()
1101 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_read_extended_dpcd_caps()
1113 if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & in drm_dp_read_extended_dpcd_caps()
1124 if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) { in drm_dp_read_extended_dpcd_caps()
1127 aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]); in drm_dp_read_extended_dpcd_caps()
1131 if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext))) in drm_dp_read_extended_dpcd_caps()
1134 drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd); in drm_dp_read_extended_dpcd_caps()
1136 memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext)); in drm_dp_read_extended_dpcd_caps()
1155 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_read_dpcd_caps()
1159 ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE); in drm_dp_read_dpcd_caps()
1162 if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0) in drm_dp_read_dpcd_caps()
1165 ret = drm_dp_read_extended_dpcd_caps(aux, dpcd); in drm_dp_read_dpcd_caps()
1169 drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd); in drm_dp_read_dpcd_caps()
1189 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_downstream_info()
1198 if (!drm_dp_is_branch(dpcd) || dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) in drm_dp_read_downstream_info()
1205 len = drm_dp_downstream_port_count(dpcd); in drm_dp_read_downstream_info()
1209 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) in drm_dp_read_downstream_info()
1232 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_max_dotclock()
1235 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_max_dotclock()
1238 if (dpcd[DP_DPCD_REV] < 0x11) in drm_dp_downstream_max_dotclock()
1243 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_max_dotclock()
1261 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_max_tmds_clock()
1265 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_max_tmds_clock()
1268 if (dpcd[DP_DPCD_REV] < 0x11) { in drm_dp_downstream_max_tmds_clock()
1269 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { in drm_dp_downstream_max_tmds_clock()
1303 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_max_tmds_clock()
1307 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_max_tmds_clock()
1326 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_min_tmds_clock()
1330 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_min_tmds_clock()
1333 if (dpcd[DP_DPCD_REV] < 0x11) { in drm_dp_downstream_min_tmds_clock()
1334 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { in drm_dp_downstream_min_tmds_clock()
1369 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_max_bpc()
1373 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_max_bpc()
1376 if (dpcd[DP_DPCD_REV] < 0x11) { in drm_dp_downstream_max_bpc()
1377 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { in drm_dp_downstream_max_bpc()
1395 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_max_bpc()
1425 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_420_passthrough()
1428 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_420_passthrough()
1431 if (dpcd[DP_DPCD_REV] < 0x13) in drm_dp_downstream_420_passthrough()
1438 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_420_passthrough()
1456 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_444_to_420_conversion()
1459 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_444_to_420_conversion()
1462 if (dpcd[DP_DPCD_REV] < 0x13) in drm_dp_downstream_444_to_420_conversion()
1467 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_444_to_420_conversion()
1487 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_rgb_to_ycbcr_conversion()
1491 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_rgb_to_ycbcr_conversion()
1494 if (dpcd[DP_DPCD_REV] < 0x13) in drm_dp_downstream_rgb_to_ycbcr_conversion()
1499 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_rgb_to_ycbcr_conversion()
1521 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_mode()
1527 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_mode()
1530 if (dpcd[DP_DPCD_REV] < 0x11) in drm_dp_downstream_mode()
1587 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_debug()
1592 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & in drm_dp_downstream_debug()
1600 bool branch_device = drm_dp_is_branch(dpcd); in drm_dp_downstream_debug()
1648 clk = drm_dp_downstream_max_dotclock(dpcd, port_cap); in drm_dp_downstream_debug()
1652 clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, drm_edid); in drm_dp_downstream_debug()
1656 clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, drm_edid); in drm_dp_downstream_debug()
1660 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, drm_edid); in drm_dp_downstream_debug()
1674 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_subconnector_type()
1678 if (!drm_dp_is_branch(dpcd)) in drm_dp_subconnector_type()
1681 if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) { in drm_dp_subconnector_type()
1682 type = dpcd[DP_DOWNSTREAMPORT_PRESENT] & in drm_dp_subconnector_type()
1731 const u8 *dpcd, in drm_dp_set_subconnector_property() argument
1737 subconnector = drm_dp_subconnector_type(dpcd, port_cap); in drm_dp_set_subconnector_property()
1757 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_sink_count_cap()
1762 dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 && in drm_dp_read_sink_count_cap()
1763 dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT && in drm_dp_read_sink_count_cap()
2764 const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address, in drm_dp_read_lttpr_regs()
2772 int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size; in drm_dp_read_lttpr_regs()
2800 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_lttpr_common_caps()
2803 return drm_dp_read_lttpr_regs(aux, dpcd, in drm_dp_read_lttpr_common_caps()
2821 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_lttpr_phy_caps()
2825 return drm_dp_read_lttpr_regs(aux, dpcd, in drm_dp_read_lttpr_phy_caps()
3261 bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_as_sdp_supported()
3265 if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13) in drm_dp_as_sdp_supported()
3286 bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_vsc_sdp_supported()
3290 if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13) in drm_dp_vsc_sdp_supported()
3384 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_get_pcon_max_frl_bw()