Lines Matching +full:rate +full:- +full:np +full:- +full:ms
1 // SPDX-License-Identifier: GPL-2.0
145 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
146 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality.
147 * @gpio_aux: AUX-bus sub device for GPIO controller functionality.
148 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality.
149 * @pwm_aux: AUX-bus sub device for PWM controller functionality.
164 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
172 * serves double-duty of keeping track of the direction and
178 * each other's read-modify-write.
245 ret = regmap_read(pdata->regmap, reg, ®_val);
247 dev_err(pdata->dev, "fail to read raw reg %#x: %d\n",
262 ret = regmap_bulk_read(pdata->regmap, reg, buf, ARRAY_SIZE(buf));
276 regmap_bulk_write(pdata->regmap, reg, buf, ARRAY_SIZE(buf));
284 drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
288 drm_atomic_get_new_crtc_state(state, conn_state->crtc);
290 return &crtc_state->adjusted_mode;
298 get_new_adjusted_display_mode(&pdata->bridge, state);
300 bit_rate_khz = mode->clock *
301 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
302 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
333 if (pdata->refclk) {
334 refclk_rate = clk_get_rate(pdata->refclk);
337 clk_prepare_enable(pdata->refclk);
349 /* avoid buffer overflow and "1" is the default rate in the datasheet. */
353 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
360 pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i];
366 mutex_lock(&pdata->comms_mutex);
375 * this signal by between 100 ms and 400 ms (depending on process,
376 * voltage, and temperate--I measured it at about 200 ms). One
377 * particular panel asserted HPD 84 ms after it was powered on meaning
378 * that we saw HPD 284 ms after power on. ...but the same panel said
380 * 200 ms. We'll assume that the panel driver will have the hardcoded
387 * bridge type is set. We are using bridge type instead of "no-hpd"
392 if (pdata->bridge.type != DRM_MODE_CONNECTOR_DisplayPort)
393 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
396 pdata->comms_enabled = true;
398 mutex_unlock(&pdata->comms_mutex);
403 mutex_lock(&pdata->comms_mutex);
405 pdata->comms_enabled = false;
406 clk_disable_unprepare(pdata->refclk);
408 mutex_unlock(&pdata->comms_mutex);
414 const struct i2c_client *client = to_i2c_client(pdata->dev);
417 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
426 gpiod_set_value_cansleep(pdata->enable_gpio, 1);
446 if (pdata->refclk)
449 if (client->irq) {
450 ret = regmap_update_bits(pdata->regmap, SN_IRQ_EN_REG, IRQ_EN,
453 dev_err(pdata->dev, "Failed to enable IRQ events: %d\n", ret);
464 if (pdata->refclk)
467 gpiod_set_value_cansleep(pdata->enable_gpio, 0);
469 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
484 struct ti_sn65dsi86 *pdata = s->private;
489 pm_runtime_get_sync(pdata->dev);
493 regmap_read(pdata->regmap, reg, &val);
497 pm_runtime_put_autosuspend(pdata->dev);
503 /* -----------------------------------------------------------------------------
511 struct device *dev = pdata->dev;
516 id = (client->adapter->nr << 10) | client->addr;
520 return -ENODEV;
526 /* -----------------------------------------------------------------------------
539 u32 request = msg->request & ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE);
540 u32 request_val = AUX_CMD_REQ(msg->request);
541 u8 *buf = msg->buffer;
542 unsigned int len = msg->size;
546 u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG];
549 return -EINVAL;
551 pm_runtime_get_sync(pdata->dev);
552 mutex_lock(&pdata->comms_mutex);
557 * do it. Fail right away. This prevents non-refclk users from reading
560 if (!pdata->comms_enabled) {
561 ret = -EIO;
570 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val);
572 msg->reply = 0;
575 ret = -EINVAL;
580 put_unaligned_be32((msg->address & SN_AUX_ADDR_MASK) << 8 | len,
582 regmap_bulk_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, addr_len,
586 regmap_bulk_write(pdata->regmap, SN_AUX_WDATA_REG(0), buf, len);
589 regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG,
594 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND);
597 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val,
602 ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val);
612 ret = -ETIMEDOUT;
617 ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &short_len);
625 msg->reply |= DP_AUX_I2C_REPLY_NACK;
629 msg->reply |= DP_AUX_NATIVE_REPLY_NACK;
637 ret = regmap_bulk_read(pdata->regmap, SN_AUX_RDATA_REG(0), buf, len);
640 mutex_unlock(&pdata->comms_mutex);
641 pm_runtime_mark_last_busy(pdata->dev);
642 pm_runtime_put_autosuspend(pdata->dev);
657 * 500ms delay.
670 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
673 pdata->aux.name = "ti-sn65dsi86-aux";
674 pdata->aux.dev = &adev->dev;
675 pdata->aux.transfer = ti_sn_aux_transfer;
676 pdata->aux.wait_hpd_asserted = ti_sn_aux_wait_hpd_asserted;
677 drm_dp_aux_init(&pdata->aux);
679 ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux);
687 return ti_sn65dsi86_add_aux_device(pdata, &pdata->bridge_aux, "bridge");
701 /*------------------------------------------------------------------------------
715 struct device *dev = pdata->dev;
721 host = of_find_mipi_dsi_host_by_node(pdata->host_node);
723 return -EPROBE_DEFER;
725 dsi = devm_mipi_dsi_device_register_full(&adev->dev, host, &info);
730 dsi->lanes = 4;
731 dsi->format = MIPI_DSI_FMT_RGB888;
732 dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
736 regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val);
739 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS;
741 pdata->dsi = dsi;
743 return devm_mipi_dsi_attach(&adev->dev, dsi);
753 pdata->aux.drm_dev = bridge->dev;
754 ret = drm_dp_aux_register(&pdata->aux);
756 drm_err(bridge->dev, "Failed to register DP AUX channel: %d\n", ret);
764 ret = drm_bridge_attach(encoder, pdata->next_bridge,
765 &pdata->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
772 pdata->connector = drm_bridge_connector_init(pdata->bridge.dev,
773 pdata->bridge.encoder);
774 if (IS_ERR(pdata->connector)) {
775 ret = PTR_ERR(pdata->connector);
779 drm_connector_attach_encoder(pdata->connector, pdata->bridge.encoder);
784 drm_dp_aux_unregister(&pdata->aux);
790 drm_dp_aux_unregister(&bridge_to_ti_sn65dsi86(bridge)->aux);
799 if (mode->clock > 594000)
807 if ((mode->hsync_start - mode->hdisplay) > 0xff)
810 if ((mode->vsync_start - mode->vdisplay) > 0xff)
813 if ((mode->hsync_end - mode->hsync_start) > 0x7fff)
816 if ((mode->vsync_end - mode->vsync_start) > 0x7fff)
819 if ((mode->htotal - mode->hsync_end) > 0xff)
822 if ((mode->vtotal - mode->vsync_end) > 0xff)
834 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0);
843 get_new_adjusted_display_mode(&pdata->bridge, state);
846 bit_rate_mhz = (mode->clock / 1000) *
847 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
848 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
852 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
853 regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
858 if (connector->display_info.bpc <= 6)
866 * LUT values corresponds to dp data rate supported
880 get_new_adjusted_display_mode(&pdata->bridge, state);
882 /* Calculate minimum bit rate based on our pixel clock. */
883 bit_rate_khz = mode->clock * bpp;
885 /* Calculate minimum DP data rate, taking 80% as per DP spec */
887 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN);
889 for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
905 ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val);
907 DRM_DEV_ERROR(pdata->dev,
916 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES,
920 DRM_DEV_ERROR(pdata->dev,
921 "Can't read supported rate table (%d)\n", ret);
946 DRM_DEV_ERROR(pdata->dev,
951 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val);
953 DRM_DEV_ERROR(pdata->dev,
954 "Can't read max rate (%d); assuming 5.4 GHz\n",
961 DRM_DEV_ERROR(pdata->dev,
962 "Unexpected max rate (%#x); assuming 5.4 GHz\n",
983 get_new_adjusted_display_mode(&pdata->bridge, state);
986 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
988 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
992 mode->hdisplay);
994 mode->vdisplay);
995 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
996 (mode->hsync_end - mode->hsync_start) & 0xFF);
997 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
998 (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) |
1000 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
1001 (mode->vsync_end - mode->vsync_start) & 0xFF);
1002 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
1003 (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) |
1006 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
1007 (mode->htotal - mode->hsync_end) & 0xFF);
1008 regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
1009 (mode->vtotal - mode->vsync_end) & 0xFF);
1011 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
1012 (mode->hsync_start - mode->hdisplay) & 0xFF);
1013 regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
1014 (mode->vsync_start - mode->vdisplay) & 0xFF);
1016 usleep_range(10000, 10500); /* 10ms delay recommended by spec */
1024 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data);
1026 DRM_DEV_ERROR(pdata->dev,
1042 regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
1046 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
1048 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val,
1064 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
1065 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val,
1073 ret = -EIO;
1082 DRM_DEV_INFO(pdata->dev, "Link training needed %d retries\n", i);
1087 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1097 const char *last_err_str = "No supported DP rate";
1101 int ret = -EINVAL;
1106 bridge->encoder);
1108 dev_err_ratelimited(pdata->dev, "Could not get the connector\n");
1113 pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes);
1116 val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes);
1117 regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
1120 regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign);
1121 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK,
1122 pdata->ln_polrs << LN_POLRS_OFFSET);
1136 if (pdata->bridge.type == DRM_MODE_CONNECTOR_eDP) {
1137 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET,
1140 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG,
1143 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG,
1150 regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val);
1153 val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
1154 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
1171 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret);
1179 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
1188 pm_runtime_get_sync(pdata->dev);
1190 if (!pdata->refclk)
1203 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
1205 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0);
1207 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1209 if (!pdata->refclk)
1212 pm_runtime_put_sync(pdata->dev);
1225 * debounce time (~100-400 ms).
1228 regmap_read(pdata->regmap, SN_HPD_DISABLE_REG, &val);
1239 return drm_edid_read_ddc(connector, &pdata->aux.ddc);
1247 debugfs = debugfs_create_dir(dev_name(pdata->dev), root);
1254 const struct i2c_client *client = to_i2c_client(pdata->dev);
1263 pm_runtime_get_sync(pdata->dev);
1265 mutex_lock(&pdata->hpd_mutex);
1266 pdata->hpd_enabled = true;
1267 mutex_unlock(&pdata->hpd_mutex);
1269 if (client->irq) {
1270 ret = regmap_set_bits(pdata->regmap, SN_IRQ_EVENTS_EN_REG,
1273 dev_err(pdata->dev, "Failed to enable HPD events: %d\n", ret);
1280 const struct i2c_client *client = to_i2c_client(pdata->dev);
1283 if (client->irq) {
1284 ret = regmap_clear_bits(pdata->regmap, SN_IRQ_EVENTS_EN_REG,
1287 dev_err(pdata->dev, "Failed to disable HPD events: %d\n", ret);
1290 mutex_lock(&pdata->hpd_mutex);
1291 pdata->hpd_enabled = false;
1292 mutex_unlock(&pdata->hpd_mutex);
1294 pm_runtime_put_autosuspend(pdata->dev);
1316 struct device_node *np)
1330 * data-lanes but not lane-polarities but not vice versa.
1336 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1339 of_property_read_u32_array(endpoint, "data-lanes",
1341 of_property_read_u32_array(endpoint, "lane-polarities",
1350 * data-lanes had fewer elements so that we nicely initialize
1353 for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) {
1359 pdata->dp_lanes = dp_lanes;
1360 pdata->ln_assign = ln_assign;
1361 pdata->ln_polrs = ln_polrs;
1366 struct device_node *np = pdata->dev->of_node;
1368 pdata->host_node = of_graph_get_remote_node(np, 0, 0);
1370 if (!pdata->host_node) {
1372 return -ENODEV;
1381 struct drm_device *dev = pdata->bridge.dev;
1388 dev_err(pdata->dev, "Failed to read IRQ status: %d\n", ret);
1394 dev_dbg(pdata->dev, "(SN_IRQ_STATUS_REG = %#x)\n", status);
1398 ret = regmap_write(pdata->regmap, SN_IRQ_STATUS_REG, status);
1400 dev_err(pdata->dev, "Failed to clear IRQ status: %d\n", ret);
1405 mutex_lock(&pdata->hpd_mutex);
1406 if (pdata->hpd_enabled && hpd_event)
1408 mutex_unlock(&pdata->hpd_mutex);
1416 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1417 struct device_node *np = pdata->dev->of_node;
1420 pdata->next_bridge = devm_drm_of_get_bridge(&adev->dev, np, 1, 0);
1421 if (IS_ERR(pdata->next_bridge))
1422 return dev_err_probe(&adev->dev, PTR_ERR(pdata->next_bridge),
1425 ti_sn_bridge_parse_lanes(pdata, np);
1431 pdata->bridge.of_node = np;
1432 pdata->bridge.type = pdata->next_bridge->type == DRM_MODE_CONNECTOR_DisplayPort
1435 if (pdata->bridge.type == DRM_MODE_CONNECTOR_DisplayPort) {
1436 pdata->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT |
1449 mutex_lock(&pdata->comms_mutex);
1450 if (pdata->comms_enabled)
1451 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG,
1453 mutex_unlock(&pdata->comms_mutex);
1456 drm_bridge_add(&pdata->bridge);
1460 dev_err_probe(&adev->dev, ret, "failed to attach dsi host\n");
1467 drm_bridge_remove(&pdata->bridge);
1473 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1478 drm_bridge_remove(&pdata->bridge);
1480 of_node_put(pdata->host_node);
1495 /* -----------------------------------------------------------------------------
1501 return atomic_xchg(&pdata->pwm_pin_busy, 1) ? -EBUSY : 0;
1506 atomic_set(&pdata->pwm_pin_busy, 0);
1530 * - The PWM signal is not driven when the chip is powered down, or in its
1532 * described in the documentation. In order to save power, state->enabled is
1535 * - Changing both period and duty_cycle is not done atomically, neither is the
1536 * multi-byte register updates, so the output might briefly be undefined
1551 if (!pdata->pwm_enabled) {
1557 if (state->enabled) {
1558 if (!pdata->pwm_enabled) {
1564 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1577 * PWM_FREQ = -----------------------------------
1592 * PWM_PRE_DIV >= -------------------------
1601 * BACKLIGHT_SCALE = ---------------------- - 1
1609 if (state->period <= NSEC_PER_SEC / pdata->pwm_refclk_freq) {
1610 ret = -EINVAL;
1619 pdata->pwm_refclk_freq);
1620 period = min(state->period, period_max);
1622 pre_div = DIV64_U64_ROUND_UP(period * pdata->pwm_refclk_freq,
1624 scale = div64_u64(period * pdata->pwm_refclk_freq, (u64)NSEC_PER_SEC * pre_div) - 1;
1630 * ------- = ---------------------
1637 backlight = div64_u64(state->duty_cycle * pdata->pwm_refclk_freq,
1642 ret = regmap_write(pdata->regmap, SN_PWM_PRE_DIV_REG, pre_div);
1652 pwm_en_inv = FIELD_PREP(SN_PWM_EN_MASK, state->enabled) |
1653 FIELD_PREP(SN_PWM_INV_MASK, state->polarity == PWM_POLARITY_INVERSED);
1654 ret = regmap_write(pdata->regmap, SN_PWM_EN_INV_REG, pwm_en_inv);
1660 pdata->pwm_enabled = state->enabled;
1663 if (!pdata->pwm_enabled)
1679 ret = regmap_read(pdata->regmap, SN_PWM_EN_INV_REG, &pwm_en_inv);
1691 ret = regmap_read(pdata->regmap, SN_PWM_PRE_DIV_REG, &pre_div);
1695 state->enabled = FIELD_GET(SN_PWM_EN_MASK, pwm_en_inv);
1697 state->polarity = PWM_POLARITY_INVERSED;
1699 state->polarity = PWM_POLARITY_NORMAL;
1701 state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * (scale + 1),
1702 pdata->pwm_refclk_freq);
1703 state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * backlight,
1704 pdata->pwm_refclk_freq);
1706 if (state->duty_cycle > state->period)
1707 state->duty_cycle = state->period;
1723 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1725 pdata->pchip = chip = devm_pwmchip_alloc(&adev->dev, 1, 0);
1731 chip->ops = &ti_sn_pwm_ops;
1732 chip->of_xlate = of_pwm_single_xlate;
1734 devm_pm_runtime_enable(&adev->dev);
1741 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1743 pwmchip_remove(pdata->pchip);
1745 if (pdata->pwm_enabled)
1746 pm_runtime_put_sync(&adev->dev);
1779 /* -----------------------------------------------------------------------------
1788 if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells))
1789 return -EINVAL;
1791 if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1)
1792 return -EINVAL;
1795 *flags = gpiospec->args[1];
1797 return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET;
1811 return test_bit(offset, pdata->gchip_output) ?
1823 * powered--we just power it on to read the pin. NOTE: part of
1829 pm_runtime_get_sync(pdata->dev);
1830 ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val);
1831 pm_runtime_put_autosuspend(pdata->dev);
1845 return regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG,
1857 if (!test_and_clear_bit(offset, pdata->gchip_output))
1860 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1864 set_bit(offset, pdata->gchip_output);
1873 pm_runtime_put_autosuspend(pdata->dev);
1885 if (test_and_set_bit(offset, pdata->gchip_output))
1888 pm_runtime_get_sync(pdata->dev);
1894 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1898 clear_bit(offset, pdata->gchip_output);
1899 pm_runtime_put_autosuspend(pdata->dev);
1933 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1937 if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller"))
1940 pdata->gchip.label = dev_name(pdata->dev);
1941 pdata->gchip.parent = pdata->dev;
1942 pdata->gchip.owner = THIS_MODULE;
1943 pdata->gchip.of_xlate = tn_sn_bridge_of_xlate;
1944 pdata->gchip.of_gpio_n_cells = 2;
1945 pdata->gchip.request = ti_sn_bridge_gpio_request;
1946 pdata->gchip.free = ti_sn_bridge_gpio_free;
1947 pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction;
1948 pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input;
1949 pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output;
1950 pdata->gchip.get = ti_sn_bridge_gpio_get;
1951 pdata->gchip.set = ti_sn_bridge_gpio_set;
1952 pdata->gchip.can_sleep = true;
1953 pdata->gchip.names = ti_sn_bridge_gpio_names;
1954 pdata->gchip.ngpio = SN_NUM_GPIOS;
1955 pdata->gchip.base = -1;
1956 ret = devm_gpiochip_add_data(&adev->dev, &pdata->gchip, pdata);
1958 dev_err(pdata->dev, "can't add gpio chip\n");
1993 /* -----------------------------------------------------------------------------
2011 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
2013 return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM,
2014 pdata->supplies);
2019 struct device *dev = &client->dev;
2024 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
2026 return -ENODEV;
2033 pdata->dev = dev;
2035 mutex_init(&pdata->hpd_mutex);
2036 mutex_init(&pdata->comms_mutex);
2038 pdata->regmap = devm_regmap_init_i2c(client,
2040 if (IS_ERR(pdata->regmap))
2041 return dev_err_probe(dev, PTR_ERR(pdata->regmap),
2044 pdata->enable_gpio = devm_gpiod_get_optional(dev, "enable",
2046 if (IS_ERR(pdata->enable_gpio))
2047 return dev_err_probe(dev, PTR_ERR(pdata->enable_gpio),
2054 pdata->refclk = devm_clk_get_optional(dev, "refclk");
2055 if (IS_ERR(pdata->refclk))
2056 return dev_err_probe(dev, PTR_ERR(pdata->refclk),
2060 pm_runtime_set_autosuspend_delay(pdata->dev, 500);
2061 pm_runtime_use_autosuspend(pdata->dev);
2067 ret = regmap_bulk_read(pdata->regmap, SN_DEVICE_ID_REGS, id_buf, ARRAY_SIZE(id_buf));
2074 return dev_err_probe(dev, -EOPNOTSUPP, "unsupported device id\n");
2076 if (client->irq) {
2077 ret = devm_request_threaded_irq(pdata->dev, client->irq, NULL,
2080 dev_name(pdata->dev), pdata);
2088 * motiviation here is to solve the chicken-and-egg problem of probe
2092 * bus or the pwm_chip. Having sub-devices allows the some sub devices
2093 * to finish probing even if others return -EPROBE_DEFER and gets us
2098 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->gpio_aux, "gpio");
2104 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->pwm_aux, "pwm");
2115 return ti_sn65dsi86_add_aux_device(pdata, &pdata->aux_aux, "aux");