Lines Matching +full:write +full:- +full:to +full:- +full:write
1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <sound/hdmi-codec.h>
25 #include <media/cec-notifier.h>
27 #include <dt-bindings/display/tda998x.h>
99 /* The TDA9988 series of devices use a paged register scheme.. to simplify
100 * things we encode the page # in upper bits of the register #. To read/
101 * write a given register, we need to make sure CURPAGE register is set
109 #define REG_CURPAGE 0xff /* write */
114 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
122 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
125 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
126 #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
127 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
131 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
135 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
136 #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
137 #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
139 #define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
140 #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
141 #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
142 #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
143 #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
144 #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
149 #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
154 #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
159 #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
168 #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
175 #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
178 #define REG_MUX_AP REG(0x00, 0x26) /* read/write */
181 #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
182 #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
185 #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
186 #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
187 #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
188 #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
189 #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
190 #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
191 #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
192 #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
193 #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
194 #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
195 #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
196 #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
197 #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
198 #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
199 #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
200 #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
201 #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
202 #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
203 #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
204 #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
205 #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
206 #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
207 #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
208 #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
209 #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
210 #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
211 #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
212 #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
213 #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
214 #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
215 #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
216 #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
217 #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
218 #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
219 #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
220 #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
221 #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
222 #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
223 #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
224 #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
225 #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
226 #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
234 #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
242 #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
243 #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
248 #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
254 #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
256 #define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
260 #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
268 #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
272 #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
275 #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
279 #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
280 #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
281 #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
282 #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
283 #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
284 #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
285 #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
286 #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
287 #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
294 #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
298 #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
304 #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
305 #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
306 #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
307 #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
308 #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
312 #define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
313 #define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
314 #define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
315 #define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
316 #define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
320 #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
326 #define REG_CA_I2S REG(0x11, 0x01) /* read/write */
329 #define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
330 #define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
331 #define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
332 #define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
333 #define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
334 #define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
335 #define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
336 #define REG_CTS_N REG(0x11, 0x0c) /* read/write */
339 #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
343 #define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
346 #define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
352 #define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
356 #define REG_TX3 REG(0x12, 0x9a) /* read/write */
357 #define REG_TX4 REG(0x12, 0x9b) /* read/write */
359 #define REG_TX33 REG(0x12, 0xb8) /* read/write */
378 #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
383 #define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
391 #define REG_CEC_ENAMODS 0xff /* read/write */
411 .addr = priv->cec_addr, in cec_write()
417 ret = i2c_transfer(priv->hdmi->adapter, &msg, 1); in cec_write()
419 dev_err(&priv->hdmi->dev, "Error %d writing to cec:0x%x\n", in cec_write()
429 .addr = priv->cec_addr, in cec_read()
433 .addr = priv->cec_addr, in cec_read()
441 ret = i2c_transfer(priv->hdmi->adapter, msg, ARRAY_SIZE(msg)); in cec_read()
443 dev_err(&priv->hdmi->dev, "Error %d reading from cec:0x%x\n", in cec_read()
491 * Calibration for the internal oscillator: we need to set calibration mode,
496 struct gpio_desc *calib = priv->calib; in tda998x_cec_calibration()
498 mutex_lock(&priv->edid_mutex); in tda998x_cec_calibration()
499 if (priv->hdmi->irq > 0) in tda998x_cec_calibration()
500 disable_irq(priv->hdmi->irq); in tda998x_cec_calibration()
512 if (priv->hdmi->irq > 0) in tda998x_cec_calibration()
513 enable_irq(priv->hdmi->irq); in tda998x_cec_calibration()
514 mutex_unlock(&priv->edid_mutex); in tda998x_cec_calibration()
522 calib = gpiod_get(&priv->hdmi->dev, "nxp,calib", GPIOD_ASIS); in tda998x_cec_hook_init()
524 dev_warn(&priv->hdmi->dev, "failed to get calibration gpio: %ld\n", in tda998x_cec_hook_init()
529 priv->calib = calib; in tda998x_cec_hook_init()
538 gpiod_put(priv->calib); in tda998x_cec_hook_exit()
539 priv->calib = NULL; in tda998x_cec_hook_exit()
562 if (REG2PAGE(reg) != priv->current_page) { in set_page()
563 struct i2c_client *client = priv->hdmi; in set_page()
569 dev_err(&client->dev, "%s %04x err %d\n", __func__, in set_page()
574 priv->current_page = REG2PAGE(reg); in set_page()
582 struct i2c_client *client = priv->hdmi; in reg_read_range()
586 mutex_lock(&priv->mutex); in reg_read_range()
602 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg); in reg_read_range()
604 mutex_unlock(&priv->mutex); in reg_read_range()
613 struct i2c_client *client = priv->hdmi; in reg_write_range()
619 dev_err(&client->dev, "Fixed write buffer too small (%d)\n", in reg_write_range()
627 mutex_lock(&priv->mutex); in reg_write_range()
634 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); in reg_write_range()
636 mutex_unlock(&priv->mutex); in reg_write_range()
654 struct i2c_client *client = priv->hdmi; in reg_write()
658 mutex_lock(&priv->mutex); in reg_write()
665 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); in reg_write()
667 mutex_unlock(&priv->mutex); in reg_write()
673 struct i2c_client *client = priv->hdmi; in reg_write16()
677 mutex_lock(&priv->mutex); in reg_write16()
684 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); in reg_write16()
686 mutex_unlock(&priv->mutex); in reg_write16()
737 /* Write the default value MUX register */ in tda998x_reset()
742 * The TDA998x has a problem when trying to read the EDID close to a
743 * HPD assertion: it needs a delay of 100ms to avoid timing out while
744 * trying to read EDID data.
748 * we need to delay probing modes in tda998x_connector_get_modes() after
749 * we have seen a HPD inactive->active transition. This code implements
757 priv->edid_delay_active = false; in tda998x_edid_delay_done()
758 wake_up(&priv->edid_delay_waitq); in tda998x_edid_delay_done()
759 schedule_work(&priv->detect_work); in tda998x_edid_delay_done()
764 priv->edid_delay_active = true; in tda998x_edid_delay_start()
765 mod_timer(&priv->edid_delay_timer, jiffies + HZ/10); in tda998x_edid_delay_start()
770 return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active); in tda998x_edid_delay_wait()
774 * We need to run the KMS hotplug event helper outside of our threaded
776 * which will want to make use of interrupts.
782 struct drm_device *dev = priv->connector.dev; in tda998x_detect_work()
812 schedule_work(&priv->detect_work); in tda998x_irq_thread()
814 priv->cec_notify); in tda998x_irq_thread()
820 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) { in tda998x_irq_thread()
821 priv->wq_edid_wait = 0; in tda998x_irq_thread()
822 wake_up(&priv->wq_edid); in tda998x_irq_thread()
839 dev_err(&priv->hdmi->dev, in tda998x_write_if()
841 frame->any.type, len); in tda998x_write_if()
866 &priv->connector, mode); in tda998x_write_avi()
868 drm_hdmi_avi_infoframe_quant_range(&frame.avi, &priv->connector, mode, in tda998x_write_avi()
869 priv->rgb_quant_range); in tda998x_write_avi()
880 &priv->connector, in tda998x_write_vsi()
907 s->route = &tda998x_audio_route[route]; in tda998x_derive_routing()
908 s->ena_ap = priv->audio_port_enable[route]; in tda998x_derive_routing()
909 if (s->ena_ap == 0) { in tda998x_derive_routing()
910 dev_err(&priv->hdmi->dev, "no audio configuration found\n"); in tda998x_derive_routing()
911 return -EINVAL; in tda998x_derive_routing()
929 unsigned long ser_clk = priv->tmds_clock * 1000; in tda998x_get_adiv()
932 for (adiv = AUDIO_DIV_SERCLK_32; adiv != AUDIO_DIV_SERCLK_1; adiv--) in tda998x_get_adiv()
936 dev_dbg(&priv->hdmi->dev, in tda998x_get_adiv()
944 * In auto-CTS mode, the TDA998x uses a "measured time stamp" counter to
948 * way to that which is set out in the CTS generation in the HDMI spec.
950 * tmdsclk ----> mts -> /m ---> CTS
952 * sclk -> /k -> /N
961 * When combined with the sink-side equation, and realising that sclk is
973 settings->cts_n = CTS_N_M(3) | CTS_N_K(0); in tda998x_derive_cts_n()
976 settings->cts_n = CTS_N_M(3) | CTS_N_K(1); in tda998x_derive_cts_n()
979 settings->cts_n = CTS_N_M(3) | CTS_N_K(2); in tda998x_derive_cts_n()
982 settings->cts_n = CTS_N_M(3) | CTS_N_K(3); in tda998x_derive_cts_n()
985 settings->cts_n = CTS_N_M(0) | CTS_N_K(0); in tda998x_derive_cts_n()
988 dev_err(&priv->hdmi->dev, "unsupported bclk ratio %ufs\n", in tda998x_derive_cts_n()
990 return -EINVAL; in tda998x_derive_cts_n()
1008 const struct tda998x_audio_settings *settings = &priv->audio; in tda998x_configure_audio()
1012 /* If audio is not configured, there is nothing to do. */ in tda998x_configure_audio()
1013 if (settings->ena_ap == 0) in tda998x_configure_audio()
1016 adiv = tda998x_get_adiv(priv, settings->sample_rate); in tda998x_configure_audio()
1019 reg_write(priv, REG_ENA_AP, settings->ena_ap); in tda998x_configure_audio()
1020 reg_write(priv, REG_ENA_ACLK, settings->route->ena_aclk); in tda998x_configure_audio()
1021 reg_write(priv, REG_MUX_AP, settings->route->mux_ap); in tda998x_configure_audio()
1022 reg_write(priv, REG_I2S_FORMAT, settings->i2s_format); in tda998x_configure_audio()
1023 reg_write(priv, REG_AIP_CLKSEL, settings->route->aip_clksel); in tda998x_configure_audio()
1026 reg_write(priv, REG_CTS_N, settings->cts_n); in tda998x_configure_audio()
1030 * This is the approximate value of N, which happens to be in tda998x_configure_audio()
1031 * the recommended values for non-coherent clocks. in tda998x_configure_audio()
1033 n = 128 * settings->sample_rate / 1000; in tda998x_configure_audio()
1035 /* Write the CTS and N values */ in tda998x_configure_audio()
1048 /* Write the channel status in tda998x_configure_audio()
1049 * The REG_CH_STAT_B-registers skip IEC958 AES2 byte, because in tda998x_configure_audio()
1052 buf[0] = settings->status[0]; in tda998x_configure_audio()
1053 buf[1] = settings->status[1]; in tda998x_configure_audio()
1054 buf[2] = settings->status[3]; in tda998x_configure_audio()
1055 buf[3] = settings->status[4]; in tda998x_configure_audio()
1062 tda998x_write_aif(priv, &settings->cea); in tda998x_configure_audio()
1071 bool spdif = daifmt->fmt == HDMI_SPDIF; in tda998x_audio_hw_params()
1074 .sample_rate = params->sample_rate, in tda998x_audio_hw_params()
1075 .cea = params->cea, in tda998x_audio_hw_params()
1078 memcpy(audio.status, params->iec.status, in tda998x_audio_hw_params()
1079 min(sizeof(audio.status), sizeof(params->iec.status))); in tda998x_audio_hw_params()
1081 switch (daifmt->fmt) { in tda998x_audio_hw_params()
1095 dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt); in tda998x_audio_hw_params()
1096 return -EINVAL; in tda998x_audio_hw_params()
1100 (daifmt->bit_clk_inv || daifmt->frame_clk_inv || in tda998x_audio_hw_params()
1101 daifmt->bit_clk_provider || daifmt->frame_clk_provider)) { in tda998x_audio_hw_params()
1103 daifmt->bit_clk_inv, daifmt->frame_clk_inv, in tda998x_audio_hw_params()
1104 daifmt->bit_clk_provider, in tda998x_audio_hw_params()
1105 daifmt->frame_clk_provider); in tda998x_audio_hw_params()
1106 return -EINVAL; in tda998x_audio_hw_params()
1113 bclk_ratio = spdif ? 64 : params->sample_width * 2; in tda998x_audio_hw_params()
1118 mutex_lock(&priv->audio_mutex); in tda998x_audio_hw_params()
1119 priv->audio = audio; in tda998x_audio_hw_params()
1120 if (priv->supports_infoframes && priv->sink_has_audio) in tda998x_audio_hw_params()
1122 mutex_unlock(&priv->audio_mutex); in tda998x_audio_hw_params()
1131 mutex_lock(&priv->audio_mutex); in tda998x_audio_shutdown()
1134 priv->audio.ena_ap = 0; in tda998x_audio_shutdown()
1136 mutex_unlock(&priv->audio_mutex); in tda998x_audio_shutdown()
1144 mutex_lock(&priv->audio_mutex); in tda998x_audio_mute_stream()
1148 mutex_unlock(&priv->audio_mutex); in tda998x_audio_mute_stream()
1157 mutex_lock(&priv->audio_mutex); in tda998x_audio_get_eld()
1158 memcpy(buf, priv->connector.eld, in tda998x_audio_get_eld()
1159 min(sizeof(priv->connector.eld), len)); in tda998x_audio_get_eld()
1160 mutex_unlock(&priv->audio_mutex); in tda998x_audio_get_eld()
1183 if (priv->audio_port_enable[AUDIO_ROUTE_I2S]) in tda998x_audio_codec_init()
1185 if (priv->audio_port_enable[AUDIO_ROUTE_SPDIF]) in tda998x_audio_codec_init()
1188 priv->audio_pdev = platform_device_register_data( in tda998x_audio_codec_init()
1192 return PTR_ERR_OR_ZERO(priv->audio_pdev); in tda998x_audio_codec_init()
1230 mutex_lock(&priv->edid_mutex); in read_edid_block()
1238 priv->wq_edid_wait = 1; in read_edid_block()
1244 /* wait for block read to complete: */ in read_edid_block()
1245 if (priv->hdmi->irq) { in read_edid_block()
1246 i = wait_event_timeout(priv->wq_edid, in read_edid_block()
1247 !priv->wq_edid_wait, in read_edid_block()
1250 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i); in read_edid_block()
1255 for (i = 100; i > 0; i--) { in read_edid_block()
1266 dev_err(&priv->hdmi->dev, "read edid timeout\n"); in read_edid_block()
1267 ret = -ETIMEDOUT; in read_edid_block()
1273 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n", in read_edid_block()
1281 mutex_unlock(&priv->edid_mutex); in read_edid_block()
1299 if (priv->rev == TDA19988) in tda998x_connector_get_modes()
1304 if (priv->rev == TDA19988) in tda998x_connector_get_modes()
1308 cec_notifier_set_phys_addr(priv->cec_notify, in tda998x_connector_get_modes()
1309 connector->display_info.source_physical_address); in tda998x_connector_get_modes()
1312 dev_warn(&priv->hdmi->dev, "failed to read EDID\n"); in tda998x_connector_get_modes()
1316 mutex_lock(&priv->audio_mutex); in tda998x_connector_get_modes()
1318 priv->sink_has_audio = connector->display_info.has_audio; in tda998x_connector_get_modes()
1319 mutex_unlock(&priv->audio_mutex); in tda998x_connector_get_modes()
1331 return priv->bridge.encoder; in tda998x_connector_best_encoder()
1343 struct drm_connector *connector = &priv->connector; in tda998x_connector_init()
1346 connector->interlace_allowed = 1; in tda998x_connector_init()
1348 if (priv->hdmi->irq) in tda998x_connector_init()
1349 connector->polled = DRM_CONNECTOR_POLL_HPD; in tda998x_connector_init()
1351 connector->polled = DRM_CONNECTOR_POLL_CONNECT | in tda998x_connector_init()
1360 drm_connector_attach_encoder(&priv->connector, in tda998x_connector_init()
1361 priv->bridge.encoder); in tda998x_connector_init()
1375 DRM_ERROR("Fix bridge driver to make connector optional!"); in tda998x_bridge_attach()
1376 return -EINVAL; in tda998x_bridge_attach()
1379 return tda998x_connector_init(priv, bridge->dev); in tda998x_bridge_attach()
1386 drm_connector_cleanup(&priv->connector); in tda998x_bridge_detach()
1393 /* TDA19988 dotclock can go up to 165MHz */ in tda998x_bridge_mode_valid()
1396 if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000)) in tda998x_bridge_mode_valid()
1398 if (mode->htotal >= BIT(13)) in tda998x_bridge_mode_valid()
1400 if (mode->vtotal >= BIT(11)) in tda998x_bridge_mode_valid()
1409 if (!priv->is_on) { in tda998x_bridge_enable()
1415 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0); in tda998x_bridge_enable()
1416 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1); in tda998x_bridge_enable()
1417 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2); in tda998x_bridge_enable()
1419 priv->is_on = true; in tda998x_bridge_enable()
1427 if (priv->is_on) { in tda998x_bridge_disable()
1433 priv->is_on = false; in tda998x_bridge_disable()
1454 * full-range RGB. If the monitor supports full-range, then use in tda998x_bridge_mode_set()
1455 * it, otherwise reduce to limited-range. in tda998x_bridge_mode_set()
1457 priv->rgb_quant_range = in tda998x_bridge_mode_set()
1458 priv->connector.display_info.rgb_quant_range_selectable ? in tda998x_bridge_mode_set()
1463 * Internally TDA998x is using ITU-R BT.656 style sync but in tda998x_bridge_mode_set()
1465 * relative to ITU to sync to the input frame and for output in tda998x_bridge_mode_set()
1470 * Now there is some issues to take care of: in tda998x_bridge_mode_set()
1471 * - HDMI data islands require sync-before-active in tda998x_bridge_mode_set()
1472 * - TDA998x register values must be > 0 to be enabled in tda998x_bridge_mode_set()
1473 * - REFLINE needs an additional offset of +1 in tda998x_bridge_mode_set()
1474 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB in tda998x_bridge_mode_set()
1476 * So we add +1 to all horizontal and vertical register values, in tda998x_bridge_mode_set()
1479 n_pix = mode->htotal; in tda998x_bridge_mode_set()
1480 n_line = mode->vtotal; in tda998x_bridge_mode_set()
1482 hs_pix_e = mode->hsync_end - mode->hdisplay; in tda998x_bridge_mode_set()
1483 hs_pix_s = mode->hsync_start - mode->hdisplay; in tda998x_bridge_mode_set()
1484 de_pix_e = mode->htotal; in tda998x_bridge_mode_set()
1485 de_pix_s = mode->htotal - mode->hdisplay; in tda998x_bridge_mode_set()
1490 * those to adjust the position of the rising VS edge by adding in tda998x_bridge_mode_set()
1491 * HSKEW to ref_pix. in tda998x_bridge_mode_set()
1493 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW) in tda998x_bridge_mode_set()
1494 ref_pix += adjusted_mode->hskew; in tda998x_bridge_mode_set()
1496 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) { in tda998x_bridge_mode_set()
1497 ref_line = 1 + mode->vsync_start - mode->vdisplay; in tda998x_bridge_mode_set()
1498 vwin1_line_s = mode->vtotal - mode->vdisplay - 1; in tda998x_bridge_mode_set()
1499 vwin1_line_e = vwin1_line_s + mode->vdisplay; in tda998x_bridge_mode_set()
1501 vs1_line_s = mode->vsync_start - mode->vdisplay; in tda998x_bridge_mode_set()
1503 mode->vsync_end - mode->vsync_start; in tda998x_bridge_mode_set()
1508 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2; in tda998x_bridge_mode_set()
1509 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2; in tda998x_bridge_mode_set()
1510 vwin1_line_e = vwin1_line_s + mode->vdisplay/2; in tda998x_bridge_mode_set()
1512 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2; in tda998x_bridge_mode_set()
1514 (mode->vsync_end - mode->vsync_start)/2; in tda998x_bridge_mode_set()
1515 vwin2_line_s = vwin1_line_s + mode->vtotal/2; in tda998x_bridge_mode_set()
1516 vwin2_line_e = vwin2_line_s + mode->vdisplay/2; in tda998x_bridge_mode_set()
1517 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2; in tda998x_bridge_mode_set()
1518 vs2_line_s = vs1_line_s + mode->vtotal/2 ; in tda998x_bridge_mode_set()
1520 (mode->vsync_end - mode->vsync_start)/2; in tda998x_bridge_mode_set()
1524 * Select pixel repeat depending on the double-clock flag in tda998x_bridge_mode_set()
1525 * (which means we have to repeat each pixel once.) in tda998x_bridge_mode_set()
1527 rep = mode->flags & DRM_MODE_FLAG_DBLCLK ? 1 : 0; in tda998x_bridge_mode_set()
1532 tmds_clock = mode->clock * (1 + rep); in tda998x_bridge_mode_set()
1535 * The divisor is power-of-2. The TDA9983B datasheet gives in tda998x_bridge_mode_set()
1537 * 0 - 800 to 1500 Msample/s in tda998x_bridge_mode_set()
1538 * 1 - 400 to 800 Msample/s in tda998x_bridge_mode_set()
1539 * 2 - 200 to 400 Msample/s in tda998x_bridge_mode_set()
1540 * 3 - as 2 above in tda998x_bridge_mode_set()
1546 mutex_lock(&priv->audio_mutex); in tda998x_bridge_mode_set()
1548 priv->tmds_clock = tmds_clock; in tda998x_bridge_mode_set()
1558 /* no pre-filter or interpolator: */ in tda998x_bridge_mode_set()
1577 /* set color matrix according to output rgb quant range */ in tda998x_bridge_mode_set()
1578 if (priv->rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) { in tda998x_bridge_mode_set()
1606 * TDA19988 requires high-active sync at input stage, in tda998x_bridge_mode_set()
1607 * so invert low-active sync provided by master encoder here in tda998x_bridge_mode_set()
1609 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in tda998x_bridge_mode_set()
1611 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in tda998x_bridge_mode_set()
1637 if (priv->rev == TDA19988) { in tda998x_bridge_mode_set()
1643 * Always generate sync polarity relative to input sync and in tda998x_bridge_mode_set()
1647 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in tda998x_bridge_mode_set()
1649 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in tda998x_bridge_mode_set()
1656 /* CEA-861B section 6 says that: in tda998x_bridge_mode_set()
1657 * CEA version 1 (CEA-861) has no support for infoframes. in tda998x_bridge_mode_set()
1658 * CEA version 2 (CEA-861A) supports version 1 AVI infoframes, in tda998x_bridge_mode_set()
1660 * CEA version 3 (CEA-861B) supports version 1 and 2 AVI infoframes, in tda998x_bridge_mode_set()
1665 * CEA-861 source.) in tda998x_bridge_mode_set()
1667 priv->supports_infoframes = priv->connector.display_info.cea_rev >= 3; in tda998x_bridge_mode_set()
1669 if (priv->supports_infoframes) { in tda998x_bridge_mode_set()
1670 /* We need to turn HDMI HDCP stuff on to get audio through */ in tda998x_bridge_mode_set()
1679 if (priv->sink_has_audio) in tda998x_bridge_mode_set()
1683 mutex_unlock(&priv->audio_mutex); in tda998x_bridge_mode_set()
1704 port_data = of_get_property(np, "audio-ports", &size); in tda998x_get_audio_ports()
1709 if (size > 2 * ARRAY_SIZE(priv->audio_port_enable) || size % 2 != 0) { in tda998x_get_audio_ports()
1710 dev_err(&priv->hdmi->dev, in tda998x_get_audio_ports()
1711 "Bad number of elements in audio-ports dt-property\n"); in tda998x_get_audio_ports()
1712 return -EINVAL; in tda998x_get_audio_ports()
1730 dev_err(&priv->hdmi->dev, in tda998x_get_audio_ports()
1732 return -EINVAL; in tda998x_get_audio_ports()
1736 dev_err(&priv->hdmi->dev, "invalid zero port config\n"); in tda998x_get_audio_ports()
1740 if (priv->audio_port_enable[route]) { in tda998x_get_audio_ports()
1741 dev_err(&priv->hdmi->dev, in tda998x_get_audio_ports()
1744 return -EINVAL; in tda998x_get_audio_ports()
1747 priv->audio_port_enable[route] = ena_ap; in tda998x_get_audio_ports()
1756 drm_bridge_remove(&priv->bridge); in tda998x_destroy()
1762 if (priv->audio_pdev) in tda998x_destroy()
1763 platform_device_unregister(priv->audio_pdev); in tda998x_destroy()
1765 if (priv->hdmi->irq) in tda998x_destroy()
1766 free_irq(priv->hdmi->irq, priv); in tda998x_destroy()
1768 timer_delete_sync(&priv->edid_delay_timer); in tda998x_destroy()
1769 cancel_work_sync(&priv->detect_work); in tda998x_destroy()
1771 i2c_unregister_device(priv->cec); in tda998x_destroy()
1773 cec_notifier_conn_unregister(priv->cec_notify); in tda998x_destroy()
1779 struct device_node *np = client->dev.of_node; in tda998x_create()
1791 mutex_init(&priv->mutex); /* protect the page access */ in tda998x_create()
1792 mutex_init(&priv->audio_mutex); /* protect access from audio thread */ in tda998x_create()
1793 mutex_init(&priv->edid_mutex); in tda998x_create()
1794 INIT_LIST_HEAD(&priv->bridge.list); in tda998x_create()
1795 init_waitqueue_head(&priv->edid_delay_waitq); in tda998x_create()
1796 timer_setup(&priv->edid_delay_timer, tda998x_edid_delay_done, 0); in tda998x_create()
1797 INIT_WORK(&priv->detect_work, tda998x_detect_work); in tda998x_create()
1799 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3); in tda998x_create()
1800 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1); in tda998x_create()
1801 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5); in tda998x_create()
1803 /* CEC I2C address bound to TDA998x I2C addr by configuration pins */ in tda998x_create()
1804 priv->cec_addr = 0x34 + (client->addr & 0x03); in tda998x_create()
1805 priv->current_page = 0xff; in tda998x_create()
1806 priv->hdmi = client; in tda998x_create()
1817 dev_err(dev, "failed to read version: %d\n", rev_lo); in tda998x_create()
1823 dev_err(dev, "failed to read version: %d\n", rev_hi); in tda998x_create()
1827 priv->rev = rev_lo | rev_hi << 8; in tda998x_create()
1830 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */ in tda998x_create()
1832 switch (priv->rev) { in tda998x_create()
1846 dev_err(dev, "found unsupported device: %04x\n", priv->rev); in tda998x_create()
1847 return -ENXIO; in tda998x_create()
1856 /* if necessary, disable multi-master: */ in tda998x_create()
1857 if (priv->rev == TDA19989) in tda998x_create()
1873 if (client->irq) { in tda998x_create()
1877 init_waitqueue_head(&priv->wq_edid); in tda998x_create()
1880 irqd_get_trigger_type(irq_get_irq_data(client->irq)); in tda998x_create()
1882 priv->cec_glue.irq_flags = irq_flags; in tda998x_create()
1885 ret = request_threaded_irq(client->irq, NULL, in tda998x_create()
1889 dev_err(dev, "failed to request IRQ#%u: %d\n", in tda998x_create()
1890 client->irq, ret); in tda998x_create()
1898 priv->cec_notify = cec_notifier_conn_register(dev, NULL, NULL); in tda998x_create()
1899 if (!priv->cec_notify) { in tda998x_create()
1900 ret = -ENOMEM; in tda998x_create()
1904 priv->cec_glue.parent = dev; in tda998x_create()
1905 priv->cec_glue.data = priv; in tda998x_create()
1906 priv->cec_glue.init = tda998x_cec_hook_init; in tda998x_create()
1907 priv->cec_glue.exit = tda998x_cec_hook_exit; in tda998x_create()
1908 priv->cec_glue.open = tda998x_cec_hook_open; in tda998x_create()
1909 priv->cec_glue.release = tda998x_cec_hook_release; in tda998x_create()
1916 * to the TDA998x address pins. Hence, it always has the same in tda998x_create()
1921 cec_info.addr = priv->cec_addr; in tda998x_create()
1922 cec_info.platform_data = &priv->cec_glue; in tda998x_create()
1923 cec_info.irq = client->irq; in tda998x_create()
1925 priv->cec = i2c_new_client_device(client->adapter, &cec_info); in tda998x_create()
1926 if (IS_ERR(priv->cec)) { in tda998x_create()
1927 ret = PTR_ERR(priv->cec); in tda998x_create()
1936 ret = of_property_read_u32(np, "video-ports", &video); in tda998x_create()
1938 priv->vip_cntrl_0 = video >> 16; in tda998x_create()
1939 priv->vip_cntrl_1 = video >> 8; in tda998x_create()
1940 priv->vip_cntrl_2 = video; in tda998x_create()
1947 if (priv->audio_port_enable[AUDIO_ROUTE_I2S] || in tda998x_create()
1948 priv->audio_port_enable[AUDIO_ROUTE_SPDIF]) in tda998x_create()
1949 tda998x_audio_codec_init(priv, &client->dev); in tda998x_create()
1953 priv->bridge.of_node = dev->of_node; in tda998x_create()
1956 drm_bridge_add(&priv->bridge); in tda998x_create()
1974 if (dev->of_node) in tda998x_encoder_init()
1975 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); in tda998x_encoder_init()
1977 /* If no CRTCs were found, fall back to our old behaviour */ in tda998x_encoder_init()
1979 dev_warn(dev, "Falling back to first CRTC\n"); in tda998x_encoder_init()
1983 priv->encoder.possible_crtcs = crtcs; in tda998x_encoder_init()
1985 ret = drm_simple_encoder_init(drm, &priv->encoder, in tda998x_encoder_init()
1990 ret = drm_bridge_attach(&priv->encoder, &priv->bridge, NULL, 0); in tda998x_encoder_init()
1997 drm_encoder_cleanup(&priv->encoder); in tda998x_encoder_init()
2014 drm_encoder_cleanup(&priv->encoder); in tda998x_unbind()
2027 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { in tda998x_probe()
2028 dev_warn(&client->dev, "adapter does not support I2C\n"); in tda998x_probe()
2029 return -EIO; in tda998x_probe()
2032 ret = tda998x_create(&client->dev); in tda998x_probe()
2036 ret = component_add(&client->dev, &tda998x_ops); in tda998x_probe()
2038 tda998x_destroy(&client->dev); in tda998x_probe()
2044 component_del(&client->dev, &tda998x_ops); in tda998x_remove()
2045 tda998x_destroy(&client->dev); in tda998x_remove()