1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/media-bus-format.h>
36 /* DSI D-PHY Layer Registers */
37 #define D0W_DPHYCONTTX  0x0004  /* Data Lane 0 DPHY Tx Control */
38 #define CLW_DPHYCONTRX  0x0020  /* Clock Lane DPHY Rx Control */
39 #define D0W_DPHYCONTRX  0x0024  /* Data Lane 0 DPHY Rx Control */
40 #define D1W_DPHYCONTRX  0x0028  /* Data Lane 1 DPHY Rx Control */
41 #define D2W_DPHYCONTRX  0x002C  /* Data Lane 2 DPHY Rx Control */
42 #define D3W_DPHYCONTRX  0x0030  /* Data Lane 3 DPHY Rx Control */
44 #define CLW_CNTRL       0x0040  /* Clock Lane Control */
45 #define D0W_CNTRL       0x0044  /* Data Lane 0 Control */
46 #define D1W_CNTRL       0x0048  /* Data Lane 1 Control */
47 #define D2W_CNTRL       0x004C  /* Data Lane 2 Control */
48 #define D3W_CNTRL       0x0050  /* Data Lane 3 Control */
52 #define PPI_STARTPPI    0x0104  /* START control bit of PPI-TX function. */
58 #define PPI_LANEENABLE  0x0134  /* Enables each lane at the PPI layer. */
62 #define PPI_CLS_ATMR    0x0140  /* Delay for Clock Lane in LPRX  */
63 #define PPI_D0S_ATMR    0x0144  /* Delay for Data Lane 0 in LPRX */
64 #define PPI_D1S_ATMR    0x0148  /* Delay for Data Lane 1 in LPRX */
65 #define PPI_D2S_ATMR    0x014C  /* Delay for Data Lane 2 in LPRX */
66 #define PPI_D3S_ATMR    0x0150  /* Delay for Data Lane 3 in LPRX */
68 #define PPI_D0S_CLRSIPOCOUNT    0x0164  /* For lane 0 */
69 #define PPI_D1S_CLRSIPOCOUNT    0x0168  /* For lane 1 */
70 #define PPI_D2S_CLRSIPOCOUNT    0x016C  /* For lane 2 */
71 #define PPI_D3S_CLRSIPOCOUNT    0x0170  /* For lane 3 */
93 #define DSI_STARTDSI    0x0204  /* START control bit of DSI-TX function */
97 #define DSI_LANEENABLE  0x0210  /* Enables each lane at the Protocol layer. */
98 #define DSI_LANESTATUS0 0x0214  /* Displays lane is in HS RX mode. */
99 #define DSI_LANESTATUS1 0x0218  /* Displays lane is in ULPS or STOP state */
121 #define LV_MX0407        0x0484  /* Bit 4 to 7 */
127 #define LV_MX(b0, b1, b2, b3)	(FLD_VAL(b0, 4, 0) | FLD_VAL(b1, 12, 8) | \
166 #define LV_PHY0_ND(v)           FLD_VAL(v, 4, 0) /* Frequency range select */
173 #define SYS_RST_I2CS	BIT(0) /* Reset I2C-Slave controller */
174 #define SYS_RST_I2CM	BIT(1) /* Reset I2C-Master controller */
177 #define SYS_RST_DSIRX	BIT(4) /* Reset DSI-RX and App controller */
194 #define LPX_PERIOD		4
238 #define TC358775_LVCFG_PCLKDIV__SHIFT	4
279 	u8			lvds_link; /* single-link or dual-link */
293 	struct device *dev = &tc->dsi->dev;  in tc_bridge_pre_enable()
296 	ret = regulator_enable(tc->vddio);  in tc_bridge_pre_enable()
301 	ret = regulator_enable(tc->vdd);  in tc_bridge_pre_enable()
306 	gpiod_set_value(tc->stby_gpio, 0);  in tc_bridge_pre_enable()
309 	gpiod_set_value(tc->reset_gpio, 0);  in tc_bridge_pre_enable()
316 	struct device *dev = &tc->dsi->dev;  in tc_bridge_post_disable()
319 	gpiod_set_value(tc->reset_gpio, 1);  in tc_bridge_post_disable()
322 	gpiod_set_value(tc->stby_gpio, 1);  in tc_bridge_post_disable()
325 	ret = regulator_disable(tc->vdd);  in tc_bridge_post_disable()
330 	ret = regulator_disable(tc->vddio);  in tc_bridge_post_disable()
354 	dev_err(&i2c->dev, "Error %d reading from subaddress 0x%x\n",  in d2l_read()
368 		dev_err(&i2c->dev, "Error %d writing to subaddress 0x%x\n",  in d2l_write()
375 	struct drm_device *dev = encoder->dev;  in get_connector()
378 	list_for_each_entry(connector, &dev->mode_config.connector_list, head)  in get_connector()
379 		if (connector->encoder == encoder)  in get_connector()
393 	struct drm_connector *connector = get_connector(bridge->encoder);  in tc_bridge_enable()
395 	mode = &bridge->encoder->crtc->state->adjusted_mode;  in tc_bridge_enable()
397 	hback_porch = mode->htotal - mode->hsync_end;  in tc_bridge_enable()
398 	hsync_len  = mode->hsync_end - mode->hsync_start;  in tc_bridge_enable()
399 	vback_porch = mode->vtotal - mode->vsync_end;  in tc_bridge_enable()
400 	vsync_len  = mode->vsync_end - mode->vsync_start;  in tc_bridge_enable()
405 	hfront_porch = mode->hsync_start - mode->hdisplay;  in tc_bridge_enable()
406 	hactive = mode->hdisplay;  in tc_bridge_enable()
407 	vfront_porch = mode->vsync_start - mode->vdisplay;  in tc_bridge_enable()
408 	vactive = mode->vdisplay;  in tc_bridge_enable()
413 	d2l_read(tc->i2c, IDREG, &val);  in tc_bridge_enable()
415 	dev_info(tc->dev, "DSI2LVDS Chip ID.%02x Revision ID. %02x **\n",  in tc_bridge_enable()
418 	d2l_write(tc->i2c, SYSRST, SYS_RST_REG | SYS_RST_DSIRX | SYS_RST_BM |  in tc_bridge_enable()
422 	d2l_write(tc->i2c, PPI_TX_RX_TA, TTA_GET | TTA_SURE);  in tc_bridge_enable()
423 	d2l_write(tc->i2c, PPI_LPTXTIMECNT, LPX_PERIOD);  in tc_bridge_enable()
424 	d2l_write(tc->i2c, PPI_D0S_CLRSIPOCOUNT, 3);  in tc_bridge_enable()
425 	d2l_write(tc->i2c, PPI_D1S_CLRSIPOCOUNT, 3);  in tc_bridge_enable()
426 	d2l_write(tc->i2c, PPI_D2S_CLRSIPOCOUNT, 3);  in tc_bridge_enable()
427 	d2l_write(tc->i2c, PPI_D3S_CLRSIPOCOUNT, 3);  in tc_bridge_enable()
429 	val = ((L0EN << tc->num_dsi_lanes) - L0EN) | DSI_CLEN_BIT;  in tc_bridge_enable()
430 	d2l_write(tc->i2c, PPI_LANEENABLE, val);  in tc_bridge_enable()
431 	d2l_write(tc->i2c, DSI_LANEENABLE, val);  in tc_bridge_enable()
433 	d2l_write(tc->i2c, PPI_STARTPPI, PPI_START_FUNCTION);  in tc_bridge_enable()
434 	d2l_write(tc->i2c, DSI_STARTDSI, DSI_RX_START);  in tc_bridge_enable()
437 	if (tc->type == TC358765)  in tc_bridge_enable()
442 	if (tc->bpc == 8)  in tc_bridge_enable()
447 	dsiclk = mode->crtc_clock * 3 * tc->bpc / tc->num_dsi_lanes / 1000;  in tc_bridge_enable()
448 	clkdiv = dsiclk / (tc->lvds_link == DUAL_LINK ? DIVIDE_BY_6 : DIVIDE_BY_3);  in tc_bridge_enable()
449 	byteclk = dsiclk / 4;  in tc_bridge_enable()
450 	t1 = hactive * (tc->bpc * 3 / 8) / tc->num_dsi_lanes;  in tc_bridge_enable()
452 	t3 = ((t2 * byteclk) / 100) - (hactive * (tc->bpc * 3 / 8) /  in tc_bridge_enable()
453 		tc->num_dsi_lanes);  in tc_bridge_enable()
455 	vsdelay = (clkdiv * (t1 + t3) / byteclk) - hback_porch - hsync_len - hactive;  in tc_bridge_enable()
458 	d2l_write(tc->i2c, VPCTRL, val);  in tc_bridge_enable()
460 	d2l_write(tc->i2c, HTIM1, htime1);  in tc_bridge_enable()
461 	d2l_write(tc->i2c, VTIM1, vtime1);  in tc_bridge_enable()
462 	d2l_write(tc->i2c, HTIM2, htime2);  in tc_bridge_enable()
463 	d2l_write(tc->i2c, VTIM2, vtime2);  in tc_bridge_enable()
465 	d2l_write(tc->i2c, VFUEN, VFUEN_EN);  in tc_bridge_enable()
466 	d2l_write(tc->i2c, SYSRST, SYS_RST_LCD);  in tc_bridge_enable()
467 	d2l_write(tc->i2c, LVPHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_ND(6));  in tc_bridge_enable()
469 	dev_dbg(tc->dev, "bus_formats %04x bpc %d\n",  in tc_bridge_enable()
470 		connector->display_info.bus_formats[0],  in tc_bridge_enable()
471 		tc->bpc);  in tc_bridge_enable()
472 	if (connector->display_info.bus_formats[0] ==  in tc_bridge_enable()
474 		/* VESA-24 */  in tc_bridge_enable()
475 		d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3));  in tc_bridge_enable()
476 		d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0));  in tc_bridge_enable()
477 		d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_G6, LVI_G7));  in tc_bridge_enable()
478 		d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0));  in tc_bridge_enable()
479 		d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1, LVI_B2));  in tc_bridge_enable()
480 		d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0));  in tc_bridge_enable()
481 		d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R6));  in tc_bridge_enable()
483 		/* JEIDA-18 and JEIDA-24 */  in tc_bridge_enable()
484 		d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R2, LVI_R3, LVI_R4, LVI_R5));  in tc_bridge_enable()
485 		d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R6, LVI_R1, LVI_R7, LVI_G2));  in tc_bridge_enable()
486 		d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G3, LVI_G4, LVI_G0, LVI_G1));  in tc_bridge_enable()
487 		d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G5, LVI_G6, LVI_G7, LVI_B2));  in tc_bridge_enable()
488 		d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B0, LVI_B1, LVI_B3, LVI_B4));  in tc_bridge_enable()
489 		d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B5, LVI_B6, LVI_B7, LVI_L0));  in tc_bridge_enable()
490 		d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R0));  in tc_bridge_enable()
493 	d2l_write(tc->i2c, VFUEN, VFUEN_EN);  in tc_bridge_enable()
496 	if (tc->lvds_link == DUAL_LINK) {  in tc_bridge_enable()
502 	d2l_write(tc->i2c, LVCFG, val);  in tc_bridge_enable()
513 	 * Maximum pixel clock speed 135MHz for single-link  in tc_mode_valid()
514 	 * 270MHz for dual-link  in tc_mode_valid()
516 	if ((mode->clock > 135000 && tc->lvds_link == SINGLE_LINK) ||  in tc_mode_valid()
517 	    (mode->clock > 270000 && tc->lvds_link == DUAL_LINK))  in tc_mode_valid()
520 	switch (info->bus_formats[0]) {  in tc_mode_valid()
524 		tc->bpc = 8;  in tc_mode_valid()
528 		tc->bpc = 6;  in tc_mode_valid()
531 		dev_warn(tc->dev,  in tc_mode_valid()
533 			 info->bus_formats[0]);  in tc_mode_valid()
544 	int dsi_lanes = -1;  in tc358775_parse_dt()
546 	endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node,  in tc358775_parse_dt()
547 						 TC358775_DSI_IN, -1);  in tc358775_parse_dt()
548 	dsi_lanes = drm_of_get_data_lanes_count(endpoint, 1, 4);  in tc358775_parse_dt()
551 	if (dsi_lanes == -EINVAL || dsi_lanes == -ENODEV) {  in tc358775_parse_dt()
553 		dsi_lanes = drm_of_get_data_lanes_count(remote, 1, 4);  in tc358775_parse_dt()
556 			dev_warn(tc->dev, "no dsi-lanes for the bridge, using host lanes\n");  in tc358775_parse_dt()
564 	tc->num_dsi_lanes = dsi_lanes;  in tc358775_parse_dt()
566 	tc->host_node = of_graph_get_remote_node(np, 0, 0);  in tc358775_parse_dt()
567 	if (!tc->host_node)  in tc358775_parse_dt()
568 		return -ENODEV;  in tc358775_parse_dt()
570 	of_node_put(tc->host_node);  in tc358775_parse_dt()
572 	tc->lvds_link = SINGLE_LINK;  in tc358775_parse_dt()
573 	endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node,  in tc358775_parse_dt()
574 						 TC358775_LVDS_OUT1, -1);  in tc358775_parse_dt()
581 				tc->lvds_link = DUAL_LINK;  in tc358775_parse_dt()
586 	dev_dbg(tc->dev, "no.of dsi lanes: %d\n", tc->num_dsi_lanes);  in tc358775_parse_dt()
587 	dev_dbg(tc->dev, "operating in %d-link mode\n",	tc->lvds_link);  in tc358775_parse_dt()
597 	/* Attach the panel-bridge to the dsi bridge */  in tc_bridge_attach()
598 	return drm_bridge_attach(bridge->encoder, tc->panel_bridge,  in tc_bridge_attach()
599 				 &tc->bridge, flags);  in tc_bridge_attach()
612 	struct device *dev = &tc->i2c->dev;  in tc_attach_host()
621 	host = of_find_mipi_dsi_host_by_node(tc->host_node);  in tc_attach_host()
623 		return dev_err_probe(dev, -EPROBE_DEFER, "failed to find dsi host\n");  in tc_attach_host()
631 	tc->dsi = dsi;  in tc_attach_host()
633 	dsi->lanes = tc->num_dsi_lanes;  in tc_attach_host()
634 	dsi->format = MIPI_DSI_FMT_RGB888;  in tc_attach_host()
635 	dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |  in tc_attach_host()
645 	if (tc->type == TC358765)  in tc_attach_host()
646 		dsi->hs_rate = 800000000;  in tc_attach_host()
648 		dsi->hs_rate = 1000000000;  in tc_attach_host()
649 	dsi->lp_rate = 10000000;  in tc_attach_host()
662 	struct device *dev = &client->dev;  in tc_probe()
668 		return -ENOMEM;  in tc_probe()
670 	tc->dev = dev;  in tc_probe()
671 	tc->i2c = client;  in tc_probe()
672 	tc->type = (enum tc3587x5_type)(unsigned long)of_device_get_match_data(dev);  in tc_probe()
674 	tc->panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node,  in tc_probe()
676 	if (IS_ERR(tc->panel_bridge))  in tc_probe()
677 		return PTR_ERR(tc->panel_bridge);  in tc_probe()
679 	ret = tc358775_parse_dt(dev->of_node, tc);  in tc_probe()
683 	tc->vddio = devm_regulator_get(dev, "vddio-supply");  in tc_probe()
684 	if (IS_ERR(tc->vddio)) {  in tc_probe()
685 		ret = PTR_ERR(tc->vddio);  in tc_probe()
686 		dev_err(dev, "vddio-supply not found\n");  in tc_probe()
690 	tc->vdd = devm_regulator_get(dev, "vdd-supply");  in tc_probe()
691 	if (IS_ERR(tc->vdd)) {  in tc_probe()
692 		ret = PTR_ERR(tc->vdd);  in tc_probe()
693 		dev_err(dev, "vdd-supply not found\n");  in tc_probe()
697 	tc->stby_gpio = devm_gpiod_get_optional(dev, "stby", GPIOD_OUT_HIGH);  in tc_probe()
698 	if (IS_ERR(tc->stby_gpio))  in tc_probe()
699 		return PTR_ERR(tc->stby_gpio);  in tc_probe()
701 	tc->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);  in tc_probe()
702 	if (IS_ERR(tc->reset_gpio)) {  in tc_probe()
703 		ret = PTR_ERR(tc->reset_gpio);  in tc_probe()
704 		dev_err(dev, "cannot get reset-gpios %d\n", ret);  in tc_probe()
708 	tc->bridge.funcs = &tc_bridge_funcs;  in tc_probe()
709 	tc->bridge.of_node = dev->of_node;  in tc_probe()
710 	tc->bridge.pre_enable_prev_first = true;  in tc_probe()
711 	drm_bridge_add(&tc->bridge);  in tc_probe()
722 	drm_bridge_remove(&tc->bridge);  in tc_probe()
730 	drm_bridge_remove(&tc->bridge);  in tc_remove()