Lines Matching +full:vddc +full:- +full:supply
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com
13 #include <linux/media-bus-format.h>
29 /* Global (16-bit addressable) */
46 /* Debug (16-bit addressable) */
52 /* TX PHY (32-bit addressable) */
64 /* TX PPI (32-bit addressable) */
80 /* TX CTRL (32-bit addressable) */
101 /* DSITX CTRL (16-bit addressable) */
132 "vddc", "vddmipi", "vddio"
181 int ret = priv->error;
183 priv->error = 0;
193 if (priv->error)
196 /* 16-bit register? */
200 priv->error = regmap_bulk_write(priv->regmap, reg, &tmpval, count);
207 if (priv->error)
210 /* 16-bit register? */
216 priv->error = regmap_bulk_read(priv->regmap, reg, val, count);
226 if (priv->error)
241 if (priv->error)
245 priv->error = regmap_read_poll_timeout(priv->regmap, TC358768_DSICMD_TX, val,
264 if (priv->enabled)
267 ret = clk_prepare_enable(priv->refclk);
269 dev_err(priv->dev, "error enabling refclk (%d)\n", ret);
271 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
273 dev_err(priv->dev, "error enabling regulators (%d)\n", ret);
275 if (priv->reset_gpio)
282 gpiod_set_value_cansleep(priv->reset_gpio, 0);
287 priv->enabled = true;
294 if (!priv->enabled)
301 gpiod_set_value_cansleep(priv->reset_gpio, 1);
303 ret = regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
304 priv->supplies);
306 dev_err(priv->dev, "error disabling regulators (%d)\n", ret);
308 clk_disable_unprepare(priv->refclk);
310 priv->enabled = false;
315 return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->dsi_bpp);
320 return (u32)div_u64((u64)pclk * priv->dsi_bpp, priv->dsi_lanes);
338 target_pll = tc358768_pclk_to_pll(priv, mode->clock * 1000);
347 return -EINVAL;
349 frs = i - 1;
350 max_pll = frs_limits[i - 1];
353 refclk = clk_get_rate(priv->refclk);
376 diff = max(pll, target_pll) - min(pll, target_pll);
391 dev_err(priv->dev, "could not find suitable PLL setup\n");
392 return -EINVAL;
399 priv->fbd = best_fbd;
400 priv->prd = best_prd;
401 priv->frs = frs;
402 priv->dsiclk = best_pll / 2;
403 priv->pclk = mode->clock * 1000;
417 if (dev->lanes > 4) {
418 dev_err(priv->dev, "unsupported number of data lanes(%u)\n",
419 dev->lanes);
420 return -EINVAL;
427 if (!(dev->mode_flags & MIPI_DSI_MODE_VIDEO)) {
428 dev_err(priv->dev, "Only MIPI_DSI_MODE_VIDEO is supported\n");
429 return -ENOTSUPP;
436 if (dev->format != MIPI_DSI_FMT_RGB888) {
437 dev_warn(priv->dev, "Only MIPI_DSI_FMT_RGB888 tested!\n");
438 return -ENOTSUPP;
441 ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, &panel,
453 priv->output.dev = dev;
454 priv->output.bridge = bridge;
455 priv->output.panel = panel;
457 priv->dsi_lanes = dev->lanes;
458 priv->dsi_bpp = mipi_dsi_pixel_format_to_bpp(dev->format);
461 ret = -EINVAL;
462 ep = of_graph_get_endpoint_by_regs(host->dev->of_node, 0, 0);
464 ret = of_property_read_u32(ep, "bus-width", &priv->pd_lines);
466 ret = of_property_read_u32(ep, "data-lines", &priv->pd_lines);
472 priv->pd_lines = priv->dsi_bpp;
474 drm_bridge_add(&priv->bridge);
484 drm_bridge_remove(&priv->bridge);
485 if (priv->output.panel)
486 drm_panel_bridge_remove(priv->output.bridge);
498 if (!priv->enabled) {
499 dev_err(priv->dev, "Bridge is not enabled\n");
500 return -ENODEV;
503 if (msg->rx_len) {
504 dev_warn(priv->dev, "MIPI rx is not supported\n");
505 return -ENOTSUPP;
508 if (msg->tx_len > 8) {
509 dev_warn(priv->dev, "Maximum 8 byte MIPI tx is supported\n");
510 return -ENOTSUPP;
517 if (mipi_dsi_packet_format_is_short(msg->type)) {
543 dev_warn(priv->dev, "Software disable failed: %d\n", ret);
562 if (!drm_core_check_feature(bridge->dev, DRIVER_ATOMIC)) {
563 dev_err(priv->dev, "needs atomic updates support\n");
564 return -ENOTSUPP;
567 return drm_bridge_attach(encoder, priv->output.bridge, bridge,
604 dev_warn(priv->dev, "Software disable failed: %d\n", ret);
623 dev_err(priv->dev, "PLL calculation failed: %d\n", ret);
627 fbd = priv->fbd;
628 prd = priv->prd;
629 frs = priv->frs;
631 dev_dbg(priv->dev, "PLL: refclk %lu, fbd %u, prd %u, frs %u\n",
632 clk_get_rate(priv->refclk), fbd, prd, frs);
633 dev_dbg(priv->dev, "PLL: pll_clk: %u, DSIClk %u, HSByteClk %u\n",
634 priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4);
635 dev_dbg(priv->dev, "PLL: pclk %u (panel: %u)\n",
636 tc358768_pll_to_pclk(priv, priv->dsiclk * 2),
637 mode->clock * 1000);
640 tc358768_write(priv, TC358768_PLLCTL0, ((prd - 1) << 12) | (fbd - 1));
674 u64 m = (u64)val * priv->dsiclk / 4 * priv->dsi_lanes;
675 u64 n = priv->pclk;
677 return (u32)div_u64(m + n - 1, n);
683 u64 n = priv->dsiclk / 4 * priv->dsi_lanes;
692 struct mipi_dsi_device *dsi_dev = priv->output.dev;
693 unsigned long mode_flags = dsi_dev->mode_flags;
704 struct device *dev = priv->dev;
716 dev_warn_once(dev, "Non-continuous mode unimplemented, falling back to continuous\n");
729 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
731 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
732 mode = &crtc_state->adjusted_mode;
742 dsiclk = priv->dsiclk;
747 switch (dsi_dev->format) {
772 dsi_dev->format);
781 * 1. Keep the DPI line-time and the DSI line-time as close to each
814 if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
832 dsi_hfp = dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss;
849 * Seems like sometimes HSW has to be divisible by num-lanes, but
852 dsi_hsw = roundup(dsi_hsw, priv->dsi_lanes);
854 dsi_hfp = dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss;
882 dsi_vsdly *= priv->dsi_lanes;
886 dsi_vsdly = dsi_dpi_data_start - dsi_hss - dsi_hsw - dsi_hbp;
887 dsi_vsdly = roundup(dsi_vsdly, priv->dsi_lanes);
902 dsi_vsdly /= priv->dsi_lanes;
916 if (dsi_vsdly - internal_dly > 0x3ff) {
922 tc358768_write(priv, TC358768_VSDLY, dsi_vsdly - internal_dly);
927 /* Enable D-PHY (HiZ->LP11) */
930 for (i = 0; i < dsi_dev->lanes; i++)
940 /* LP11 > 100us for D-PHY Rx Init */
941 val = tc358768_ns_to_cnt(100 * 1000, hsbyteclk_ps) - 1;
946 val = tc358768_ns_to_cnt(50, hsbyteclk_ps) - 1;
952 val = tc358768_ns_to_cnt(65, hsbyteclk_ps) - 1;
955 val2 = tc358768_ns_to_cnt(300 - tc358768_ps_to_ns(2 * ui_ps),
956 hsbyteclk_ps) - 2;
962 raw_val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(2 * ui_ps), hsbyteclk_ps) - 5;
969 val = tc358768_ns_to_cnt(val, hsbyteclk_ps) - 1;
972 raw_val = tc358768_ns_to_cnt(145 - tc358768_ps_to_ns(3 * ui_ps), hsbyteclk_ps) - 10;
980 val = val / (lptxcnt + 1) - 1;
986 hsbyteclk_ps) - 3;
992 hsbyteclk_ps) - 4;
998 for (i = 0; i < dsi_dev->lanes; i++)
1007 val = tc358768_ns_to_cnt(val, hsbyteclk_ps) / 4 - 1;
1010 hsbyteclk_ps) - 2;
1018 if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
1056 (mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIT(5) : 0);
1060 (mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIT(0) : 0);
1072 val |= (dsi_dev->lanes - 1) << 1;
1079 if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
1099 if (!priv->enabled) {
1100 dev_err(priv->dev, "Bridge is not enabled\n");
1112 dev_err(priv->dev, "Bridge enable failed: %d\n", ret);
1135 switch (priv->pd_lines) {
1159 if (!(adjusted_mode->flags &
1161 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC;
1163 if (!(adjusted_mode->flags &
1165 adjusted_mode->flags |= DRM_MODE_FLAG_PVSYNC;
1269 for (i = 0; i < ARRAY_SIZE(priv->supplies); ++i)
1270 priv->supplies[i].supply = tc358768_supplies[i];
1272 ret = devm_regulator_bulk_get(priv->dev, ARRAY_SIZE(priv->supplies),
1273 priv->supplies);
1275 dev_err(priv->dev, "failed to get regulators: %d\n", ret);
1283 struct device *dev = &client->dev;
1284 struct device_node *np = dev->of_node;
1288 return -ENODEV;
1296 priv->dev = dev;
1302 priv->refclk = devm_clk_get(dev, "refclk");
1303 if (IS_ERR(priv->refclk))
1304 return PTR_ERR(priv->refclk);
1311 priv->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1313 if (IS_ERR(priv->reset_gpio))
1314 return PTR_ERR(priv->reset_gpio);
1316 priv->regmap = devm_regmap_init_i2c(client, &tc358768_regmap_config);
1317 if (IS_ERR(priv->regmap)) {
1319 return PTR_ERR(priv->regmap);
1322 priv->dsi_host.dev = dev;
1323 priv->dsi_host.ops = &tc358768_dsi_host_ops;
1325 priv->bridge.timings = &default_tc358768_timings;
1326 priv->bridge.of_node = np;
1330 return mipi_dsi_host_register(&priv->dsi_host);
1337 mipi_dsi_host_unregister(&priv->dsi_host);