Lines Matching full:tc
417 static inline int tc_poll_timeout(struct tc_data *tc, unsigned int addr, in tc_poll_timeout() argument
424 return regmap_read_poll_timeout(tc->regmap, addr, val, in tc_poll_timeout()
429 static int tc_aux_wait_busy(struct tc_data *tc) in tc_aux_wait_busy() argument
431 return tc_poll_timeout(tc, DP0_AUXSTATUS, AUX_BUSY, 0, 100, 100000); in tc_aux_wait_busy()
434 static int tc_aux_write_data(struct tc_data *tc, const void *data, in tc_aux_write_data() argument
442 ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count); in tc_aux_write_data()
449 static int tc_aux_read_data(struct tc_data *tc, void *data, size_t size) in tc_aux_read_data() argument
454 ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count); in tc_aux_read_data()
478 struct tc_data *tc = aux_to_tc(aux); in tc_aux_transfer() local
484 ret = tc_aux_wait_busy(tc); in tc_aux_transfer()
495 ret = tc_aux_write_data(tc, msg->buffer, size); in tc_aux_transfer()
505 ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address); in tc_aux_transfer()
509 ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size)); in tc_aux_transfer()
513 ret = tc_aux_wait_busy(tc); in tc_aux_transfer()
517 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus); in tc_aux_transfer()
537 return tc_aux_read_data(tc, msg->buffer, size); in tc_aux_transfer()
562 static u32 tc_srcctrl(struct tc_data *tc) in tc_srcctrl() argument
570 if (tc->link.scrambler_dis) in tc_srcctrl()
572 if (tc->link.spread) in tc_srcctrl()
574 if (tc->link.num_lanes == 2) in tc_srcctrl()
576 if (tc->link.rate != 162000) in tc_srcctrl()
581 static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl) in tc_pllupdate() argument
585 ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN); in tc_pllupdate()
595 static int tc_pxl_pll_calc(struct tc_data *tc, u32 refclk, u32 pixelclock, in tc_pxl_pll_calc() argument
614 if (tc->bridge.type == DRM_MODE_CONNECTOR_DPI) { in tc_pxl_pll_calc()
622 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock, in tc_pxl_pll_calc()
671 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n", in tc_pxl_pll_calc()
676 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock, best_delta); in tc_pxl_pll_calc()
677 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk, in tc_pxl_pll_calc()
705 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) in tc_pxl_pll_en() argument
710 ret = tc_pxl_pll_calc(tc, refclk, pixelclock, NULL, &pxl_pllparam); in tc_pxl_pll_en()
715 ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN); in tc_pxl_pll_en()
719 ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam); in tc_pxl_pll_en()
724 return tc_pllupdate(tc, PXL_PLLCTRL); in tc_pxl_pll_en()
727 static int tc_pxl_pll_dis(struct tc_data *tc) in tc_pxl_pll_dis() argument
730 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP); in tc_pxl_pll_dis()
733 static int tc_stream_clock_calc(struct tc_data *tc) in tc_stream_clock_calc() argument
750 return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768); in tc_stream_clock_calc()
753 static int tc_set_syspllparam(struct tc_data *tc) in tc_set_syspllparam() argument
758 rate = clk_get_rate(tc->refclk); in tc_set_syspllparam()
773 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate); in tc_set_syspllparam()
777 return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam); in tc_set_syspllparam()
780 static int tc_aux_link_setup(struct tc_data *tc) in tc_aux_link_setup() argument
786 ret = tc_set_syspllparam(tc); in tc_aux_link_setup()
790 ret = regmap_write(tc->regmap, DP_PHY_CTRL, in tc_aux_link_setup()
798 ret = tc_pllupdate(tc, DP0_PLLCTRL); in tc_aux_link_setup()
802 ret = tc_pllupdate(tc, DP1_PLLCTRL); in tc_aux_link_setup()
806 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 100, 100000); in tc_aux_link_setup()
808 dev_err(tc->dev, "Timeout waiting for PHY to become ready"); in tc_aux_link_setup()
819 ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1); in tc_aux_link_setup()
824 tc->aux.name = "TC358767 AUX i2c adapter"; in tc_aux_link_setup()
825 tc->aux.dev = tc->dev; in tc_aux_link_setup()
826 tc->aux.transfer = tc_aux_transfer; in tc_aux_link_setup()
827 drm_dp_aux_init(&tc->aux); in tc_aux_link_setup()
831 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret); in tc_aux_link_setup()
835 static int tc_get_display_props(struct tc_data *tc) in tc_get_display_props() argument
843 ret = drm_dp_dpcd_read(&tc->aux, DP_DPCD_REV, tc->link.dpcd, in tc_get_display_props()
848 revision = tc->link.dpcd[DP_DPCD_REV]; in tc_get_display_props()
849 rate = drm_dp_max_link_rate(tc->link.dpcd); in tc_get_display_props()
850 num_lanes = drm_dp_max_lane_count(tc->link.dpcd); in tc_get_display_props()
853 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n"); in tc_get_display_props()
857 tc->link.rate = rate; in tc_get_display_props()
860 dev_dbg(tc->dev, "Falling to 2 lanes\n"); in tc_get_display_props()
864 tc->link.num_lanes = num_lanes; in tc_get_display_props()
866 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, ®); in tc_get_display_props()
869 tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5; in tc_get_display_props()
871 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, ®); in tc_get_display_props()
875 tc->link.scrambler_dis = false; in tc_get_display_props()
877 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, ®); in tc_get_display_props()
880 tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; in tc_get_display_props()
882 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n", in tc_get_display_props()
884 (tc->link.rate == 162000) ? "1.62Gbps" : "2.7Gbps", in tc_get_display_props()
885 tc->link.num_lanes, in tc_get_display_props()
886 drm_dp_enhanced_frame_cap(tc->link.dpcd) ? in tc_get_display_props()
888 dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n", in tc_get_display_props()
889 tc->link.spread ? "0.5%" : "0.0%", in tc_get_display_props()
890 tc->link.scrambler_dis ? "disabled" : "enabled"); in tc_get_display_props()
891 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n", in tc_get_display_props()
892 tc->link.assr, tc->assr); in tc_get_display_props()
897 dev_err(tc->dev, "failed to read DPCD: %d\n", ret); in tc_get_display_props()
901 static int tc_set_common_video_mode(struct tc_data *tc, in tc_set_common_video_mode() argument
912 dev_dbg(tc->dev, "set mode %dx%d\n", in tc_set_common_video_mode()
914 dev_dbg(tc->dev, "H margin %d,%d sync %d\n", in tc_set_common_video_mode()
916 dev_dbg(tc->dev, "V margin %d,%d sync %d\n", in tc_set_common_video_mode()
918 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal); in tc_set_common_video_mode()
926 ret = regmap_write(tc->regmap, VPCTRL0, in tc_set_common_video_mode()
932 ret = regmap_write(tc->regmap, HTIM01, in tc_set_common_video_mode()
938 ret = regmap_write(tc->regmap, HTIM02, in tc_set_common_video_mode()
944 ret = regmap_write(tc->regmap, VTIM01, in tc_set_common_video_mode()
950 ret = regmap_write(tc->regmap, VTIM02, in tc_set_common_video_mode()
956 ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */ in tc_set_common_video_mode()
961 ret = regmap_write(tc->regmap, TSTCTL, in tc_set_common_video_mode()
971 static int tc_set_dpi_video_mode(struct tc_data *tc, in tc_set_dpi_video_mode() argument
976 if (tc->mode.flags & DRM_MODE_FLAG_NHSYNC) in tc_set_dpi_video_mode()
979 if (tc->mode.flags & DRM_MODE_FLAG_NVSYNC) in tc_set_dpi_video_mode()
982 return regmap_write(tc->regmap, POCTRL, value); in tc_set_dpi_video_mode()
985 static int tc_set_edp_video_mode(struct tc_data *tc, in tc_set_edp_video_mode() argument
1009 out_bw = tc->link.num_lanes * tc->link.rate; in tc_set_edp_video_mode()
1014 ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY, in tc_set_edp_video_mode()
1018 ret = regmap_write(tc->regmap, DP0_TOTALVAL, in tc_set_edp_video_mode()
1024 ret = regmap_write(tc->regmap, DP0_STARTVAL, in tc_set_edp_video_mode()
1030 ret = regmap_write(tc->regmap, DP0_ACTIVEVAL, in tc_set_edp_video_mode()
1045 ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval); in tc_set_edp_video_mode()
1057 ret = regmap_write(tc->regmap, DPIPXLFMT, dpipxlfmt); in tc_set_edp_video_mode()
1061 ret = regmap_write(tc->regmap, DP0_MISC, in tc_set_edp_video_mode()
1068 static int tc_wait_link_training(struct tc_data *tc) in tc_wait_link_training() argument
1073 ret = tc_poll_timeout(tc, DP0_LTSTAT, LT_LOOPDONE, in tc_wait_link_training()
1076 dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n"); in tc_wait_link_training()
1080 ret = regmap_read(tc->regmap, DP0_LTSTAT, &value); in tc_wait_link_training()
1087 static int tc_main_link_enable(struct tc_data *tc) in tc_main_link_enable() argument
1089 struct drm_dp_aux *aux = &tc->aux; in tc_main_link_enable()
1090 struct device *dev = tc->dev; in tc_main_link_enable()
1096 dev_dbg(tc->dev, "link enable\n"); in tc_main_link_enable()
1098 ret = regmap_read(tc->regmap, DP0CTL, &value); in tc_main_link_enable()
1103 ret = regmap_write(tc->regmap, DP0CTL, 0); in tc_main_link_enable()
1108 ret = regmap_write(tc->regmap, DP0_SRCCTRL, in tc_main_link_enable()
1109 tc_srcctrl(tc) | in tc_main_link_enable()
1110 FIELD_PREP(DP0_SRCCTRL_PRE0, tc->pre_emphasis[0]) | in tc_main_link_enable()
1111 FIELD_PREP(DP0_SRCCTRL_PRE1, tc->pre_emphasis[1])); in tc_main_link_enable()
1115 ret = regmap_write(tc->regmap, DP1_SRCCTRL, in tc_main_link_enable()
1116 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) | in tc_main_link_enable()
1117 ((tc->link.rate != 162000) ? DP0_SRCCTRL_BW27 : 0) | in tc_main_link_enable()
1118 FIELD_PREP(DP1_SRCCTRL_PRE, tc->pre_emphasis[1])); in tc_main_link_enable()
1122 ret = tc_set_syspllparam(tc); in tc_main_link_enable()
1128 if (tc->link.num_lanes == 2) in tc_main_link_enable()
1131 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); in tc_main_link_enable()
1136 ret = tc_pllupdate(tc, DP0_PLLCTRL); in tc_main_link_enable()
1140 ret = tc_pllupdate(tc, DP1_PLLCTRL); in tc_main_link_enable()
1146 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); in tc_main_link_enable()
1149 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); in tc_main_link_enable()
1151 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 500, 100000); in tc_main_link_enable()
1158 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8); in tc_main_link_enable()
1167 * check is tc configured for same mode in tc_main_link_enable()
1169 if (tc->assr != tc->link.assr) { in tc_main_link_enable()
1171 tc->assr); in tc_main_link_enable()
1173 tmp[0] = tc->assr; in tc_main_link_enable()
1182 if (tmp[0] != tc->assr) { in tc_main_link_enable()
1184 tc->assr); in tc_main_link_enable()
1186 tc->link.scrambler_dis = true; in tc_main_link_enable()
1191 tmp[0] = drm_dp_link_rate_to_bw_code(tc->link.rate); in tc_main_link_enable()
1192 tmp[1] = tc->link.num_lanes; in tc_main_link_enable()
1194 if (drm_dp_enhanced_frame_cap(tc->link.dpcd)) in tc_main_link_enable()
1202 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00; in tc_main_link_enable()
1211 FIELD_PREP(DP_TRAIN_PRE_EMPHASIS_MASK, tc->pre_emphasis[0]); in tc_main_link_enable()
1213 FIELD_PREP(DP_TRAIN_PRE_EMPHASIS_MASK, tc->pre_emphasis[1]); in tc_main_link_enable()
1221 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL, in tc_main_link_enable()
1227 ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL, in tc_main_link_enable()
1234 ret = regmap_write(tc->regmap, DP0_SRCCTRL, in tc_main_link_enable()
1235 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | in tc_main_link_enable()
1238 FIELD_PREP(DP0_SRCCTRL_PRE0, tc->pre_emphasis[0]) | in tc_main_link_enable()
1239 FIELD_PREP(DP0_SRCCTRL_PRE1, tc->pre_emphasis[1])); in tc_main_link_enable()
1244 ret = regmap_write(tc->regmap, DP0CTL, in tc_main_link_enable()
1245 (drm_dp_enhanced_frame_cap(tc->link.dpcd) ? in tc_main_link_enable()
1252 ret = tc_wait_link_training(tc); in tc_main_link_enable()
1257 dev_err(tc->dev, "Link training phase 1 failed: %s\n", in tc_main_link_enable()
1265 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL, in tc_main_link_enable()
1271 ret = regmap_write(tc->regmap, DP0_SRCCTRL, in tc_main_link_enable()
1272 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | in tc_main_link_enable()
1275 FIELD_PREP(DP0_SRCCTRL_PRE0, tc->pre_emphasis[0]) | in tc_main_link_enable()
1276 FIELD_PREP(DP0_SRCCTRL_PRE1, tc->pre_emphasis[1])); in tc_main_link_enable()
1281 ret = tc_wait_link_training(tc); in tc_main_link_enable()
1286 dev_err(tc->dev, "Link training phase 2 failed: %s\n", in tc_main_link_enable()
1301 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) | in tc_main_link_enable()
1303 FIELD_PREP(DP0_SRCCTRL_PRE0, tc->pre_emphasis[0]) | in tc_main_link_enable()
1304 FIELD_PREP(DP0_SRCCTRL_PRE1, tc->pre_emphasis[1])); in tc_main_link_enable()
1310 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00; in tc_main_link_enable()
1325 dev_err(tc->dev, "Lane 0 failed: %x\n", value); in tc_main_link_enable()
1329 if (tc->link.num_lanes == 2) { in tc_main_link_enable()
1333 dev_err(tc->dev, "Lane 1 failed: %x\n", value); in tc_main_link_enable()
1338 dev_err(tc->dev, "Interlane align failed\n"); in tc_main_link_enable()
1355 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret); in tc_main_link_enable()
1358 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret); in tc_main_link_enable()
1362 static int tc_main_link_disable(struct tc_data *tc) in tc_main_link_disable() argument
1366 dev_dbg(tc->dev, "link disable\n"); in tc_main_link_disable()
1368 ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0); in tc_main_link_disable()
1372 ret = regmap_write(tc->regmap, DP0CTL, 0); in tc_main_link_disable()
1376 return regmap_update_bits(tc->regmap, DP_PHY_CTRL, in tc_main_link_disable()
1381 static int tc_dsi_rx_enable(struct tc_data *tc) in tc_dsi_rx_enable() argument
1386 regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 5); in tc_dsi_rx_enable()
1387 regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 5); in tc_dsi_rx_enable()
1388 regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 5); in tc_dsi_rx_enable()
1389 regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 5); in tc_dsi_rx_enable()
1390 regmap_write(tc->regmap, PPI_D0S_ATMR, 0); in tc_dsi_rx_enable()
1391 regmap_write(tc->regmap, PPI_D1S_ATMR, 0); in tc_dsi_rx_enable()
1392 regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE); in tc_dsi_rx_enable()
1393 regmap_write(tc->regmap, PPI_LPTXTIMECNT, LPX_PERIOD); in tc_dsi_rx_enable()
1395 value = ((LANEENABLE_L0EN << tc->dsi->lanes) - LANEENABLE_L0EN) | in tc_dsi_rx_enable()
1397 regmap_write(tc->regmap, PPI_LANEENABLE, value); in tc_dsi_rx_enable()
1398 regmap_write(tc->regmap, DSI_LANEENABLE, value); in tc_dsi_rx_enable()
1406 ret = regmap_write(tc->regmap, SYSCTRL, value); in tc_dsi_rx_enable()
1412 regmap_write(tc->regmap, PPI_STARTPPI, PPI_START_FUNCTION); in tc_dsi_rx_enable()
1413 regmap_write(tc->regmap, DSI_STARTDSI, DSI_RX_START); in tc_dsi_rx_enable()
1418 static int tc_dpi_rx_enable(struct tc_data *tc) in tc_dpi_rx_enable() argument
1428 return regmap_write(tc->regmap, SYSCTRL, value); in tc_dpi_rx_enable()
1431 static int tc_dpi_stream_enable(struct tc_data *tc) in tc_dpi_stream_enable() argument
1435 dev_dbg(tc->dev, "enable video stream\n"); in tc_dpi_stream_enable()
1438 ret = tc_set_syspllparam(tc); in tc_dpi_stream_enable()
1446 ret = tc_pllupdate(tc, DP0_PLLCTRL); in tc_dpi_stream_enable()
1450 ret = tc_pllupdate(tc, DP1_PLLCTRL); in tc_dpi_stream_enable()
1455 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk), in tc_dpi_stream_enable()
1456 1000 * tc->mode.clock); in tc_dpi_stream_enable()
1460 ret = tc_set_common_video_mode(tc, &tc->mode); in tc_dpi_stream_enable()
1464 ret = tc_set_dpi_video_mode(tc, &tc->mode); in tc_dpi_stream_enable()
1468 return tc_dsi_rx_enable(tc); in tc_dpi_stream_enable()
1471 static int tc_dpi_stream_disable(struct tc_data *tc) in tc_dpi_stream_disable() argument
1473 dev_dbg(tc->dev, "disable video stream\n"); in tc_dpi_stream_disable()
1475 tc_pxl_pll_dis(tc); in tc_dpi_stream_disable()
1480 static int tc_edp_stream_enable(struct tc_data *tc) in tc_edp_stream_enable() argument
1485 dev_dbg(tc->dev, "enable video stream\n"); in tc_edp_stream_enable()
1498 if (tc->input_connector_dsi || tc_test_pattern) { in tc_edp_stream_enable()
1499 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk), in tc_edp_stream_enable()
1500 1000 * tc->mode.clock); in tc_edp_stream_enable()
1505 ret = tc_set_common_video_mode(tc, &tc->mode); in tc_edp_stream_enable()
1509 ret = tc_set_edp_video_mode(tc, &tc->mode); in tc_edp_stream_enable()
1514 ret = tc_stream_clock_calc(tc); in tc_edp_stream_enable()
1519 if (drm_dp_enhanced_frame_cap(tc->link.dpcd)) in tc_edp_stream_enable()
1521 ret = regmap_write(tc->regmap, DP0CTL, value); in tc_edp_stream_enable()
1533 ret = regmap_write(tc->regmap, DP0CTL, value); in tc_edp_stream_enable()
1538 if (tc->input_connector_dsi) in tc_edp_stream_enable()
1539 return tc_dsi_rx_enable(tc); in tc_edp_stream_enable()
1541 return tc_dpi_rx_enable(tc); in tc_edp_stream_enable()
1544 static int tc_edp_stream_disable(struct tc_data *tc) in tc_edp_stream_disable() argument
1548 dev_dbg(tc->dev, "disable video stream\n"); in tc_edp_stream_disable()
1550 ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0); in tc_edp_stream_disable()
1554 tc_pxl_pll_dis(tc); in tc_edp_stream_disable()
1563 struct tc_data *tc = bridge_to_tc(bridge); in tc_dpi_bridge_atomic_enable() local
1566 ret = tc_dpi_stream_enable(tc); in tc_dpi_bridge_atomic_enable()
1568 dev_err(tc->dev, "main link stream start error: %d\n", ret); in tc_dpi_bridge_atomic_enable()
1569 tc_main_link_disable(tc); in tc_dpi_bridge_atomic_enable()
1577 struct tc_data *tc = bridge_to_tc(bridge); in tc_dpi_bridge_atomic_disable() local
1580 ret = tc_dpi_stream_disable(tc); in tc_dpi_bridge_atomic_disable()
1582 dev_err(tc->dev, "main link stream stop error: %d\n", ret); in tc_dpi_bridge_atomic_disable()
1588 struct tc_data *tc = bridge_to_tc(bridge); in tc_edp_bridge_atomic_enable() local
1591 ret = tc_get_display_props(tc); in tc_edp_bridge_atomic_enable()
1593 dev_err(tc->dev, "failed to read display props: %d\n", ret); in tc_edp_bridge_atomic_enable()
1597 ret = tc_main_link_enable(tc); in tc_edp_bridge_atomic_enable()
1599 dev_err(tc->dev, "main link enable error: %d\n", ret); in tc_edp_bridge_atomic_enable()
1603 ret = tc_edp_stream_enable(tc); in tc_edp_bridge_atomic_enable()
1605 dev_err(tc->dev, "main link stream start error: %d\n", ret); in tc_edp_bridge_atomic_enable()
1606 tc_main_link_disable(tc); in tc_edp_bridge_atomic_enable()
1614 struct tc_data *tc = bridge_to_tc(bridge); in tc_edp_bridge_atomic_disable() local
1617 ret = tc_edp_stream_disable(tc); in tc_edp_bridge_atomic_disable()
1619 dev_err(tc->dev, "main link stream stop error: %d\n", ret); in tc_edp_bridge_atomic_disable()
1621 ret = tc_main_link_disable(tc); in tc_edp_bridge_atomic_disable()
1623 dev_err(tc->dev, "main link disable error: %d\n", ret); in tc_edp_bridge_atomic_disable()
1631 struct tc_data *tc = bridge_to_tc(bridge); in tc_dpi_atomic_check() local
1635 ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk), in tc_dpi_atomic_check()
1655 struct tc_data *tc = bridge_to_tc(bridge); in tc_edp_atomic_check() local
1659 ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk), in tc_edp_atomic_check()
1691 struct tc_data *tc = bridge_to_tc(bridge); in tc_edp_mode_valid() local
1700 avail = tc->link.num_lanes * tc->link.rate; in tc_edp_mode_valid()
1712 struct tc_data *tc = bridge_to_tc(bridge); in tc_bridge_mode_set() local
1714 drm_mode_copy(&tc->mode, adj); in tc_bridge_mode_set()
1720 struct tc_data *tc = bridge_to_tc(bridge); in tc_edid_read() local
1723 ret = tc_get_display_props(tc); in tc_edid_read()
1725 dev_err(tc->dev, "failed to read display props: %d\n", ret); in tc_edid_read()
1729 return drm_edid_read_ddc(connector, &tc->aux.ddc); in tc_edid_read()
1734 struct tc_data *tc = connector_to_tc(connector); in tc_connector_get_modes() local
1739 ret = tc_get_display_props(tc); in tc_connector_get_modes()
1741 dev_err(tc->dev, "failed to read display props: %d\n", ret); in tc_connector_get_modes()
1745 if (tc->panel_bridge) { in tc_connector_get_modes()
1746 num_modes = drm_bridge_get_modes(tc->panel_bridge, connector); in tc_connector_get_modes()
1751 drm_edid = tc_edid_read(&tc->bridge, connector); in tc_connector_get_modes()
1766 struct tc_data *tc = bridge_to_tc(bridge); in tc_bridge_detect() local
1771 ret = regmap_read(tc->regmap, GPIOI, &val); in tc_bridge_detect()
1775 conn = val & BIT(tc->hpd_pin); in tc_bridge_detect()
1786 struct tc_data *tc = connector_to_tc(connector); in tc_connector_detect() local
1788 if (tc->hpd_pin >= 0) in tc_connector_detect()
1789 return tc_bridge_detect(&tc->bridge, connector); in tc_connector_detect()
1791 if (tc->panel_bridge) in tc_connector_detect()
1810 struct tc_data *tc = bridge_to_tc(bridge); in tc_dpi_bridge_attach() local
1812 if (!tc->panel_bridge) in tc_dpi_bridge_attach()
1815 return drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge, in tc_dpi_bridge_attach()
1816 &tc->bridge, flags); in tc_dpi_bridge_attach()
1824 struct tc_data *tc = bridge_to_tc(bridge); in tc_edp_bridge_attach() local
1828 if (tc->panel_bridge) { in tc_edp_bridge_attach()
1830 ret = drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge, in tc_edp_bridge_attach()
1831 &tc->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR); in tc_edp_bridge_attach()
1839 tc->aux.drm_dev = drm; in tc_edp_bridge_attach()
1840 ret = drm_dp_aux_register(&tc->aux); in tc_edp_bridge_attach()
1845 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs); in tc_edp_bridge_attach()
1846 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, tc->bridge.type); in tc_edp_bridge_attach()
1851 if (tc->hpd_pin >= 0) { in tc_edp_bridge_attach()
1852 if (tc->have_irq) in tc_edp_bridge_attach()
1853 tc->connector.polled = DRM_CONNECTOR_POLL_HPD; in tc_edp_bridge_attach()
1855 tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT | in tc_edp_bridge_attach()
1859 drm_display_info_set_bus_formats(&tc->connector.display_info, in tc_edp_bridge_attach()
1861 tc->connector.display_info.bus_flags = in tc_edp_bridge_attach()
1865 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder); in tc_edp_bridge_attach()
1869 drm_dp_aux_unregister(&tc->aux); in tc_edp_bridge_attach()
2229 struct tc_data *tc = arg; in tc_irq_handler() local
2233 r = regmap_read(tc->regmap, INTSTS_G, &val); in tc_irq_handler()
2243 regmap_read(tc->regmap, SYSSTAT, &stat); in tc_irq_handler()
2245 dev_err(tc->dev, "syserr %x\n", stat); in tc_irq_handler()
2248 if (tc->hpd_pin >= 0 && tc->bridge.dev && tc->aux.drm_dev) { in tc_irq_handler()
2255 bool h = val & INT_GPIO_H(tc->hpd_pin); in tc_irq_handler()
2256 bool lc = val & INT_GPIO_LC(tc->hpd_pin); in tc_irq_handler()
2259 dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin, in tc_irq_handler()
2261 drm_kms_helper_hotplug_event(tc->bridge.dev); in tc_irq_handler()
2265 regmap_write(tc->regmap, INTSTS_G, val); in tc_irq_handler()
2270 static int tc_mipi_dsi_host_attach(struct tc_data *tc) in tc_mipi_dsi_host_attach() argument
2272 struct device *dev = tc->dev; in tc_mipi_dsi_host_attach()
2302 tc->dsi = dsi; in tc_mipi_dsi_host_attach()
2317 static int tc_probe_dpi_bridge_endpoint(struct tc_data *tc) in tc_probe_dpi_bridge_endpoint() argument
2319 struct device *dev = tc->dev; in tc_probe_dpi_bridge_endpoint()
2337 tc->panel_bridge = bridge; in tc_probe_dpi_bridge_endpoint()
2338 tc->bridge.type = DRM_MODE_CONNECTOR_DPI; in tc_probe_dpi_bridge_endpoint()
2346 static int tc_probe_edp_bridge_endpoint(struct tc_data *tc) in tc_probe_edp_bridge_endpoint() argument
2348 struct device *dev = tc->dev; in tc_probe_edp_bridge_endpoint()
2365 tc->panel_bridge = panel_bridge; in tc_probe_edp_bridge_endpoint()
2366 tc->bridge.type = DRM_MODE_CONNECTOR_eDP; in tc_probe_edp_bridge_endpoint()
2368 tc->bridge.type = DRM_MODE_CONNECTOR_DisplayPort; in tc_probe_edp_bridge_endpoint()
2371 if (tc->hpd_pin >= 0) in tc_probe_edp_bridge_endpoint()
2372 tc->bridge.ops |= DRM_BRIDGE_OP_DETECT; in tc_probe_edp_bridge_endpoint()
2373 tc->bridge.ops |= DRM_BRIDGE_OP_EDID; in tc_probe_edp_bridge_endpoint()
2419 static int tc_probe_bridge_endpoint(struct tc_data *tc, enum tc_mode mode) in tc_probe_bridge_endpoint() argument
2421 struct device *dev = tc->dev; in tc_probe_bridge_endpoint()
2429 tc->pre_emphasis, in tc_probe_bridge_endpoint()
2430 ARRAY_SIZE(tc->pre_emphasis)); in tc_probe_bridge_endpoint()
2432 if (tc->pre_emphasis[0] < 0 || tc->pre_emphasis[0] > 2 || in tc_probe_bridge_endpoint()
2433 tc->pre_emphasis[1] < 0 || tc->pre_emphasis[1] > 2) { in tc_probe_bridge_endpoint()
2442 tc->input_connector_dsi = false; in tc_probe_bridge_endpoint()
2443 return tc_probe_edp_bridge_endpoint(tc); in tc_probe_bridge_endpoint()
2445 tc->input_connector_dsi = true; in tc_probe_bridge_endpoint()
2446 return tc_probe_dpi_bridge_endpoint(tc); in tc_probe_bridge_endpoint()
2448 tc->input_connector_dsi = true; in tc_probe_bridge_endpoint()
2449 return tc_probe_edp_bridge_endpoint(tc); in tc_probe_bridge_endpoint()
2460 struct tc_data *tc; in tc_probe() local
2467 tc = devm_drm_bridge_alloc(dev, struct tc_data, bridge, funcs); in tc_probe()
2468 if (IS_ERR(tc)) in tc_probe()
2469 return PTR_ERR(tc); in tc_probe()
2471 tc->dev = dev; in tc_probe()
2473 ret = tc_probe_bridge_endpoint(tc, mode); in tc_probe()
2477 tc->refclk = devm_clk_get_enabled(dev, "ref"); in tc_probe()
2478 if (IS_ERR(tc->refclk)) in tc_probe()
2479 return dev_err_probe(dev, PTR_ERR(tc->refclk), in tc_probe()
2486 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH); in tc_probe()
2487 if (IS_ERR(tc->sd_gpio)) in tc_probe()
2488 return PTR_ERR(tc->sd_gpio); in tc_probe()
2490 if (tc->sd_gpio) { in tc_probe()
2491 gpiod_set_value_cansleep(tc->sd_gpio, 0); in tc_probe()
2496 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); in tc_probe()
2497 if (IS_ERR(tc->reset_gpio)) in tc_probe()
2498 return PTR_ERR(tc->reset_gpio); in tc_probe()
2500 if (tc->reset_gpio) { in tc_probe()
2501 gpiod_set_value_cansleep(tc->reset_gpio, 1); in tc_probe()
2505 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config); in tc_probe()
2506 if (IS_ERR(tc->regmap)) { in tc_probe()
2507 ret = PTR_ERR(tc->regmap); in tc_probe()
2513 &tc->hpd_pin); in tc_probe()
2515 tc->hpd_pin = -ENODEV; in tc_probe()
2517 if (tc->hpd_pin < 0 || tc->hpd_pin > 1) { in tc_probe()
2525 regmap_write(tc->regmap, INTCTL_G, INT_SYSERR); in tc_probe()
2530 "tc358767-irq", tc); in tc_probe()
2536 tc->have_irq = true; in tc_probe()
2539 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev); in tc_probe()
2541 dev_err(tc->dev, "can not read device ID: %d\n", ret); in tc_probe()
2545 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) { in tc_probe()
2546 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev); in tc_probe()
2550 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */ in tc_probe()
2552 if (!tc->reset_gpio) { in tc_probe()
2559 regmap_update_bits(tc->regmap, SYSRSTENB, in tc_probe()
2562 regmap_update_bits(tc->regmap, SYSRSTENB, in tc_probe()
2568 if (tc->hpd_pin >= 0) { in tc_probe()
2569 u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT; in tc_probe()
2570 u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin); in tc_probe()
2573 regmap_write(tc->regmap, lcnt_reg, in tc_probe()
2574 clk_get_rate(tc->refclk) * 2 / 1000); in tc_probe()
2576 regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin)); in tc_probe()
2578 if (tc->have_irq) { in tc_probe()
2580 regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc); in tc_probe()
2584 if (tc->bridge.type != DRM_MODE_CONNECTOR_DPI) { /* (e)DP output */ in tc_probe()
2585 ret = tc_aux_link_setup(tc); in tc_probe()
2590 tc->bridge.of_node = dev->of_node; in tc_probe()
2591 drm_bridge_add(&tc->bridge); in tc_probe()
2593 i2c_set_clientdata(client, tc); in tc_probe()
2595 if (tc->input_connector_dsi) { /* DSI input */ in tc_probe()
2596 ret = tc_mipi_dsi_host_attach(tc); in tc_probe()
2598 drm_bridge_remove(&tc->bridge); in tc_probe()
2608 struct tc_data *tc = i2c_get_clientdata(client); in tc_remove() local
2610 drm_bridge_remove(&tc->bridge); in tc_remove()