Lines Matching +full:lanes +full:- +full:per +full:- +full:direction
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TC358767/TC358867/TC9595 DSI/DPI-to-DPI/(e)DP bridge driver
6 * All modes are supported -- DPI->(e)DP / DSI->DPI / DSI->(e)DP .
27 #include <linux/media-bus-format.h>
44 /* DSI D-PHY Layer registers */
77 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
110 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
166 #define GPIOC 0x0544 /* GPIO Direction Control Register */
184 #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
219 #define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */
296 #define PHY_2LANE BIT(2) /* PHY Enable 2 lanes */
390 /* HPD pin number (0 or 1) or -ENODEV */
416 return regmap_read_poll_timeout(tc->regmap, addr, val,
434 ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count);
446 ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count);
457 u32 auxcfg0 = msg->request;
460 auxcfg0 |= FIELD_PREP(DP0_AUXCFG0_BSIZE, size - 1);
471 size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size);
472 u8 request = msg->request & ~DP_AUX_I2C_MOT;
487 ret = tc_aux_write_data(tc, msg->buffer, size);
493 return -EINVAL;
497 ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address);
501 ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size));
509 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus);
514 return -ETIMEDOUT;
516 * For some reason address-only DP_AUX_I2C_WRITE (MOT), still
519 * address-only transfer
523 msg->reply = FIELD_GET(AUX_STATUS, auxstatus);
529 return tc_aux_read_data(tc, msg->buffer, size);
562 if (tc->link.scrambler_dis)
564 if (tc->link.spread)
566 if (tc->link.num_lanes == 2)
567 reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */
568 if (tc->link.rate != 162000)
577 ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN);
603 * - DPI ..... 0 to 100 MHz
604 * - (e)DP ... 150 to 650 MHz
606 if (tc->bridge.type == DRM_MODE_CONNECTOR_DPI) {
614 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock,
649 delta = clk - pixelclock;
663 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n",
665 return -EINVAL;
668 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock, best_delta);
669 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
682 pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */
683 pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */
707 ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN);
711 ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam);
722 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP);
742 return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768);
750 rate = clk_get_rate(tc->refclk);
765 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
766 return -EINVAL;
769 return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam);
777 /* Setup DP-PHY / PLL */
782 ret = regmap_write(tc->regmap, DP_PHY_CTRL,
799 if (ret == -ETIMEDOUT) {
800 dev_err(tc->dev, "Timeout waiting for PHY to become ready");
811 ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1);
816 tc->aux.name = "TC358767 AUX i2c adapter";
817 tc->aux.dev = tc->dev;
818 tc->aux.transfer = tc_aux_transfer;
819 drm_dp_aux_init(&tc->aux);
823 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret);
835 ret = drm_dp_dpcd_read(&tc->aux, DP_DPCD_REV, tc->link.dpcd,
840 revision = tc->link.dpcd[DP_DPCD_REV];
841 rate = drm_dp_max_link_rate(tc->link.dpcd);
842 num_lanes = drm_dp_max_lane_count(tc->link.dpcd);
845 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n");
849 tc->link.rate = rate;
852 dev_dbg(tc->dev, "Falling to 2 lanes\n");
856 tc->link.num_lanes = num_lanes;
858 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, ®);
861 tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5;
863 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, ®);
867 tc->link.scrambler_dis = false;
869 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, ®);
872 tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
874 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
876 (tc->link.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
877 tc->link.num_lanes,
878 drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
880 dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n",
881 tc->link.spread ? "0.5%" : "0.0%",
882 tc->link.scrambler_dis ? "disabled" : "enabled");
883 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n",
884 tc->link.assr, tc->assr);
889 dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
896 int left_margin = mode->htotal - mode->hsync_end;
897 int right_margin = mode->hsync_start - mode->hdisplay;
898 int hsync_len = mode->hsync_end - mode->hsync_start;
899 int upper_margin = mode->vtotal - mode->vsync_end;
900 int lower_margin = mode->vsync_start - mode->vdisplay;
901 int vsync_len = mode->vsync_end - mode->vsync_start;
904 dev_dbg(tc->dev, "set mode %dx%d\n",
905 mode->hdisplay, mode->vdisplay);
906 dev_dbg(tc->dev, "H margin %d,%d sync %d\n",
908 dev_dbg(tc->dev, "V margin %d,%d sync %d\n",
910 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
918 ret = regmap_write(tc->regmap, VPCTRL0,
924 ret = regmap_write(tc->regmap, HTIM01,
930 ret = regmap_write(tc->regmap, HTIM02,
931 FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) |
936 ret = regmap_write(tc->regmap, VTIM01,
942 ret = regmap_write(tc->regmap, VTIM02,
944 FIELD_PREP(VDISPR, mode->vdisplay));
948 ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */
953 ret = regmap_write(tc->regmap, TSTCTL,
968 if (tc->mode.flags & DRM_MODE_FLAG_NHSYNC)
971 if (tc->mode.flags & DRM_MODE_FLAG_NVSYNC)
974 return regmap_write(tc->regmap, POCTRL, value);
984 int left_margin = mode->htotal - mode->hsync_end;
985 int hsync_len = mode->hsync_end - mode->hsync_start;
986 int upper_margin = mode->vtotal - mode->vsync_end;
987 int vsync_len = mode->vsync_end - mode->vsync_start;
1000 in_bw = mode->clock * bits_per_pixel / 8;
1001 out_bw = tc->link.num_lanes * tc->link.rate;
1005 vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
1006 ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY,
1010 ret = regmap_write(tc->regmap, DP0_TOTALVAL,
1011 FIELD_PREP(H_TOTAL, mode->htotal) |
1012 FIELD_PREP(V_TOTAL, mode->vtotal));
1016 ret = regmap_write(tc->regmap, DP0_STARTVAL,
1022 ret = regmap_write(tc->regmap, DP0_ACTIVEVAL,
1023 FIELD_PREP(V_ACT, mode->vdisplay) |
1024 FIELD_PREP(H_ACT, mode->hdisplay));
1031 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1034 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1037 ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval);
1043 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1046 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1049 ret = regmap_write(tc->regmap, DPIPXLFMT, dpipxlfmt);
1053 ret = regmap_write(tc->regmap, DP0_MISC,
1068 dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n");
1072 ret = regmap_read(tc->regmap, DP0_LTSTAT, &value);
1081 struct drm_dp_aux *aux = &tc->aux;
1082 struct device *dev = tc->dev;
1088 dev_dbg(tc->dev, "link enable\n");
1090 ret = regmap_read(tc->regmap, DP0CTL, &value);
1095 ret = regmap_write(tc->regmap, DP0CTL, 0);
1100 ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1102 FIELD_PREP(DP0_SRCCTRL_PRE0, tc->pre_emphasis[0]) |
1103 FIELD_PREP(DP0_SRCCTRL_PRE1, tc->pre_emphasis[1]));
1107 ret = regmap_write(tc->regmap, DP1_SRCCTRL,
1108 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
1109 ((tc->link.rate != 162000) ? DP0_SRCCTRL_BW27 : 0) |
1110 FIELD_PREP(DP1_SRCCTRL_PRE, tc->pre_emphasis[1]));
1120 if (tc->link.num_lanes == 2)
1123 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
1138 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
1141 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
1149 /* Set misc: 8 bits per color */
1150 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
1161 if (tc->assr != tc->link.assr) {
1163 tc->assr);
1165 tmp[0] = tc->assr;
1174 if (tmp[0] != tc->assr) {
1176 tc->assr);
1178 tc->link.scrambler_dis = true;
1183 tmp[0] = drm_dp_link_rate_to_bw_code(tc->link.rate);
1184 tmp[1] = tc->link.num_lanes;
1186 if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
1194 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
1201 /* Reset voltage-swing & pre-emphasis */
1203 FIELD_PREP(DP_TRAIN_PRE_EMPHASIS_MASK, tc->pre_emphasis[0]);
1205 FIELD_PREP(DP_TRAIN_PRE_EMPHASIS_MASK, tc->pre_emphasis[1]);
1210 /* Clock-Recovery */
1213 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1219 ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL,
1226 ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1230 FIELD_PREP(DP0_SRCCTRL_PRE0, tc->pre_emphasis[0]) |
1231 FIELD_PREP(DP0_SRCCTRL_PRE1, tc->pre_emphasis[1]));
1236 ret = regmap_write(tc->regmap, DP0CTL,
1237 (drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
1249 dev_err(tc->dev, "Link training phase 1 failed: %s\n",
1251 return -ENODEV;
1257 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1263 ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1267 FIELD_PREP(DP0_SRCCTRL_PRE0, tc->pre_emphasis[0]) |
1268 FIELD_PREP(DP0_SRCCTRL_PRE1, tc->pre_emphasis[1]));
1278 dev_err(tc->dev, "Link training phase 2 failed: %s\n",
1280 return -ENODEV;
1293 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) |
1295 FIELD_PREP(DP0_SRCCTRL_PRE0, tc->pre_emphasis[0]) |
1296 FIELD_PREP(DP0_SRCCTRL_PRE1, tc->pre_emphasis[1]));
1302 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00;
1317 dev_err(tc->dev, "Lane 0 failed: %x\n", value);
1318 ret = -ENODEV;
1321 if (tc->link.num_lanes == 2) {
1325 dev_err(tc->dev, "Lane 1 failed: %x\n", value);
1326 ret = -ENODEV;
1330 dev_err(tc->dev, "Interlane align failed\n");
1331 ret = -ENODEV;
1347 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret);
1350 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
1358 dev_dbg(tc->dev, "link disable\n");
1360 ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0);
1364 ret = regmap_write(tc->regmap, DP0CTL, 0);
1368 return regmap_update_bits(tc->regmap, DP_PHY_CTRL,
1378 regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 5);
1379 regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 5);
1380 regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 5);
1381 regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 5);
1382 regmap_write(tc->regmap, PPI_D0S_ATMR, 0);
1383 regmap_write(tc->regmap, PPI_D1S_ATMR, 0);
1384 regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
1385 regmap_write(tc->regmap, PPI_LPTXTIMECNT, LPX_PERIOD);
1387 value = ((LANEENABLE_L0EN << tc->dsi->lanes) - LANEENABLE_L0EN) |
1389 regmap_write(tc->regmap, PPI_LANEENABLE, value);
1390 regmap_write(tc->regmap, DSI_LANEENABLE, value);
1398 ret = regmap_write(tc->regmap, SYSCTRL, value);
1404 regmap_write(tc->regmap, PPI_STARTPPI, PPI_START_FUNCTION);
1405 regmap_write(tc->regmap, DSI_STARTDSI, DSI_RX_START);
1420 return regmap_write(tc->regmap, SYSCTRL, value);
1427 dev_dbg(tc->dev, "enable video stream\n");
1447 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
1448 1000 * tc->mode.clock);
1452 ret = tc_set_common_video_mode(tc, &tc->mode);
1456 ret = tc_set_dpi_video_mode(tc, &tc->mode);
1465 dev_dbg(tc->dev, "disable video stream\n");
1477 dev_dbg(tc->dev, "enable video stream\n");
1482 * Per TC9595XBG datasheet Revision 0.1 2018-12-27 Figure 4.18
1486 * In case built-in test pattern is desired OR DSI input mode
1490 if (tc->input_connector_dsi || tc_test_pattern) {
1491 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
1492 1000 * tc->mode.clock);
1497 ret = tc_set_common_video_mode(tc, &tc->mode);
1501 ret = tc_set_edp_video_mode(tc, &tc->mode);
1511 if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
1513 ret = regmap_write(tc->regmap, DP0CTL, value);
1525 ret = regmap_write(tc->regmap, DP0CTL, value);
1530 if (tc->input_connector_dsi)
1540 dev_dbg(tc->dev, "disable video stream\n");
1542 ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0);
1560 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1574 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1585 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1591 dev_err(tc->dev, "main link enable error: %d\n", ret);
1597 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1611 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1615 dev_err(tc->dev, "main link disable error: %d\n", ret);
1627 ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk),
1628 crtc_state->mode.clock * 1000,
1633 crtc_state->adjusted_mode.clock = adjusted_clock / 1000;
1635 /* DSI->DPI interface clock limitation: upto 100 MHz */
1636 if (crtc_state->adjusted_mode.clock > 100000)
1637 return -EINVAL;
1651 ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk),
1652 crtc_state->mode.clock * 1000,
1657 crtc_state->adjusted_mode.clock = adjusted_clock / 1000;
1659 /* DPI->(e)DP interface clock limitation: upto 154 MHz */
1660 if (crtc_state->adjusted_mode.clock > 154000)
1661 return -EINVAL;
1672 if (mode->clock > 100000)
1687 /* DPI->(e)DP interface clock limitation: up to 154 MHz */
1688 if (mode->clock > 154000)
1691 req = mode->clock * bits_per_pixel / 8;
1692 avail = tc->link.num_lanes * tc->link.rate;
1706 drm_mode_copy(&tc->mode, adj);
1717 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1721 return drm_edid_read_ddc(connector, &tc->aux.ddc);
1733 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1737 if (tc->panel_bridge) {
1738 num_modes = drm_bridge_get_modes(tc->panel_bridge, connector);
1743 drm_edid = tc_edid_read(&tc->bridge, connector);
1762 ret = regmap_read(tc->regmap, GPIOI, &val);
1766 conn = val & BIT(tc->hpd_pin);
1779 if (tc->hpd_pin >= 0)
1780 return tc_bridge_detect(&tc->bridge);
1782 if (tc->panel_bridge)
1803 if (!tc->panel_bridge)
1806 return drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge,
1807 &tc->bridge, flags);
1816 struct drm_device *drm = bridge->dev;
1819 if (tc->panel_bridge) {
1821 ret = drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge,
1822 &tc->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
1830 tc->aux.drm_dev = drm;
1831 ret = drm_dp_aux_register(&tc->aux);
1836 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
1837 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, tc->bridge.type);
1842 if (tc->hpd_pin >= 0) {
1843 if (tc->have_irq)
1844 tc->connector.polled = DRM_CONNECTOR_POLL_HPD;
1846 tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
1850 drm_display_info_set_bus_formats(&tc->connector.display_info,
1852 tc->connector.display_info.bus_flags =
1856 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
1860 drm_dp_aux_unregister(&tc->aux);
1866 drm_dp_aux_unregister(&bridge_to_tc(bridge)->aux);
1889 /* This is the DSI-end bus format */
1951 /* DSI D-PHY Layer */
2224 r = regmap_read(tc->regmap, INTSTS_G, &val);
2234 regmap_read(tc->regmap, SYSSTAT, &stat);
2236 dev_err(tc->dev, "syserr %x\n", stat);
2239 if (tc->hpd_pin >= 0 && tc->bridge.dev && tc->aux.drm_dev) {
2246 bool h = val & INT_GPIO_H(tc->hpd_pin);
2247 bool lc = val & INT_GPIO_LC(tc->hpd_pin);
2250 dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin,
2252 drm_kms_helper_hotplug_event(tc->bridge.dev);
2256 regmap_write(tc->regmap, INTSTS_G, val);
2263 struct device *dev = tc->dev;
2275 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
2283 return -EPROBE_DEFER;
2293 tc->dsi = dsi;
2294 dsi->lanes = dsi_lanes;
2295 dsi->format = MIPI_DSI_FMT_RGB888;
2296 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
2310 struct device *dev = tc->dev;
2316 ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, &bridge);
2317 if (ret && ret != -ENODEV)
2328 tc->panel_bridge = bridge;
2329 tc->bridge.type = DRM_MODE_CONNECTOR_DPI;
2330 tc->bridge.funcs = &tc_dpi_bridge_funcs;
2340 struct device *dev = tc->dev;
2345 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &panel, NULL);
2346 if (ret && ret != -ENODEV)
2357 tc->panel_bridge = panel_bridge;
2358 tc->bridge.type = DRM_MODE_CONNECTOR_eDP;
2360 tc->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
2363 tc->bridge.funcs = &tc_edp_bridge_funcs;
2364 if (tc->hpd_pin >= 0)
2365 tc->bridge.ops |= DRM_BRIDGE_OP_DETECT;
2366 tc->bridge.ops |= DRM_BRIDGE_OP_EDID;
2373 struct device *dev = tc->dev;
2387 * port@0 - DSI input
2388 * port@1 - DPI input/output
2389 * port@2 - eDP output
2392 * DPI -> port@1 -> port@2 -> eDP :: [port@0 is not connected]
2393 * DSI -> port@0 -> port@2 -> eDP :: [port@1 is not connected]
2394 * DSI -> port@0 -> port@1 -> DPI :: [port@2 is not connected]
2397 for_each_endpoint_of_node(dev->of_node, node) {
2401 return -EINVAL;
2406 of_property_read_u8_array(node, "toshiba,pre-emphasis",
2407 tc->pre_emphasis,
2408 ARRAY_SIZE(tc->pre_emphasis));
2410 if (tc->pre_emphasis[0] < 0 || tc->pre_emphasis[0] > 2 ||
2411 tc->pre_emphasis[1] < 0 || tc->pre_emphasis[1] > 2) {
2412 dev_err(dev, "Incorrect Pre-Emphasis setting, use either 0=0dB 1=3.5dB 2=6dB\n");
2414 return -EINVAL;
2420 tc->input_connector_dsi = false;
2423 tc->input_connector_dsi = true;
2426 tc->input_connector_dsi = true;
2432 return -EINVAL;
2437 struct device *dev = &client->dev;
2443 return -ENOMEM;
2445 tc->dev = dev;
2451 tc->refclk = devm_clk_get_enabled(dev, "ref");
2452 if (IS_ERR(tc->refclk))
2453 return dev_err_probe(dev, PTR_ERR(tc->refclk),
2460 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
2461 if (IS_ERR(tc->sd_gpio))
2462 return PTR_ERR(tc->sd_gpio);
2464 if (tc->sd_gpio) {
2465 gpiod_set_value_cansleep(tc->sd_gpio, 0);
2470 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
2471 if (IS_ERR(tc->reset_gpio))
2472 return PTR_ERR(tc->reset_gpio);
2474 if (tc->reset_gpio) {
2475 gpiod_set_value_cansleep(tc->reset_gpio, 1);
2479 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config);
2480 if (IS_ERR(tc->regmap)) {
2481 ret = PTR_ERR(tc->regmap);
2486 ret = of_property_read_u32(dev->of_node, "toshiba,hpd-pin",
2487 &tc->hpd_pin);
2489 tc->hpd_pin = -ENODEV;
2491 if (tc->hpd_pin < 0 || tc->hpd_pin > 1) {
2493 return -EINVAL;
2497 if (client->irq > 0) {
2499 regmap_write(tc->regmap, INTCTL_G, INT_SYSERR);
2501 ret = devm_request_threaded_irq(dev, client->irq,
2504 "tc358767-irq", tc);
2510 tc->have_irq = true;
2513 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev);
2515 dev_err(tc->dev, "can not read device ID: %d\n", ret);
2519 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) {
2520 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev);
2521 return -EINVAL;
2524 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */
2526 if (!tc->reset_gpio) {
2533 regmap_update_bits(tc->regmap, SYSRSTENB,
2536 regmap_update_bits(tc->regmap, SYSRSTENB,
2542 if (tc->hpd_pin >= 0) {
2543 u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT;
2544 u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin);
2547 regmap_write(tc->regmap, lcnt_reg,
2548 clk_get_rate(tc->refclk) * 2 / 1000);
2550 regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin));
2552 if (tc->have_irq) {
2554 regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc);
2558 if (tc->bridge.type != DRM_MODE_CONNECTOR_DPI) { /* (e)DP output */
2564 tc->bridge.of_node = dev->of_node;
2565 drm_bridge_add(&tc->bridge);
2569 if (tc->input_connector_dsi) { /* DSI input */
2572 drm_bridge_remove(&tc->bridge);
2584 drm_bridge_remove(&tc->bridge);