Lines Matching +full:i2s +full:- +full:data +full:- +full:lanes
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TC358767/TC358867/TC9595 DSI/DPI-to-DPI/(e)DP bridge driver
6 * All modes are supported -- DPI->(e)DP / DSI->DPI / DSI->(e)DP .
27 #include <linux/media-bus-format.h>
44 /* DSI D-PHY Layer registers */
77 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
110 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
184 #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
296 #define PHY_2LANE BIT(2) /* PHY Enable 2 lanes */
304 /* I2S */
305 #define I2SCFG 0x0880 /* I2S Audio Config 0 Register */
306 #define I2SCH0STAT0 0x0888 /* I2S Audio Channel 0 Status Bytes 3 to 0 */
307 #define I2SCH0STAT1 0x088c /* I2S Audio Channel 0 Status Bytes 7 to 4 */
308 #define I2SCH0STAT2 0x0890 /* I2S Audio Channel 0 Status Bytes 11 to 8 */
309 #define I2SCH0STAT3 0x0894 /* I2S Audio Channel 0 Status Bytes 15 to 12 */
310 #define I2SCH0STAT4 0x0898 /* I2S Audio Channel 0 Status Bytes 19 to 16 */
311 #define I2SCH0STAT5 0x089c /* I2S Audio Channel 0 Status Bytes 23 to 20 */
312 #define I2SCH1STAT0 0x08a0 /* I2S Audio Channel 1 Status Bytes 3 to 0 */
313 #define I2SCH1STAT1 0x08a4 /* I2S Audio Channel 1 Status Bytes 7 to 4 */
314 #define I2SCH1STAT2 0x08a8 /* I2S Audio Channel 1 Status Bytes 11 to 8 */
315 #define I2SCH1STAT3 0x08ac /* I2S Audio Channel 1 Status Bytes 15 to 12 */
316 #define I2SCH1STAT4 0x08b0 /* I2S Audio Channel 1 Status Bytes 19 to 16 */
317 #define I2SCH1STAT5 0x08b4 /* I2S Audio Channel 1 Status Bytes 23 to 20 */
390 /* HPD pin number (0 or 1) or -ENODEV */
416 return regmap_read_poll_timeout(tc->regmap, addr, val, in tc_poll_timeout()
426 static int tc_aux_write_data(struct tc_data *tc, const void *data, in tc_aux_write_data() argument
432 memcpy(auxwdata, data, size); in tc_aux_write_data()
434 ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count); in tc_aux_write_data()
441 static int tc_aux_read_data(struct tc_data *tc, void *data, size_t size) in tc_aux_read_data() argument
446 ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count); in tc_aux_read_data()
450 memcpy(data, auxrdata, size); in tc_aux_read_data()
457 u32 auxcfg0 = msg->request; in tc_auxcfg0()
460 auxcfg0 |= FIELD_PREP(DP0_AUXCFG0_BSIZE, size - 1); in tc_auxcfg0()
471 size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size); in tc_aux_transfer()
472 u8 request = msg->request & ~DP_AUX_I2C_MOT; in tc_aux_transfer()
487 ret = tc_aux_write_data(tc, msg->buffer, size); in tc_aux_transfer()
493 return -EINVAL; in tc_aux_transfer()
497 ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address); in tc_aux_transfer()
501 ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size)); in tc_aux_transfer()
509 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus); in tc_aux_transfer()
514 return -ETIMEDOUT; in tc_aux_transfer()
516 * For some reason address-only DP_AUX_I2C_WRITE (MOT), still in tc_aux_transfer()
519 * address-only transfer in tc_aux_transfer()
523 msg->reply = FIELD_GET(AUX_STATUS, auxstatus); in tc_aux_transfer()
529 return tc_aux_read_data(tc, msg->buffer, size); in tc_aux_transfer()
557 * No training pattern, skew lane 1 data by two LSCLK cycles with in tc_srcctrl()
558 * respect to lane 0 data, AutoCorrect Mode = 0 in tc_srcctrl()
562 if (tc->link.scrambler_dis) in tc_srcctrl()
564 if (tc->link.spread) in tc_srcctrl()
566 if (tc->link.num_lanes == 2) in tc_srcctrl()
567 reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */ in tc_srcctrl()
568 if (tc->link.rate != 162000) in tc_srcctrl()
577 ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN); in tc_pllupdate()
603 * - DPI ..... 0 to 100 MHz in tc_pxl_pll_calc()
604 * - (e)DP ... 150 to 650 MHz in tc_pxl_pll_calc()
606 if (tc->bridge.type == DRM_MODE_CONNECTOR_DPI) { in tc_pxl_pll_calc()
614 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock, in tc_pxl_pll_calc()
649 delta = clk - pixelclock; in tc_pxl_pll_calc()
663 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n", in tc_pxl_pll_calc()
665 return -EINVAL; in tc_pxl_pll_calc()
668 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock, best_delta); in tc_pxl_pll_calc()
669 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk, in tc_pxl_pll_calc()
682 pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */ in tc_pxl_pll_calc()
683 pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */ in tc_pxl_pll_calc()
707 ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN); in tc_pxl_pll_en()
711 ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam); in tc_pxl_pll_en()
722 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP); in tc_pxl_pll_dis()
742 return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768); in tc_stream_clock_calc()
750 rate = clk_get_rate(tc->refclk); in tc_set_syspllparam()
765 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate); in tc_set_syspllparam()
766 return -EINVAL; in tc_set_syspllparam()
769 return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam); in tc_set_syspllparam()
777 /* Setup DP-PHY / PLL */ in tc_aux_link_setup()
782 ret = regmap_write(tc->regmap, DP_PHY_CTRL, in tc_aux_link_setup()
799 if (ret == -ETIMEDOUT) { in tc_aux_link_setup()
800 dev_err(tc->dev, "Timeout waiting for PHY to become ready"); in tc_aux_link_setup()
811 ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1); in tc_aux_link_setup()
816 tc->aux.name = "TC358767 AUX i2c adapter"; in tc_aux_link_setup()
817 tc->aux.dev = tc->dev; in tc_aux_link_setup()
818 tc->aux.transfer = tc_aux_transfer; in tc_aux_link_setup()
819 drm_dp_aux_init(&tc->aux); in tc_aux_link_setup()
823 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret); in tc_aux_link_setup()
835 ret = drm_dp_dpcd_read(&tc->aux, DP_DPCD_REV, tc->link.dpcd, in tc_get_display_props()
840 revision = tc->link.dpcd[DP_DPCD_REV]; in tc_get_display_props()
841 rate = drm_dp_max_link_rate(tc->link.dpcd); in tc_get_display_props()
842 num_lanes = drm_dp_max_lane_count(tc->link.dpcd); in tc_get_display_props()
845 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n"); in tc_get_display_props()
849 tc->link.rate = rate; in tc_get_display_props()
852 dev_dbg(tc->dev, "Falling to 2 lanes\n"); in tc_get_display_props()
856 tc->link.num_lanes = num_lanes; in tc_get_display_props()
858 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, ®); in tc_get_display_props()
861 tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5; in tc_get_display_props()
863 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, ®); in tc_get_display_props()
867 tc->link.scrambler_dis = false; in tc_get_display_props()
869 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, ®); in tc_get_display_props()
872 tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; in tc_get_display_props()
874 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n", in tc_get_display_props()
876 (tc->link.rate == 162000) ? "1.62Gbps" : "2.7Gbps", in tc_get_display_props()
877 tc->link.num_lanes, in tc_get_display_props()
878 drm_dp_enhanced_frame_cap(tc->link.dpcd) ? in tc_get_display_props()
880 dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n", in tc_get_display_props()
881 tc->link.spread ? "0.5%" : "0.0%", in tc_get_display_props()
882 tc->link.scrambler_dis ? "disabled" : "enabled"); in tc_get_display_props()
883 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n", in tc_get_display_props()
884 tc->link.assr, tc->assr); in tc_get_display_props()
889 dev_err(tc->dev, "failed to read DPCD: %d\n", ret); in tc_get_display_props()
896 int left_margin = mode->htotal - mode->hsync_end; in tc_set_common_video_mode()
897 int right_margin = mode->hsync_start - mode->hdisplay; in tc_set_common_video_mode()
898 int hsync_len = mode->hsync_end - mode->hsync_start; in tc_set_common_video_mode()
899 int upper_margin = mode->vtotal - mode->vsync_end; in tc_set_common_video_mode()
900 int lower_margin = mode->vsync_start - mode->vdisplay; in tc_set_common_video_mode()
901 int vsync_len = mode->vsync_end - mode->vsync_start; in tc_set_common_video_mode()
904 dev_dbg(tc->dev, "set mode %dx%d\n", in tc_set_common_video_mode()
905 mode->hdisplay, mode->vdisplay); in tc_set_common_video_mode()
906 dev_dbg(tc->dev, "H margin %d,%d sync %d\n", in tc_set_common_video_mode()
908 dev_dbg(tc->dev, "V margin %d,%d sync %d\n", in tc_set_common_video_mode()
910 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal); in tc_set_common_video_mode()
918 ret = regmap_write(tc->regmap, VPCTRL0, in tc_set_common_video_mode()
924 ret = regmap_write(tc->regmap, HTIM01, in tc_set_common_video_mode()
930 ret = regmap_write(tc->regmap, HTIM02, in tc_set_common_video_mode()
931 FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) | in tc_set_common_video_mode()
936 ret = regmap_write(tc->regmap, VTIM01, in tc_set_common_video_mode()
942 ret = regmap_write(tc->regmap, VTIM02, in tc_set_common_video_mode()
944 FIELD_PREP(VDISPR, mode->vdisplay)); in tc_set_common_video_mode()
948 ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */ in tc_set_common_video_mode()
953 ret = regmap_write(tc->regmap, TSTCTL, in tc_set_common_video_mode()
968 if (tc->mode.flags & DRM_MODE_FLAG_NHSYNC) in tc_set_dpi_video_mode()
971 if (tc->mode.flags & DRM_MODE_FLAG_NVSYNC) in tc_set_dpi_video_mode()
974 return regmap_write(tc->regmap, POCTRL, value); in tc_set_dpi_video_mode()
984 int left_margin = mode->htotal - mode->hsync_end; in tc_set_edp_video_mode()
985 int hsync_len = mode->hsync_end - mode->hsync_start; in tc_set_edp_video_mode()
986 int upper_margin = mode->vtotal - mode->vsync_end; in tc_set_edp_video_mode()
987 int vsync_len = mode->vsync_end - mode->vsync_start; in tc_set_edp_video_mode()
1000 in_bw = mode->clock * bits_per_pixel / 8; in tc_set_edp_video_mode()
1001 out_bw = tc->link.num_lanes * tc->link.rate; in tc_set_edp_video_mode()
1005 vid_sync_dly = hsync_len + left_margin + mode->hdisplay; in tc_set_edp_video_mode()
1006 ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY, in tc_set_edp_video_mode()
1010 ret = regmap_write(tc->regmap, DP0_TOTALVAL, in tc_set_edp_video_mode()
1011 FIELD_PREP(H_TOTAL, mode->htotal) | in tc_set_edp_video_mode()
1012 FIELD_PREP(V_TOTAL, mode->vtotal)); in tc_set_edp_video_mode()
1016 ret = regmap_write(tc->regmap, DP0_STARTVAL, in tc_set_edp_video_mode()
1022 ret = regmap_write(tc->regmap, DP0_ACTIVEVAL, in tc_set_edp_video_mode()
1023 FIELD_PREP(V_ACT, mode->vdisplay) | in tc_set_edp_video_mode()
1024 FIELD_PREP(H_ACT, mode->hdisplay)); in tc_set_edp_video_mode()
1031 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in tc_set_edp_video_mode()
1034 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in tc_set_edp_video_mode()
1037 ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval); in tc_set_edp_video_mode()
1043 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in tc_set_edp_video_mode()
1046 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in tc_set_edp_video_mode()
1049 ret = regmap_write(tc->regmap, DPIPXLFMT, dpipxlfmt); in tc_set_edp_video_mode()
1053 ret = regmap_write(tc->regmap, DP0_MISC, in tc_set_edp_video_mode()
1068 dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n"); in tc_wait_link_training()
1072 ret = regmap_read(tc->regmap, DP0_LTSTAT, &value); in tc_wait_link_training()
1081 struct drm_dp_aux *aux = &tc->aux; in tc_main_link_enable()
1082 struct device *dev = tc->dev; in tc_main_link_enable()
1088 dev_dbg(tc->dev, "link enable\n"); in tc_main_link_enable()
1090 ret = regmap_read(tc->regmap, DP0CTL, &value); in tc_main_link_enable()
1095 ret = regmap_write(tc->regmap, DP0CTL, 0); in tc_main_link_enable()
1100 ret = regmap_write(tc->regmap, DP0_SRCCTRL, in tc_main_link_enable()
1102 FIELD_PREP(DP0_SRCCTRL_PRE0, tc->pre_emphasis[0]) | in tc_main_link_enable()
1103 FIELD_PREP(DP0_SRCCTRL_PRE1, tc->pre_emphasis[1])); in tc_main_link_enable()
1107 ret = regmap_write(tc->regmap, DP1_SRCCTRL, in tc_main_link_enable()
1108 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) | in tc_main_link_enable()
1109 ((tc->link.rate != 162000) ? DP0_SRCCTRL_BW27 : 0) | in tc_main_link_enable()
1110 FIELD_PREP(DP1_SRCCTRL_PRE, tc->pre_emphasis[1])); in tc_main_link_enable()
1120 if (tc->link.num_lanes == 2) in tc_main_link_enable()
1123 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); in tc_main_link_enable()
1138 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); in tc_main_link_enable()
1141 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); in tc_main_link_enable()
1150 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8); in tc_main_link_enable()
1161 if (tc->assr != tc->link.assr) { in tc_main_link_enable()
1163 tc->assr); in tc_main_link_enable()
1165 tmp[0] = tc->assr; in tc_main_link_enable()
1174 if (tmp[0] != tc->assr) { in tc_main_link_enable()
1176 tc->assr); in tc_main_link_enable()
1178 tc->link.scrambler_dis = true; in tc_main_link_enable()
1183 tmp[0] = drm_dp_link_rate_to_bw_code(tc->link.rate); in tc_main_link_enable()
1184 tmp[1] = tc->link.num_lanes; in tc_main_link_enable()
1186 if (drm_dp_enhanced_frame_cap(tc->link.dpcd)) in tc_main_link_enable()
1194 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00; in tc_main_link_enable()
1201 /* Reset voltage-swing & pre-emphasis */ in tc_main_link_enable()
1203 FIELD_PREP(DP_TRAIN_PRE_EMPHASIS_MASK, tc->pre_emphasis[0]); in tc_main_link_enable()
1205 FIELD_PREP(DP_TRAIN_PRE_EMPHASIS_MASK, tc->pre_emphasis[1]); in tc_main_link_enable()
1210 /* Clock-Recovery */ in tc_main_link_enable()
1213 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL, in tc_main_link_enable()
1219 ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL, in tc_main_link_enable()
1226 ret = regmap_write(tc->regmap, DP0_SRCCTRL, in tc_main_link_enable()
1230 FIELD_PREP(DP0_SRCCTRL_PRE0, tc->pre_emphasis[0]) | in tc_main_link_enable()
1231 FIELD_PREP(DP0_SRCCTRL_PRE1, tc->pre_emphasis[1])); in tc_main_link_enable()
1236 ret = regmap_write(tc->regmap, DP0CTL, in tc_main_link_enable()
1237 (drm_dp_enhanced_frame_cap(tc->link.dpcd) ? in tc_main_link_enable()
1249 dev_err(tc->dev, "Link training phase 1 failed: %s\n", in tc_main_link_enable()
1251 return -ENODEV; in tc_main_link_enable()
1257 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL, in tc_main_link_enable()
1263 ret = regmap_write(tc->regmap, DP0_SRCCTRL, in tc_main_link_enable()
1267 FIELD_PREP(DP0_SRCCTRL_PRE0, tc->pre_emphasis[0]) | in tc_main_link_enable()
1268 FIELD_PREP(DP0_SRCCTRL_PRE1, tc->pre_emphasis[1])); in tc_main_link_enable()
1278 dev_err(tc->dev, "Link training phase 2 failed: %s\n", in tc_main_link_enable()
1280 return -ENODEV; in tc_main_link_enable()
1293 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) | in tc_main_link_enable()
1295 FIELD_PREP(DP0_SRCCTRL_PRE0, tc->pre_emphasis[0]) | in tc_main_link_enable()
1296 FIELD_PREP(DP0_SRCCTRL_PRE1, tc->pre_emphasis[1])); in tc_main_link_enable()
1302 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00; in tc_main_link_enable()
1317 dev_err(tc->dev, "Lane 0 failed: %x\n", value); in tc_main_link_enable()
1318 ret = -ENODEV; in tc_main_link_enable()
1321 if (tc->link.num_lanes == 2) { in tc_main_link_enable()
1325 dev_err(tc->dev, "Lane 1 failed: %x\n", value); in tc_main_link_enable()
1326 ret = -ENODEV; in tc_main_link_enable()
1330 dev_err(tc->dev, "Interlane align failed\n"); in tc_main_link_enable()
1331 ret = -ENODEV; in tc_main_link_enable()
1347 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret); in tc_main_link_enable()
1350 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret); in tc_main_link_enable()
1358 dev_dbg(tc->dev, "link disable\n"); in tc_main_link_disable()
1360 ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0); in tc_main_link_disable()
1364 ret = regmap_write(tc->regmap, DP0CTL, 0); in tc_main_link_disable()
1368 return regmap_update_bits(tc->regmap, DP_PHY_CTRL, in tc_main_link_disable()
1378 regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 5); in tc_dsi_rx_enable()
1379 regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 5); in tc_dsi_rx_enable()
1380 regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 5); in tc_dsi_rx_enable()
1381 regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 5); in tc_dsi_rx_enable()
1382 regmap_write(tc->regmap, PPI_D0S_ATMR, 0); in tc_dsi_rx_enable()
1383 regmap_write(tc->regmap, PPI_D1S_ATMR, 0); in tc_dsi_rx_enable()
1384 regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE); in tc_dsi_rx_enable()
1385 regmap_write(tc->regmap, PPI_LPTXTIMECNT, LPX_PERIOD); in tc_dsi_rx_enable()
1387 value = ((LANEENABLE_L0EN << tc->dsi->lanes) - LANEENABLE_L0EN) | in tc_dsi_rx_enable()
1389 regmap_write(tc->regmap, PPI_LANEENABLE, value); in tc_dsi_rx_enable()
1390 regmap_write(tc->regmap, DSI_LANEENABLE, value); in tc_dsi_rx_enable()
1398 ret = regmap_write(tc->regmap, SYSCTRL, value); in tc_dsi_rx_enable()
1404 regmap_write(tc->regmap, PPI_STARTPPI, PPI_START_FUNCTION); in tc_dsi_rx_enable()
1405 regmap_write(tc->regmap, DSI_STARTDSI, DSI_RX_START); in tc_dsi_rx_enable()
1420 return regmap_write(tc->regmap, SYSCTRL, value); in tc_dpi_rx_enable()
1427 dev_dbg(tc->dev, "enable video stream\n"); in tc_dpi_stream_enable()
1447 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk), in tc_dpi_stream_enable()
1448 1000 * tc->mode.clock); in tc_dpi_stream_enable()
1452 ret = tc_set_common_video_mode(tc, &tc->mode); in tc_dpi_stream_enable()
1456 ret = tc_set_dpi_video_mode(tc, &tc->mode); in tc_dpi_stream_enable()
1465 dev_dbg(tc->dev, "disable video stream\n"); in tc_dpi_stream_disable()
1477 dev_dbg(tc->dev, "enable video stream\n"); in tc_edp_stream_enable()
1482 * Per TC9595XBG datasheet Revision 0.1 2018-12-27 Figure 4.18 in tc_edp_stream_enable()
1486 * In case built-in test pattern is desired OR DSI input mode in tc_edp_stream_enable()
1490 if (tc->input_connector_dsi || tc_test_pattern) { in tc_edp_stream_enable()
1491 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk), in tc_edp_stream_enable()
1492 1000 * tc->mode.clock); in tc_edp_stream_enable()
1497 ret = tc_set_common_video_mode(tc, &tc->mode); in tc_edp_stream_enable()
1501 ret = tc_set_edp_video_mode(tc, &tc->mode); in tc_edp_stream_enable()
1511 if (drm_dp_enhanced_frame_cap(tc->link.dpcd)) in tc_edp_stream_enable()
1513 ret = regmap_write(tc->regmap, DP0CTL, value); in tc_edp_stream_enable()
1525 ret = regmap_write(tc->regmap, DP0CTL, value); in tc_edp_stream_enable()
1530 if (tc->input_connector_dsi) in tc_edp_stream_enable()
1540 dev_dbg(tc->dev, "disable video stream\n"); in tc_edp_stream_disable()
1542 ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0); in tc_edp_stream_disable()
1561 dev_err(tc->dev, "main link stream start error: %d\n", ret); in tc_dpi_bridge_atomic_enable()
1576 dev_err(tc->dev, "main link stream stop error: %d\n", ret); in tc_dpi_bridge_atomic_disable()
1588 dev_err(tc->dev, "failed to read display props: %d\n", ret); in tc_edp_bridge_atomic_enable()
1594 dev_err(tc->dev, "main link enable error: %d\n", ret); in tc_edp_bridge_atomic_enable()
1600 dev_err(tc->dev, "main link stream start error: %d\n", ret); in tc_edp_bridge_atomic_enable()
1615 dev_err(tc->dev, "main link stream stop error: %d\n", ret); in tc_edp_bridge_atomic_disable()
1619 dev_err(tc->dev, "main link disable error: %d\n", ret); in tc_edp_bridge_atomic_disable()
1631 ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk), in tc_dpi_atomic_check()
1632 crtc_state->mode.clock * 1000, in tc_dpi_atomic_check()
1637 crtc_state->adjusted_mode.clock = adjusted_clock / 1000; in tc_dpi_atomic_check()
1639 /* DSI->DPI interface clock limitation: upto 100 MHz */ in tc_dpi_atomic_check()
1640 if (crtc_state->adjusted_mode.clock > 100000) in tc_dpi_atomic_check()
1641 return -EINVAL; in tc_dpi_atomic_check()
1655 ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk), in tc_edp_atomic_check()
1656 crtc_state->mode.clock * 1000, in tc_edp_atomic_check()
1661 crtc_state->adjusted_mode.clock = adjusted_clock / 1000; in tc_edp_atomic_check()
1663 /* DPI->(e)DP interface clock limitation: upto 154 MHz */ in tc_edp_atomic_check()
1664 if (crtc_state->adjusted_mode.clock > 154000) in tc_edp_atomic_check()
1665 return -EINVAL; in tc_edp_atomic_check()
1676 if (mode->clock > 100000) in tc_dpi_mode_valid()
1691 /* DPI->(e)DP interface clock limitation: up to 154 MHz */ in tc_edp_mode_valid()
1692 if (mode->clock > 154000) in tc_edp_mode_valid()
1695 req = mode->clock * bits_per_pixel / 8; in tc_edp_mode_valid()
1696 avail = tc->link.num_lanes * tc->link.rate; in tc_edp_mode_valid()
1710 drm_mode_copy(&tc->mode, adj); in tc_bridge_mode_set()
1721 dev_err(tc->dev, "failed to read display props: %d\n", ret); in tc_edid_read()
1725 return drm_edid_read_ddc(connector, &tc->aux.ddc); in tc_edid_read()
1737 dev_err(tc->dev, "failed to read display props: %d\n", ret); in tc_connector_get_modes()
1741 if (tc->panel_bridge) { in tc_connector_get_modes()
1742 num_modes = drm_bridge_get_modes(tc->panel_bridge, connector); in tc_connector_get_modes()
1747 drm_edid = tc_edid_read(&tc->bridge, connector); in tc_connector_get_modes()
1766 ret = regmap_read(tc->regmap, GPIOI, &val); in tc_bridge_detect()
1770 conn = val & BIT(tc->hpd_pin); in tc_bridge_detect()
1783 if (tc->hpd_pin >= 0) in tc_connector_detect()
1784 return tc_bridge_detect(&tc->bridge); in tc_connector_detect()
1786 if (tc->panel_bridge) in tc_connector_detect()
1806 if (!tc->panel_bridge) in tc_dpi_bridge_attach()
1809 return drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge, in tc_dpi_bridge_attach()
1810 &tc->bridge, flags); in tc_dpi_bridge_attach()
1818 struct drm_device *drm = bridge->dev; in tc_edp_bridge_attach()
1821 if (tc->panel_bridge) { in tc_edp_bridge_attach()
1823 ret = drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge, in tc_edp_bridge_attach()
1824 &tc->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR); in tc_edp_bridge_attach()
1832 tc->aux.drm_dev = drm; in tc_edp_bridge_attach()
1833 ret = drm_dp_aux_register(&tc->aux); in tc_edp_bridge_attach()
1838 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs); in tc_edp_bridge_attach()
1839 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, tc->bridge.type); in tc_edp_bridge_attach()
1844 if (tc->hpd_pin >= 0) { in tc_edp_bridge_attach()
1845 if (tc->have_irq) in tc_edp_bridge_attach()
1846 tc->connector.polled = DRM_CONNECTOR_POLL_HPD; in tc_edp_bridge_attach()
1848 tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT | in tc_edp_bridge_attach()
1852 drm_display_info_set_bus_formats(&tc->connector.display_info, in tc_edp_bridge_attach()
1854 tc->connector.display_info.bus_flags = in tc_edp_bridge_attach()
1858 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder); in tc_edp_bridge_attach()
1862 drm_dp_aux_unregister(&tc->aux); in tc_edp_bridge_attach()
1868 drm_dp_aux_unregister(&bridge_to_tc(bridge)->aux); in tc_edp_bridge_detach()
1891 /* This is the DSI-end bus format */ in tc_dpi_atomic_get_input_bus_fmts()
1953 /* DSI D-PHY Layer */ in tc_readable_reg()
2107 /* I2S */ in tc_readable_reg()
2226 r = regmap_read(tc->regmap, INTSTS_G, &val); in tc_irq_handler()
2236 regmap_read(tc->regmap, SYSSTAT, &stat); in tc_irq_handler()
2238 dev_err(tc->dev, "syserr %x\n", stat); in tc_irq_handler()
2241 if (tc->hpd_pin >= 0 && tc->bridge.dev && tc->aux.drm_dev) { in tc_irq_handler()
2248 bool h = val & INT_GPIO_H(tc->hpd_pin); in tc_irq_handler()
2249 bool lc = val & INT_GPIO_LC(tc->hpd_pin); in tc_irq_handler()
2252 dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin, in tc_irq_handler()
2254 drm_kms_helper_hotplug_event(tc->bridge.dev); in tc_irq_handler()
2258 regmap_write(tc->regmap, INTSTS_G, val); in tc_irq_handler()
2265 struct device *dev = tc->dev; in tc_mipi_dsi_host_attach()
2277 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1); in tc_mipi_dsi_host_attach()
2285 return -EPROBE_DEFER; in tc_mipi_dsi_host_attach()
2295 tc->dsi = dsi; in tc_mipi_dsi_host_attach()
2296 dsi->lanes = dsi_lanes; in tc_mipi_dsi_host_attach()
2297 dsi->format = MIPI_DSI_FMT_RGB888; in tc_mipi_dsi_host_attach()
2298 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | in tc_mipi_dsi_host_attach()
2312 struct device *dev = tc->dev; in tc_probe_dpi_bridge_endpoint()
2318 ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, &bridge); in tc_probe_dpi_bridge_endpoint()
2319 if (ret && ret != -ENODEV) in tc_probe_dpi_bridge_endpoint()
2330 tc->panel_bridge = bridge; in tc_probe_dpi_bridge_endpoint()
2331 tc->bridge.type = DRM_MODE_CONNECTOR_DPI; in tc_probe_dpi_bridge_endpoint()
2332 tc->bridge.funcs = &tc_dpi_bridge_funcs; in tc_probe_dpi_bridge_endpoint()
2342 struct device *dev = tc->dev; in tc_probe_edp_bridge_endpoint()
2347 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &panel, NULL); in tc_probe_edp_bridge_endpoint()
2348 if (ret && ret != -ENODEV) in tc_probe_edp_bridge_endpoint()
2359 tc->panel_bridge = panel_bridge; in tc_probe_edp_bridge_endpoint()
2360 tc->bridge.type = DRM_MODE_CONNECTOR_eDP; in tc_probe_edp_bridge_endpoint()
2362 tc->bridge.type = DRM_MODE_CONNECTOR_DisplayPort; in tc_probe_edp_bridge_endpoint()
2365 tc->bridge.funcs = &tc_edp_bridge_funcs; in tc_probe_edp_bridge_endpoint()
2366 if (tc->hpd_pin >= 0) in tc_probe_edp_bridge_endpoint()
2367 tc->bridge.ops |= DRM_BRIDGE_OP_DETECT; in tc_probe_edp_bridge_endpoint()
2368 tc->bridge.ops |= DRM_BRIDGE_OP_EDID; in tc_probe_edp_bridge_endpoint()
2375 struct device *dev = tc->dev; in tc_probe_bridge_endpoint()
2389 * port@0 - DSI input in tc_probe_bridge_endpoint()
2390 * port@1 - DPI input/output in tc_probe_bridge_endpoint()
2391 * port@2 - eDP output in tc_probe_bridge_endpoint()
2394 * DPI -> port@1 -> port@2 -> eDP :: [port@0 is not connected] in tc_probe_bridge_endpoint()
2395 * DSI -> port@0 -> port@2 -> eDP :: [port@1 is not connected] in tc_probe_bridge_endpoint()
2396 * DSI -> port@0 -> port@1 -> DPI :: [port@2 is not connected] in tc_probe_bridge_endpoint()
2399 for_each_endpoint_of_node(dev->of_node, node) { in tc_probe_bridge_endpoint()
2403 return -EINVAL; in tc_probe_bridge_endpoint()
2408 of_property_read_u8_array(node, "toshiba,pre-emphasis", in tc_probe_bridge_endpoint()
2409 tc->pre_emphasis, in tc_probe_bridge_endpoint()
2410 ARRAY_SIZE(tc->pre_emphasis)); in tc_probe_bridge_endpoint()
2412 if (tc->pre_emphasis[0] < 0 || tc->pre_emphasis[0] > 2 || in tc_probe_bridge_endpoint()
2413 tc->pre_emphasis[1] < 0 || tc->pre_emphasis[1] > 2) { in tc_probe_bridge_endpoint()
2414 dev_err(dev, "Incorrect Pre-Emphasis setting, use either 0=0dB 1=3.5dB 2=6dB\n"); in tc_probe_bridge_endpoint()
2416 return -EINVAL; in tc_probe_bridge_endpoint()
2422 tc->input_connector_dsi = false; in tc_probe_bridge_endpoint()
2425 tc->input_connector_dsi = true; in tc_probe_bridge_endpoint()
2428 tc->input_connector_dsi = true; in tc_probe_bridge_endpoint()
2434 return -EINVAL; in tc_probe_bridge_endpoint()
2439 struct device *dev = &client->dev; in tc_probe()
2445 return -ENOMEM; in tc_probe()
2447 tc->dev = dev; in tc_probe()
2453 tc->refclk = devm_clk_get_enabled(dev, "ref"); in tc_probe()
2454 if (IS_ERR(tc->refclk)) in tc_probe()
2455 return dev_err_probe(dev, PTR_ERR(tc->refclk), in tc_probe()
2462 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH); in tc_probe()
2463 if (IS_ERR(tc->sd_gpio)) in tc_probe()
2464 return PTR_ERR(tc->sd_gpio); in tc_probe()
2466 if (tc->sd_gpio) { in tc_probe()
2467 gpiod_set_value_cansleep(tc->sd_gpio, 0); in tc_probe()
2472 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); in tc_probe()
2473 if (IS_ERR(tc->reset_gpio)) in tc_probe()
2474 return PTR_ERR(tc->reset_gpio); in tc_probe()
2476 if (tc->reset_gpio) { in tc_probe()
2477 gpiod_set_value_cansleep(tc->reset_gpio, 1); in tc_probe()
2481 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config); in tc_probe()
2482 if (IS_ERR(tc->regmap)) { in tc_probe()
2483 ret = PTR_ERR(tc->regmap); in tc_probe()
2488 ret = of_property_read_u32(dev->of_node, "toshiba,hpd-pin", in tc_probe()
2489 &tc->hpd_pin); in tc_probe()
2491 tc->hpd_pin = -ENODEV; in tc_probe()
2493 if (tc->hpd_pin < 0 || tc->hpd_pin > 1) { in tc_probe()
2495 return -EINVAL; in tc_probe()
2499 if (client->irq > 0) { in tc_probe()
2501 regmap_write(tc->regmap, INTCTL_G, INT_SYSERR); in tc_probe()
2503 ret = devm_request_threaded_irq(dev, client->irq, in tc_probe()
2506 "tc358767-irq", tc); in tc_probe()
2512 tc->have_irq = true; in tc_probe()
2515 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev); in tc_probe()
2517 dev_err(tc->dev, "can not read device ID: %d\n", ret); in tc_probe()
2521 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) { in tc_probe()
2522 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev); in tc_probe()
2523 return -EINVAL; in tc_probe()
2526 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */ in tc_probe()
2528 if (!tc->reset_gpio) { in tc_probe()
2535 regmap_update_bits(tc->regmap, SYSRSTENB, in tc_probe()
2538 regmap_update_bits(tc->regmap, SYSRSTENB, in tc_probe()
2544 if (tc->hpd_pin >= 0) { in tc_probe()
2545 u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT; in tc_probe()
2546 u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin); in tc_probe()
2549 regmap_write(tc->regmap, lcnt_reg, in tc_probe()
2550 clk_get_rate(tc->refclk) * 2 / 1000); in tc_probe()
2552 regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin)); in tc_probe()
2554 if (tc->have_irq) { in tc_probe()
2556 regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc); in tc_probe()
2560 if (tc->bridge.type != DRM_MODE_CONNECTOR_DPI) { /* (e)DP output */ in tc_probe()
2566 tc->bridge.of_node = dev->of_node; in tc_probe()
2567 drm_bridge_add(&tc->bridge); in tc_probe()
2571 if (tc->input_connector_dsi) { /* DSI input */ in tc_probe()
2574 drm_bridge_remove(&tc->bridge); in tc_probe()
2586 drm_bridge_remove(&tc->bridge); in tc_remove()