Lines Matching +full:bridge +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TC358767/TC358867/TC9595 DSI/DPI-to-DPI/(e)DP bridge driver
6 * All modes are supported -- DPI->(e)DP / DSI->DPI / DSI->(e)DP .
27 #include <linux/media-bus-format.h>
44 /* DSI D-PHY Layer registers */
77 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
82 /* Lane enable PPI and DSI register bits */
110 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
151 #define SYSRSTENB 0x050c /* System Reset/Enable Register */
184 #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
185 #define EF_EN BIT(5) /* Enable Enhanced Framing */
186 #define VID_EN BIT(1) /* Video transmission enable */
187 #define DP_EN BIT(0) /* Enable DPTX function */
291 #define BGREN BIT(25) /* AUX PHY BGR Enable */
292 #define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */
296 #define PHY_2LANE BIT(2) /* PHY Enable 2 lanes */
297 #define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */
298 #define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */
372 struct drm_bridge bridge; member
398 /* HPD pin number (0 or 1) or -ENODEV */
409 return container_of(b, struct tc_data, bridge); in bridge_to_tc()
424 return regmap_read_poll_timeout(tc->regmap, addr, val, in tc_poll_timeout()
442 ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count); in tc_aux_write_data()
454 ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count); in tc_aux_read_data()
465 u32 auxcfg0 = msg->request; in tc_auxcfg0()
468 auxcfg0 |= FIELD_PREP(DP0_AUXCFG0_BSIZE, size - 1); in tc_auxcfg0()
479 size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size); in tc_aux_transfer()
480 u8 request = msg->request & ~DP_AUX_I2C_MOT; in tc_aux_transfer()
495 ret = tc_aux_write_data(tc, msg->buffer, size); in tc_aux_transfer()
501 return -EINVAL; in tc_aux_transfer()
505 ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address); in tc_aux_transfer()
509 ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size)); in tc_aux_transfer()
517 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus); in tc_aux_transfer()
522 return -ETIMEDOUT; in tc_aux_transfer()
524 * For some reason address-only DP_AUX_I2C_WRITE (MOT), still in tc_aux_transfer()
527 * address-only transfer in tc_aux_transfer()
531 msg->reply = FIELD_GET(AUX_STATUS, auxstatus); in tc_aux_transfer()
537 return tc_aux_read_data(tc, msg->buffer, size); in tc_aux_transfer()
570 if (tc->link.scrambler_dis) in tc_srcctrl()
572 if (tc->link.spread) in tc_srcctrl()
573 reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */ in tc_srcctrl()
574 if (tc->link.num_lanes == 2) in tc_srcctrl()
576 if (tc->link.rate != 162000) in tc_srcctrl()
585 ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN); in tc_pllupdate()
611 * - DPI ..... 0 to 100 MHz in tc_pxl_pll_calc()
612 * - (e)DP ... 150 to 650 MHz in tc_pxl_pll_calc()
614 if (tc->bridge.type == DRM_MODE_CONNECTOR_DPI) { in tc_pxl_pll_calc()
622 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock, in tc_pxl_pll_calc()
657 delta = clk - pixelclock; in tc_pxl_pll_calc()
671 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n", in tc_pxl_pll_calc()
673 return -EINVAL; in tc_pxl_pll_calc()
676 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock, best_delta); in tc_pxl_pll_calc()
677 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk, in tc_pxl_pll_calc()
690 pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */ in tc_pxl_pll_calc()
691 pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */ in tc_pxl_pll_calc()
715 ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN); in tc_pxl_pll_en()
719 ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam); in tc_pxl_pll_en()
729 /* Enable PLL bypass, power down PLL */ in tc_pxl_pll_dis()
730 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP); in tc_pxl_pll_dis()
750 return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768); in tc_stream_clock_calc()
758 rate = clk_get_rate(tc->refclk); in tc_set_syspllparam()
773 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate); in tc_set_syspllparam()
774 return -EINVAL; in tc_set_syspllparam()
777 return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam); in tc_set_syspllparam()
785 /* Setup DP-PHY / PLL */ in tc_aux_link_setup()
790 ret = regmap_write(tc->regmap, DP_PHY_CTRL, in tc_aux_link_setup()
796 * disable PLL bypass, enable PLL in tc_aux_link_setup()
807 if (ret == -ETIMEDOUT) { in tc_aux_link_setup()
808 dev_err(tc->dev, "Timeout waiting for PHY to become ready"); in tc_aux_link_setup()
819 ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1); in tc_aux_link_setup()
824 tc->aux.name = "TC358767 AUX i2c adapter"; in tc_aux_link_setup()
825 tc->aux.dev = tc->dev; in tc_aux_link_setup()
826 tc->aux.transfer = tc_aux_transfer; in tc_aux_link_setup()
827 drm_dp_aux_init(&tc->aux); in tc_aux_link_setup()
831 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret); in tc_aux_link_setup()
843 ret = drm_dp_dpcd_read(&tc->aux, DP_DPCD_REV, tc->link.dpcd, in tc_get_display_props()
848 revision = tc->link.dpcd[DP_DPCD_REV]; in tc_get_display_props()
849 rate = drm_dp_max_link_rate(tc->link.dpcd); in tc_get_display_props()
850 num_lanes = drm_dp_max_lane_count(tc->link.dpcd); in tc_get_display_props()
853 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n"); in tc_get_display_props()
857 tc->link.rate = rate; in tc_get_display_props()
860 dev_dbg(tc->dev, "Falling to 2 lanes\n"); in tc_get_display_props()
864 tc->link.num_lanes = num_lanes; in tc_get_display_props()
866 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, ®); in tc_get_display_props()
869 tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5; in tc_get_display_props()
871 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, ®); in tc_get_display_props()
875 tc->link.scrambler_dis = false; in tc_get_display_props()
877 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, ®); in tc_get_display_props()
880 tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; in tc_get_display_props()
882 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n", in tc_get_display_props()
884 (tc->link.rate == 162000) ? "1.62Gbps" : "2.7Gbps", in tc_get_display_props()
885 tc->link.num_lanes, in tc_get_display_props()
886 drm_dp_enhanced_frame_cap(tc->link.dpcd) ? in tc_get_display_props()
888 dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n", in tc_get_display_props()
889 tc->link.spread ? "0.5%" : "0.0%", in tc_get_display_props()
890 tc->link.scrambler_dis ? "disabled" : "enabled"); in tc_get_display_props()
891 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n", in tc_get_display_props()
892 tc->link.assr, tc->assr); in tc_get_display_props()
897 dev_err(tc->dev, "failed to read DPCD: %d\n", ret); in tc_get_display_props()
904 int left_margin = mode->htotal - mode->hsync_end; in tc_set_common_video_mode()
905 int right_margin = mode->hsync_start - mode->hdisplay; in tc_set_common_video_mode()
906 int hsync_len = mode->hsync_end - mode->hsync_start; in tc_set_common_video_mode()
907 int upper_margin = mode->vtotal - mode->vsync_end; in tc_set_common_video_mode()
908 int lower_margin = mode->vsync_start - mode->vdisplay; in tc_set_common_video_mode()
909 int vsync_len = mode->vsync_end - mode->vsync_start; in tc_set_common_video_mode()
912 dev_dbg(tc->dev, "set mode %dx%d\n", in tc_set_common_video_mode()
913 mode->hdisplay, mode->vdisplay); in tc_set_common_video_mode()
914 dev_dbg(tc->dev, "H margin %d,%d sync %d\n", in tc_set_common_video_mode()
916 dev_dbg(tc->dev, "V margin %d,%d sync %d\n", in tc_set_common_video_mode()
918 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal); in tc_set_common_video_mode()
926 ret = regmap_write(tc->regmap, VPCTRL0, in tc_set_common_video_mode()
932 ret = regmap_write(tc->regmap, HTIM01, in tc_set_common_video_mode()
938 ret = regmap_write(tc->regmap, HTIM02, in tc_set_common_video_mode()
939 FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) | in tc_set_common_video_mode()
944 ret = regmap_write(tc->regmap, VTIM01, in tc_set_common_video_mode()
950 ret = regmap_write(tc->regmap, VTIM02, in tc_set_common_video_mode()
952 FIELD_PREP(VDISPR, mode->vdisplay)); in tc_set_common_video_mode()
956 ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */ in tc_set_common_video_mode()
961 ret = regmap_write(tc->regmap, TSTCTL, in tc_set_common_video_mode()
976 if (tc->mode.flags & DRM_MODE_FLAG_NHSYNC) in tc_set_dpi_video_mode()
979 if (tc->mode.flags & DRM_MODE_FLAG_NVSYNC) in tc_set_dpi_video_mode()
982 return regmap_write(tc->regmap, POCTRL, value); in tc_set_dpi_video_mode()
992 int left_margin = mode->htotal - mode->hsync_end; in tc_set_edp_video_mode()
993 int hsync_len = mode->hsync_end - mode->hsync_start; in tc_set_edp_video_mode()
994 int upper_margin = mode->vtotal - mode->vsync_end; in tc_set_edp_video_mode()
995 int vsync_len = mode->vsync_end - mode->vsync_start; in tc_set_edp_video_mode()
1008 in_bw = mode->clock * bits_per_pixel / 8; in tc_set_edp_video_mode()
1009 out_bw = tc->link.num_lanes * tc->link.rate; in tc_set_edp_video_mode()
1013 vid_sync_dly = hsync_len + left_margin + mode->hdisplay; in tc_set_edp_video_mode()
1014 ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY, in tc_set_edp_video_mode()
1018 ret = regmap_write(tc->regmap, DP0_TOTALVAL, in tc_set_edp_video_mode()
1019 FIELD_PREP(H_TOTAL, mode->htotal) | in tc_set_edp_video_mode()
1020 FIELD_PREP(V_TOTAL, mode->vtotal)); in tc_set_edp_video_mode()
1024 ret = regmap_write(tc->regmap, DP0_STARTVAL, in tc_set_edp_video_mode()
1030 ret = regmap_write(tc->regmap, DP0_ACTIVEVAL, in tc_set_edp_video_mode()
1031 FIELD_PREP(V_ACT, mode->vdisplay) | in tc_set_edp_video_mode()
1032 FIELD_PREP(H_ACT, mode->hdisplay)); in tc_set_edp_video_mode()
1039 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in tc_set_edp_video_mode()
1042 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in tc_set_edp_video_mode()
1045 ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval); in tc_set_edp_video_mode()
1051 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in tc_set_edp_video_mode()
1054 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in tc_set_edp_video_mode()
1057 ret = regmap_write(tc->regmap, DPIPXLFMT, dpipxlfmt); in tc_set_edp_video_mode()
1061 ret = regmap_write(tc->regmap, DP0_MISC, in tc_set_edp_video_mode()
1076 dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n"); in tc_wait_link_training()
1080 ret = regmap_read(tc->regmap, DP0_LTSTAT, &value); in tc_wait_link_training()
1089 struct drm_dp_aux *aux = &tc->aux; in tc_main_link_enable()
1090 struct device *dev = tc->dev; in tc_main_link_enable()
1096 dev_dbg(tc->dev, "link enable\n"); in tc_main_link_enable()
1098 ret = regmap_read(tc->regmap, DP0CTL, &value); in tc_main_link_enable()
1103 ret = regmap_write(tc->regmap, DP0CTL, 0); in tc_main_link_enable()
1108 ret = regmap_write(tc->regmap, DP0_SRCCTRL, in tc_main_link_enable()
1110 FIELD_PREP(DP0_SRCCTRL_PRE0, tc->pre_emphasis[0]) | in tc_main_link_enable()
1111 FIELD_PREP(DP0_SRCCTRL_PRE1, tc->pre_emphasis[1])); in tc_main_link_enable()
1115 ret = regmap_write(tc->regmap, DP1_SRCCTRL, in tc_main_link_enable()
1116 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) | in tc_main_link_enable()
1117 ((tc->link.rate != 162000) ? DP0_SRCCTRL_BW27 : 0) | in tc_main_link_enable()
1118 FIELD_PREP(DP1_SRCCTRL_PRE, tc->pre_emphasis[1])); in tc_main_link_enable()
1128 if (tc->link.num_lanes == 2) in tc_main_link_enable()
1131 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); in tc_main_link_enable()
1144 /* Reset/Enable Main Links */ in tc_main_link_enable()
1146 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); in tc_main_link_enable()
1149 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); in tc_main_link_enable()
1158 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8); in tc_main_link_enable()
1169 if (tc->assr != tc->link.assr) { in tc_main_link_enable()
1171 tc->assr); in tc_main_link_enable()
1173 tmp[0] = tc->assr; in tc_main_link_enable()
1182 if (tmp[0] != tc->assr) { in tc_main_link_enable()
1184 tc->assr); in tc_main_link_enable()
1186 tc->link.scrambler_dis = true; in tc_main_link_enable()
1191 tmp[0] = drm_dp_link_rate_to_bw_code(tc->link.rate); in tc_main_link_enable()
1192 tmp[1] = tc->link.num_lanes; in tc_main_link_enable()
1194 if (drm_dp_enhanced_frame_cap(tc->link.dpcd)) in tc_main_link_enable()
1202 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00; in tc_main_link_enable()
1209 /* Reset voltage-swing & pre-emphasis */ in tc_main_link_enable()
1211 FIELD_PREP(DP_TRAIN_PRE_EMPHASIS_MASK, tc->pre_emphasis[0]); in tc_main_link_enable()
1213 FIELD_PREP(DP_TRAIN_PRE_EMPHASIS_MASK, tc->pre_emphasis[1]); in tc_main_link_enable()
1218 /* Clock-Recovery */ in tc_main_link_enable()
1221 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL, in tc_main_link_enable()
1227 ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL, in tc_main_link_enable()
1234 ret = regmap_write(tc->regmap, DP0_SRCCTRL, in tc_main_link_enable()
1238 FIELD_PREP(DP0_SRCCTRL_PRE0, tc->pre_emphasis[0]) | in tc_main_link_enable()
1239 FIELD_PREP(DP0_SRCCTRL_PRE1, tc->pre_emphasis[1])); in tc_main_link_enable()
1243 /* Enable DP0 to start Link Training */ in tc_main_link_enable()
1244 ret = regmap_write(tc->regmap, DP0CTL, in tc_main_link_enable()
1245 (drm_dp_enhanced_frame_cap(tc->link.dpcd) ? in tc_main_link_enable()
1257 dev_err(tc->dev, "Link training phase 1 failed: %s\n", in tc_main_link_enable()
1259 return -ENODEV; in tc_main_link_enable()
1265 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL, in tc_main_link_enable()
1271 ret = regmap_write(tc->regmap, DP0_SRCCTRL, in tc_main_link_enable()
1275 FIELD_PREP(DP0_SRCCTRL_PRE0, tc->pre_emphasis[0]) | in tc_main_link_enable()
1276 FIELD_PREP(DP0_SRCCTRL_PRE1, tc->pre_emphasis[1])); in tc_main_link_enable()
1286 dev_err(tc->dev, "Link training phase 2 failed: %s\n", in tc_main_link_enable()
1288 return -ENODEV; in tc_main_link_enable()
1301 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) | in tc_main_link_enable()
1303 FIELD_PREP(DP0_SRCCTRL_PRE0, tc->pre_emphasis[0]) | in tc_main_link_enable()
1304 FIELD_PREP(DP0_SRCCTRL_PRE1, tc->pre_emphasis[1])); in tc_main_link_enable()
1310 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00; in tc_main_link_enable()
1325 dev_err(tc->dev, "Lane 0 failed: %x\n", value); in tc_main_link_enable()
1326 ret = -ENODEV; in tc_main_link_enable()
1329 if (tc->link.num_lanes == 2) { in tc_main_link_enable()
1333 dev_err(tc->dev, "Lane 1 failed: %x\n", value); in tc_main_link_enable()
1334 ret = -ENODEV; in tc_main_link_enable()
1338 dev_err(tc->dev, "Interlane align failed\n"); in tc_main_link_enable()
1339 ret = -ENODEV; in tc_main_link_enable()
1355 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret); in tc_main_link_enable()
1358 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret); in tc_main_link_enable()
1366 dev_dbg(tc->dev, "link disable\n"); in tc_main_link_disable()
1368 ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0); in tc_main_link_disable()
1372 ret = regmap_write(tc->regmap, DP0CTL, 0); in tc_main_link_disable()
1376 return regmap_update_bits(tc->regmap, DP_PHY_CTRL, in tc_main_link_disable()
1386 regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 5); in tc_dsi_rx_enable()
1387 regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 5); in tc_dsi_rx_enable()
1388 regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 5); in tc_dsi_rx_enable()
1389 regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 5); in tc_dsi_rx_enable()
1390 regmap_write(tc->regmap, PPI_D0S_ATMR, 0); in tc_dsi_rx_enable()
1391 regmap_write(tc->regmap, PPI_D1S_ATMR, 0); in tc_dsi_rx_enable()
1392 regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE); in tc_dsi_rx_enable()
1393 regmap_write(tc->regmap, PPI_LPTXTIMECNT, LPX_PERIOD); in tc_dsi_rx_enable()
1395 value = ((LANEENABLE_L0EN << tc->dsi->lanes) - LANEENABLE_L0EN) | in tc_dsi_rx_enable()
1397 regmap_write(tc->regmap, PPI_LANEENABLE, value); in tc_dsi_rx_enable()
1398 regmap_write(tc->regmap, DSI_LANEENABLE, value); in tc_dsi_rx_enable()
1406 ret = regmap_write(tc->regmap, SYSCTRL, value); in tc_dsi_rx_enable()
1412 regmap_write(tc->regmap, PPI_STARTPPI, PPI_START_FUNCTION); in tc_dsi_rx_enable()
1413 regmap_write(tc->regmap, DSI_STARTDSI, DSI_RX_START); in tc_dsi_rx_enable()
1428 return regmap_write(tc->regmap, SYSCTRL, value); in tc_dpi_rx_enable()
1435 dev_dbg(tc->dev, "enable video stream\n"); in tc_dpi_stream_enable()
1444 * disable PLL bypass, enable PLL in tc_dpi_stream_enable()
1455 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk), in tc_dpi_stream_enable()
1456 1000 * tc->mode.clock); in tc_dpi_stream_enable()
1460 ret = tc_set_common_video_mode(tc, &tc->mode); in tc_dpi_stream_enable()
1464 ret = tc_set_dpi_video_mode(tc, &tc->mode); in tc_dpi_stream_enable()
1473 dev_dbg(tc->dev, "disable video stream\n"); in tc_dpi_stream_disable()
1485 dev_dbg(tc->dev, "enable video stream\n"); in tc_edp_stream_enable()
1490 * Per TC9595XBG datasheet Revision 0.1 2018-12-27 Figure 4.18 in tc_edp_stream_enable()
1494 * In case built-in test pattern is desired OR DSI input mode in tc_edp_stream_enable()
1498 if (tc->input_connector_dsi || tc_test_pattern) { in tc_edp_stream_enable()
1499 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk), in tc_edp_stream_enable()
1500 1000 * tc->mode.clock); in tc_edp_stream_enable()
1505 ret = tc_set_common_video_mode(tc, &tc->mode); in tc_edp_stream_enable()
1509 ret = tc_set_edp_video_mode(tc, &tc->mode); in tc_edp_stream_enable()
1519 if (drm_dp_enhanced_frame_cap(tc->link.dpcd)) in tc_edp_stream_enable()
1521 ret = regmap_write(tc->regmap, DP0CTL, value); in tc_edp_stream_enable()
1533 ret = regmap_write(tc->regmap, DP0CTL, value); in tc_edp_stream_enable()
1538 if (tc->input_connector_dsi) in tc_edp_stream_enable()
1548 dev_dbg(tc->dev, "disable video stream\n"); in tc_edp_stream_disable()
1550 ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0); in tc_edp_stream_disable()
1559 static void tc_dpi_bridge_atomic_enable(struct drm_bridge *bridge, in tc_dpi_bridge_atomic_enable() argument
1563 struct tc_data *tc = bridge_to_tc(bridge); in tc_dpi_bridge_atomic_enable()
1568 dev_err(tc->dev, "main link stream start error: %d\n", ret); in tc_dpi_bridge_atomic_enable()
1574 static void tc_dpi_bridge_atomic_disable(struct drm_bridge *bridge, in tc_dpi_bridge_atomic_disable() argument
1577 struct tc_data *tc = bridge_to_tc(bridge); in tc_dpi_bridge_atomic_disable()
1582 dev_err(tc->dev, "main link stream stop error: %d\n", ret); in tc_dpi_bridge_atomic_disable()
1585 static void tc_edp_bridge_atomic_enable(struct drm_bridge *bridge, in tc_edp_bridge_atomic_enable() argument
1588 struct tc_data *tc = bridge_to_tc(bridge); in tc_edp_bridge_atomic_enable()
1593 dev_err(tc->dev, "failed to read display props: %d\n", ret); in tc_edp_bridge_atomic_enable()
1599 dev_err(tc->dev, "main link enable error: %d\n", ret); in tc_edp_bridge_atomic_enable()
1605 dev_err(tc->dev, "main link stream start error: %d\n", ret); in tc_edp_bridge_atomic_enable()
1611 static void tc_edp_bridge_atomic_disable(struct drm_bridge *bridge, in tc_edp_bridge_atomic_disable() argument
1614 struct tc_data *tc = bridge_to_tc(bridge); in tc_edp_bridge_atomic_disable()
1619 dev_err(tc->dev, "main link stream stop error: %d\n", ret); in tc_edp_bridge_atomic_disable()
1623 dev_err(tc->dev, "main link disable error: %d\n", ret); in tc_edp_bridge_atomic_disable()
1626 static int tc_dpi_atomic_check(struct drm_bridge *bridge, in tc_dpi_atomic_check() argument
1631 struct tc_data *tc = bridge_to_tc(bridge); in tc_dpi_atomic_check()
1635 ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk), in tc_dpi_atomic_check()
1636 crtc_state->mode.clock * 1000, in tc_dpi_atomic_check()
1641 crtc_state->adjusted_mode.clock = adjusted_clock / 1000; in tc_dpi_atomic_check()
1643 /* DSI->DPI interface clock limitation: upto 100 MHz */ in tc_dpi_atomic_check()
1644 if (crtc_state->adjusted_mode.clock > 100000) in tc_dpi_atomic_check()
1645 return -EINVAL; in tc_dpi_atomic_check()
1650 static int tc_edp_atomic_check(struct drm_bridge *bridge, in tc_edp_atomic_check() argument
1655 struct tc_data *tc = bridge_to_tc(bridge); in tc_edp_atomic_check()
1659 ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk), in tc_edp_atomic_check()
1660 crtc_state->mode.clock * 1000, in tc_edp_atomic_check()
1665 crtc_state->adjusted_mode.clock = adjusted_clock / 1000; in tc_edp_atomic_check()
1667 /* DPI->(e)DP interface clock limitation: upto 154 MHz */ in tc_edp_atomic_check()
1668 if (crtc_state->adjusted_mode.clock > 154000) in tc_edp_atomic_check()
1669 return -EINVAL; in tc_edp_atomic_check()
1675 tc_dpi_mode_valid(struct drm_bridge *bridge, in tc_dpi_mode_valid() argument
1680 if (mode->clock > 100000) in tc_dpi_mode_valid()
1687 tc_edp_mode_valid(struct drm_bridge *bridge, in tc_edp_mode_valid() argument
1691 struct tc_data *tc = bridge_to_tc(bridge); in tc_edp_mode_valid()
1695 /* DPI->(e)DP interface clock limitation: up to 154 MHz */ in tc_edp_mode_valid()
1696 if (mode->clock > 154000) in tc_edp_mode_valid()
1699 req = mode->clock * bits_per_pixel / 8; in tc_edp_mode_valid()
1700 avail = tc->link.num_lanes * tc->link.rate; in tc_edp_mode_valid()
1708 static void tc_bridge_mode_set(struct drm_bridge *bridge, in tc_bridge_mode_set() argument
1712 struct tc_data *tc = bridge_to_tc(bridge); in tc_bridge_mode_set()
1714 drm_mode_copy(&tc->mode, adj); in tc_bridge_mode_set()
1717 static const struct drm_edid *tc_edid_read(struct drm_bridge *bridge, in tc_edid_read() argument
1720 struct tc_data *tc = bridge_to_tc(bridge); in tc_edid_read()
1725 dev_err(tc->dev, "failed to read display props: %d\n", ret); in tc_edid_read()
1729 return drm_edid_read_ddc(connector, &tc->aux.ddc); in tc_edid_read()
1741 dev_err(tc->dev, "failed to read display props: %d\n", ret); in tc_connector_get_modes()
1745 if (tc->panel_bridge) { in tc_connector_get_modes()
1746 num_modes = drm_bridge_get_modes(tc->panel_bridge, connector); in tc_connector_get_modes()
1751 drm_edid = tc_edid_read(&tc->bridge, connector); in tc_connector_get_modes()
1764 tc_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) in tc_bridge_detect() argument
1766 struct tc_data *tc = bridge_to_tc(bridge); in tc_bridge_detect()
1771 ret = regmap_read(tc->regmap, GPIOI, &val); in tc_bridge_detect()
1775 conn = val & BIT(tc->hpd_pin); in tc_bridge_detect()
1788 if (tc->hpd_pin >= 0) in tc_connector_detect()
1789 return tc_bridge_detect(&tc->bridge, connector); in tc_connector_detect()
1791 if (tc->panel_bridge) in tc_connector_detect()
1806 static int tc_dpi_bridge_attach(struct drm_bridge *bridge, in tc_dpi_bridge_attach() argument
1810 struct tc_data *tc = bridge_to_tc(bridge); in tc_dpi_bridge_attach()
1812 if (!tc->panel_bridge) in tc_dpi_bridge_attach()
1815 return drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge, in tc_dpi_bridge_attach()
1816 &tc->bridge, flags); in tc_dpi_bridge_attach()
1819 static int tc_edp_bridge_attach(struct drm_bridge *bridge, in tc_edp_bridge_attach() argument
1824 struct tc_data *tc = bridge_to_tc(bridge); in tc_edp_bridge_attach()
1825 struct drm_device *drm = bridge->dev; in tc_edp_bridge_attach()
1828 if (tc->panel_bridge) { in tc_edp_bridge_attach()
1830 ret = drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge, in tc_edp_bridge_attach()
1831 &tc->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR); in tc_edp_bridge_attach()
1839 tc->aux.drm_dev = drm; in tc_edp_bridge_attach()
1840 ret = drm_dp_aux_register(&tc->aux); in tc_edp_bridge_attach()
1845 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs); in tc_edp_bridge_attach()
1846 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, tc->bridge.type); in tc_edp_bridge_attach()
1851 if (tc->hpd_pin >= 0) { in tc_edp_bridge_attach()
1852 if (tc->have_irq) in tc_edp_bridge_attach()
1853 tc->connector.polled = DRM_CONNECTOR_POLL_HPD; in tc_edp_bridge_attach()
1855 tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT | in tc_edp_bridge_attach()
1859 drm_display_info_set_bus_formats(&tc->connector.display_info, in tc_edp_bridge_attach()
1861 tc->connector.display_info.bus_flags = in tc_edp_bridge_attach()
1865 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder); in tc_edp_bridge_attach()
1869 drm_dp_aux_unregister(&tc->aux); in tc_edp_bridge_attach()
1873 static void tc_edp_bridge_detach(struct drm_bridge *bridge) in tc_edp_bridge_detach() argument
1875 drm_dp_aux_unregister(&bridge_to_tc(bridge)->aux); in tc_edp_bridge_detach()
1882 tc_dpi_atomic_get_input_bus_fmts(struct drm_bridge *bridge, in tc_dpi_atomic_get_input_bus_fmts() argument
1898 /* This is the DSI-end bus format */ in tc_dpi_atomic_get_input_bus_fmts()
1906 tc_edp_atomic_get_output_bus_fmts(struct drm_bridge *bridge, in tc_edp_atomic_get_output_bus_fmts() argument
1960 /* DSI D-PHY Layer */ in tc_readable_reg()
2233 r = regmap_read(tc->regmap, INTSTS_G, &val); in tc_irq_handler()
2243 regmap_read(tc->regmap, SYSSTAT, &stat); in tc_irq_handler()
2245 dev_err(tc->dev, "syserr %x\n", stat); in tc_irq_handler()
2248 if (tc->hpd_pin >= 0 && tc->bridge.dev && tc->aux.drm_dev) { in tc_irq_handler()
2255 bool h = val & INT_GPIO_H(tc->hpd_pin); in tc_irq_handler()
2256 bool lc = val & INT_GPIO_LC(tc->hpd_pin); in tc_irq_handler()
2259 dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin, in tc_irq_handler()
2261 drm_kms_helper_hotplug_event(tc->bridge.dev); in tc_irq_handler()
2265 regmap_write(tc->regmap, INTSTS_G, val); in tc_irq_handler()
2272 struct device *dev = tc->dev; in tc_mipi_dsi_host_attach()
2284 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1); in tc_mipi_dsi_host_attach()
2292 return -EPROBE_DEFER; in tc_mipi_dsi_host_attach()
2302 tc->dsi = dsi; in tc_mipi_dsi_host_attach()
2303 dsi->lanes = dsi_lanes; in tc_mipi_dsi_host_attach()
2304 dsi->format = MIPI_DSI_FMT_RGB888; in tc_mipi_dsi_host_attach()
2305 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | in tc_mipi_dsi_host_attach()
2319 struct device *dev = tc->dev; in tc_probe_dpi_bridge_endpoint()
2320 struct drm_bridge *bridge; in tc_probe_dpi_bridge_endpoint() local
2325 ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, &bridge); in tc_probe_dpi_bridge_endpoint()
2326 if (ret && ret != -ENODEV) in tc_probe_dpi_bridge_endpoint()
2328 "Could not find DPI panel or bridge\n"); in tc_probe_dpi_bridge_endpoint()
2331 bridge = devm_drm_panel_bridge_add(dev, panel); in tc_probe_dpi_bridge_endpoint()
2332 if (IS_ERR(bridge)) in tc_probe_dpi_bridge_endpoint()
2333 return PTR_ERR(bridge); in tc_probe_dpi_bridge_endpoint()
2336 if (bridge) { in tc_probe_dpi_bridge_endpoint()
2337 tc->panel_bridge = bridge; in tc_probe_dpi_bridge_endpoint()
2338 tc->bridge.type = DRM_MODE_CONNECTOR_DPI; in tc_probe_dpi_bridge_endpoint()
2348 struct device *dev = tc->dev; in tc_probe_edp_bridge_endpoint()
2353 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &panel, NULL); in tc_probe_edp_bridge_endpoint()
2354 if (ret && ret != -ENODEV) in tc_probe_edp_bridge_endpoint()
2356 "Could not find DSI panel or bridge\n"); in tc_probe_edp_bridge_endpoint()
2365 tc->panel_bridge = panel_bridge; in tc_probe_edp_bridge_endpoint()
2366 tc->bridge.type = DRM_MODE_CONNECTOR_eDP; in tc_probe_edp_bridge_endpoint()
2368 tc->bridge.type = DRM_MODE_CONNECTOR_DisplayPort; in tc_probe_edp_bridge_endpoint()
2371 if (tc->hpd_pin >= 0) in tc_probe_edp_bridge_endpoint()
2372 tc->bridge.ops |= DRM_BRIDGE_OP_DETECT; in tc_probe_edp_bridge_endpoint()
2373 tc->bridge.ops |= DRM_BRIDGE_OP_EDID; in tc_probe_edp_bridge_endpoint()
2385 * Determine bridge configuration. in tc_probe_get_mode()
2388 * port@0 - DSI input in tc_probe_get_mode()
2389 * port@1 - DPI input/output in tc_probe_get_mode()
2390 * port@2 - eDP output in tc_probe_get_mode()
2393 * DPI -> port@1 -> port@2 -> eDP :: [port@0 is not connected] in tc_probe_get_mode()
2394 * DSI -> port@0 -> port@2 -> eDP :: [port@1 is not connected] in tc_probe_get_mode()
2395 * DSI -> port@0 -> port@1 -> DPI :: [port@2 is not connected] in tc_probe_get_mode()
2398 for_each_endpoint_of_node(dev->of_node, node) { in tc_probe_get_mode()
2402 return -EINVAL; in tc_probe_get_mode()
2413 return -EINVAL; in tc_probe_get_mode()
2421 struct device *dev = tc->dev; in tc_probe_bridge_endpoint()
2425 for_each_endpoint_of_node(dev->of_node, node) { in tc_probe_bridge_endpoint()
2428 of_property_read_u8_array(node, "toshiba,pre-emphasis", in tc_probe_bridge_endpoint()
2429 tc->pre_emphasis, in tc_probe_bridge_endpoint()
2430 ARRAY_SIZE(tc->pre_emphasis)); in tc_probe_bridge_endpoint()
2432 if (tc->pre_emphasis[0] < 0 || tc->pre_emphasis[0] > 2 || in tc_probe_bridge_endpoint()
2433 tc->pre_emphasis[1] < 0 || tc->pre_emphasis[1] > 2) { in tc_probe_bridge_endpoint()
2434 dev_err(dev, "Incorrect Pre-Emphasis setting, use either 0=0dB 1=3.5dB 2=6dB\n"); in tc_probe_bridge_endpoint()
2436 return -EINVAL; in tc_probe_bridge_endpoint()
2442 tc->input_connector_dsi = false; in tc_probe_bridge_endpoint()
2445 tc->input_connector_dsi = true; in tc_probe_bridge_endpoint()
2448 tc->input_connector_dsi = true; in tc_probe_bridge_endpoint()
2453 return -EINVAL; in tc_probe_bridge_endpoint()
2458 struct device *dev = &client->dev; in tc_probe()
2467 tc = devm_drm_bridge_alloc(dev, struct tc_data, bridge, funcs); in tc_probe()
2471 tc->dev = dev; in tc_probe()
2477 tc->refclk = devm_clk_get_enabled(dev, "ref"); in tc_probe()
2478 if (IS_ERR(tc->refclk)) in tc_probe()
2479 return dev_err_probe(dev, PTR_ERR(tc->refclk), in tc_probe()
2480 "Failed to get and enable the ref clk\n"); in tc_probe()
2486 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH); in tc_probe()
2487 if (IS_ERR(tc->sd_gpio)) in tc_probe()
2488 return PTR_ERR(tc->sd_gpio); in tc_probe()
2490 if (tc->sd_gpio) { in tc_probe()
2491 gpiod_set_value_cansleep(tc->sd_gpio, 0); in tc_probe()
2496 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); in tc_probe()
2497 if (IS_ERR(tc->reset_gpio)) in tc_probe()
2498 return PTR_ERR(tc->reset_gpio); in tc_probe()
2500 if (tc->reset_gpio) { in tc_probe()
2501 gpiod_set_value_cansleep(tc->reset_gpio, 1); in tc_probe()
2505 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config); in tc_probe()
2506 if (IS_ERR(tc->regmap)) { in tc_probe()
2507 ret = PTR_ERR(tc->regmap); in tc_probe()
2512 ret = of_property_read_u32(dev->of_node, "toshiba,hpd-pin", in tc_probe()
2513 &tc->hpd_pin); in tc_probe()
2515 tc->hpd_pin = -ENODEV; in tc_probe()
2517 if (tc->hpd_pin < 0 || tc->hpd_pin > 1) { in tc_probe()
2519 return -EINVAL; in tc_probe()
2523 if (client->irq > 0) { in tc_probe()
2524 /* enable SysErr */ in tc_probe()
2525 regmap_write(tc->regmap, INTCTL_G, INT_SYSERR); in tc_probe()
2527 ret = devm_request_threaded_irq(dev, client->irq, in tc_probe()
2530 "tc358767-irq", tc); in tc_probe()
2536 tc->have_irq = true; in tc_probe()
2539 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev); in tc_probe()
2541 dev_err(tc->dev, "can not read device ID: %d\n", ret); in tc_probe()
2545 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) { in tc_probe()
2546 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev); in tc_probe()
2547 return -EINVAL; in tc_probe()
2550 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */ in tc_probe()
2552 if (!tc->reset_gpio) { in tc_probe()
2559 regmap_update_bits(tc->regmap, SYSRSTENB, in tc_probe()
2562 regmap_update_bits(tc->regmap, SYSRSTENB, in tc_probe()
2568 if (tc->hpd_pin >= 0) { in tc_probe()
2569 u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT; in tc_probe()
2570 u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin); in tc_probe()
2573 regmap_write(tc->regmap, lcnt_reg, in tc_probe()
2574 clk_get_rate(tc->refclk) * 2 / 1000); in tc_probe()
2576 regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin)); in tc_probe()
2578 if (tc->have_irq) { in tc_probe()
2579 /* enable H & LC */ in tc_probe()
2580 regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc); in tc_probe()
2584 if (tc->bridge.type != DRM_MODE_CONNECTOR_DPI) { /* (e)DP output */ in tc_probe()
2590 tc->bridge.of_node = dev->of_node; in tc_probe()
2591 drm_bridge_add(&tc->bridge); in tc_probe()
2595 if (tc->input_connector_dsi) { /* DSI input */ in tc_probe()
2598 drm_bridge_remove(&tc->bridge); in tc_probe()
2610 drm_bridge_remove(&tc->bridge); in tc_remove()